DE19650509C2 - Vorrichtung und Verfahren zur Beseitigung von falschen Ergebnissen bei der Ausführung von Befehlen - Google Patents

Vorrichtung und Verfahren zur Beseitigung von falschen Ergebnissen bei der Ausführung von Befehlen

Info

Publication number
DE19650509C2
DE19650509C2 DE19650509A DE19650509A DE19650509C2 DE 19650509 C2 DE19650509 C2 DE 19650509C2 DE 19650509 A DE19650509 A DE 19650509A DE 19650509 A DE19650509 A DE 19650509A DE 19650509 C2 DE19650509 C2 DE 19650509C2
Authority
DE
Germany
Prior art keywords
command
indicator
processor
signal
commands
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19650509A
Other languages
German (de)
English (en)
Other versions
DE19650509A1 (de
Inventor
Gregg Lesartre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of DE19650509A1 publication Critical patent/DE19650509A1/de
Application granted granted Critical
Publication of DE19650509C2 publication Critical patent/DE19650509C2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3865—Recovery, e.g. branch miss-prediction, exception handling using deferred exception handling, e.g. exception flags
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/1407—Checkpointing the instruction stream

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Advance Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE19650509A 1996-03-01 1996-12-05 Vorrichtung und Verfahren zur Beseitigung von falschen Ergebnissen bei der Ausführung von Befehlen Expired - Fee Related DE19650509C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/609,807 US5838942A (en) 1996-03-01 1996-03-01 Panic trap system and method

Publications (2)

Publication Number Publication Date
DE19650509A1 DE19650509A1 (de) 1997-09-04
DE19650509C2 true DE19650509C2 (de) 2002-02-28

Family

ID=24442416

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19650509A Expired - Fee Related DE19650509C2 (de) 1996-03-01 1996-12-05 Vorrichtung und Verfahren zur Beseitigung von falschen Ergebnissen bei der Ausführung von Befehlen

Country Status (4)

Country Link
US (1) US5838942A (enExample)
JP (1) JP3715057B2 (enExample)
DE (1) DE19650509C2 (enExample)
GB (1) GB2310742B (enExample)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6892294B1 (en) 2000-02-03 2005-05-10 Hewlett-Packard Development Company, L.P. Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor
US11886377B2 (en) * 2019-09-10 2024-01-30 Cornami, Inc. Reconfigurable arithmetic engine circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420990A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
GB2284493A (en) * 1993-12-01 1995-06-07 Intel Corp Exception handling with speculative out-of-order instruction execution.

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990010267A1 (en) * 1989-02-24 1990-09-07 Nexgen Microsystems Distributed pipeline control for a computer
US5280615A (en) * 1990-03-23 1994-01-18 Unisys Corporation Out of order job processing method and apparatus
JP2642529B2 (ja) * 1991-04-30 1997-08-20 株式会社東芝 並列プロセッサーの命令分配処理装置
US5630157A (en) * 1991-06-13 1997-05-13 International Business Machines Corporation Computer organization for multiple and out-of-order execution of condition code testing and setting instructions
US5345569A (en) * 1991-09-20 1994-09-06 Advanced Micro Devices, Inc. Apparatus and method for resolving dependencies among a plurality of instructions within a storage device
JPH0820949B2 (ja) * 1991-11-26 1996-03-04 松下電器産業株式会社 情報処理装置
WO1994008287A1 (en) * 1992-09-29 1994-04-14 Seiko Epson Corporation System and method for handling load and/or store operations in a superscalar microprocessor
US5467473A (en) * 1993-01-08 1995-11-14 International Business Machines Corporation Out of order instruction load and store comparison
US5627985A (en) * 1994-01-04 1997-05-06 Intel Corporation Speculative and committed resource files in an out-of-order processor
US5524263A (en) * 1994-02-25 1996-06-04 Intel Corporation Method and apparatus for partial and full stall handling in allocation
US5546597A (en) * 1994-02-28 1996-08-13 Intel Corporation Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
US5584037A (en) * 1994-03-01 1996-12-10 Intel Corporation Entry allocation in a circular buffer
US5546599A (en) * 1994-03-31 1996-08-13 International Business Machines Corporation Processing system and method of operation for processing dispatched instructions with detected exceptions
US5649225A (en) * 1994-06-01 1997-07-15 Advanced Micro Devices, Inc. Resynchronization of a superscalar processor
US5625789A (en) * 1994-10-24 1997-04-29 International Business Machines Corporation Apparatus for source operand dependendency analyses register renaming and rapid pipeline recovery in a microprocessor that issues and executes multiple instructions out-of-order in a single cycle
US5625835A (en) * 1995-05-10 1997-04-29 International Business Machines Corporation Method and apparatus for reordering memory operations in a superscalar or very long instruction word processor

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420990A (en) * 1993-06-17 1995-05-30 Digital Equipment Corporation Mechanism for enforcing the correct order of instruction execution
GB2284493A (en) * 1993-12-01 1995-06-07 Intel Corp Exception handling with speculative out-of-order instruction execution.

Also Published As

Publication number Publication date
GB9702535D0 (en) 1997-03-26
GB2310742A (en) 1997-09-03
DE19650509A1 (de) 1997-09-04
GB2310742B (en) 2000-09-13
US5838942A (en) 1998-11-17
JPH09244895A (ja) 1997-09-19
JP3715057B2 (ja) 2005-11-09

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: HEWLETT-PACKARD CO. (N.D.GES.D.STAATES DELAWARE),

D2 Grant after examination
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: HEWLETT-PACKARD DEVELOPMENT CO., L.P., HOUSTON, TE

R119 Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee

Effective date: 20110701