JPH09238352A - Image coder and image decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration in a reproduced image by correcting an error with respect to occurrence of the error in decoding of variable length coding data so as to detect the data. SOLUTION: A digital image signal via an A/D converter circuit 402 is given to a block division circuit 403, in which one image pattern is divided and processed in parallel. Then an error check code is added to variable length coded data from a high efficiency coding circuit 404, a formatter 405 is used to pack the code to a fixed length transmission block and the resulting block is given to a synchronizing signal detection circuit 408 via a transmission line 407. In the circuit 408, transmission synchronization is taken and the data are stored in a memory 409 and an error correction circuit 410 corrects an error on the transmission line 407. Then the ata are decoded to an original block signal by a high efficiency decoding circuit 412 via an ID detector 411. The block signal is outputted as an analog signal via an LS conversion circuit 443 and a D/C conversion circuit 414. Thus, even on the occurrence of an error in the decoding of variable length coding data, data are detected and deterioration in the reproduced image is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of an image coding apparatus and an image decoding apparatus for highly efficiently coding / decoding image data using motion compensation predictive coding.

[0002]

2. Description of the Related Art In recent years, high-efficiency coding such as predictive coding and DCT (Discrete Cosine Transform) has been carried out as a means for coding moving images, and in order to further improve coding efficiency, the correlation in the time direction of images has been improved. The mainstream is the transmission method that detects the motion vector between consecutive frames and fields and compensates the motion based on it by using it, and controls the data generation amount of the variable length coded data within a certain range. Has become.

FIG. 4 is a block diagram showing a schematic configuration of an image coding / decoding device using this motion compensation predictive coding.

In FIG. 4, an analog image signal is input to the input terminal 301 and is converted into a digital signal by the A / D conversion circuit 302.

The digitized image signal is converted into a block of m pixels in the horizontal direction and n lines in the vertical direction by a block division circuit 303, for example, m = n as shown in FIG.
= 8, that is, it is divided into blocks in units of 8 × 8 pixels, and further converted into MDU block data composed of data of luminance signals of 16 × 16 pixels and color signals of 16 × 8 pixels. Further, as shown in FIG. 5B, 15 MDU blocks are set as 1 MDU_LINE, and one screen is divided into 8 Phases for parallel processing.

The block signal divided for each phase is the high efficiency encoding circuit 3 of FIG. 4 for each phase.
It is encoded in 04, and the amount of information is reduced. In the encoding circuit 304, motion compensation predictive encoding is performed in order to improve encoding efficiency, and the encoded data is output in a format as shown in FIG. 6A, for example.

Here, the motion information written in ID1 indicates motion mode information and a motion vector.

The ID1 and the variable length coded data are shown in FIG.
Of the formatter 305. Formatter 30
In Fig. 5, the above-mentioned ID1 and variable length coded data are sequentially packed in a fixed length transmission block as shown in Fig. 6B,
The presence / absence of ID1 in the inner code string, the position information when ID1 is present, and the error detection code are written in ID2. Further, a synchronization signal for transmission synchronization is added, error correction coded by the error correction coding circuit 306 in FIG. 4, and sent to the transmission line 307.

On the receiving side, the data transmitted through the transmission path 307 is transmission-synchronized by the synchronization detection circuit 308, and the memory 3
It is stored in 09. The error correction circuit 310 corrects the error generated on the transmission line 307 with respect to the stored data. The data in which the code error is corrected is output from the memory 309 and supplied to the ID detection circuit 311. I
In the D detection circuit 311, the ID is detected from the error detection result of ID2.
1 presence / absence determination and position are detected, and MDU_L is stored in ID1.
INE No. And Phase No. To the high-efficiency decoding circuits (1 to 8) 312 for each Phase from the variable length coded data.

In the high efficiency decoding circuit 312, the original block signal is decoded by the processing opposite to that of the high efficiency encoding circuit 304 described above. This block signal is the LS conversion circuit 3
It is converted into a digital signal having a line scan structure at 13, and is converted into an analog signal at the D / A conversion circuit 314 and output to the output terminal 315.

A detailed block diagram of the ID detection circuit 311 is shown in FIG.

Data corrected for code error is input from the memory 309 of FIG. 4 from the input terminal 201 of FIG.
ID2 error detection circuit 202 and ID2 changeover switch 20
3.

The ID2 error detection circuit 202 detects an error in the ID2 and controls the ID2 changeover switch 203 according to the detection result.

If there is an error, the ID2 changeover switch 20
3 is switched to the b terminal, and at this time, the data changeover switch 211 is also switched to the b terminal, so that the input data is directly output to the output terminal 212. When there is no mistake,
The ID2 switch 203 is switched to the end a, and the input data is supplied to the ID1 presence / absence detection circuit 204 and the ID1 switch 205.

The ID1 presence / absence detection circuit 204 controls the ID1 changeover switch 205 according to the detection result of the presence / absence of ID1.

When there is no ID1, the ID1 changeover switch 2
05 is switched to the b terminal, and at this time, the data changeover switch 211 is also switched to the b terminal, so that the input data is directly output to the output terminal 212. When ID1 is present, the ID1 changeover switch 205 is switched to the end a,
The input data is supplied to the ID1 position detection circuit 206.

The ID1 position detection circuit 206 detects the symbol position on the transmission format where the ID1 written in the ID2 is located, and uses the symbol information as the ID1.
No. The signals are supplied to the detection circuit 208, the counter 209, the data changeover switch 211 and the ID1 Flag Check circuit 207, respectively.

ID1 No. In the detection circuit 208, ID
1 written in MDU_LINE No. 1 And Phase No. Is detected and ID1 No. It is supplied to the changeover switch 210, and in the counter 209, MDU_L
INE No. And Phase No. Are sequentially counted up, and these pieces of information are recorded as ID1 No. Changeover switch 2
Supply to 10.

In the ID1 Flag Check circuit 207, the ID1
The error flag of the symbol is checked from the symbol information from the position detection circuit 206, and the ID is determined by the result.
1No. The changeover switch 210 is controlled.

If there is an error, ID1 No. The changeover switch 210 is changed over to the terminal b, and the counter 209
Is supplied to the data changeover switch 211, and when there is no error, ID1 No. The changeover switch 210 is changed over to the a terminal, and the ID1 No. The output of the detection circuit 208 is supplied to the data changeover switch 211.

The data changeover switch 211 is controlled by the symbol information from the ID1 position detection circuit 206, and switches between the variable length coded data and the ID1 information to output the output terminal 2.
Output to 12.

[0022]

In the image data decoding method in the high-efficiency coding / decoding apparatus as described above,
Good decoding cannot be performed when an uncorrectable error occurs.
For example, in the ID detection circuit 311, when an error remains in ID2, the error is detected by the error detection code in ID2. Therefore, the data is supplied as it is to the high-efficiency decoding circuit 312 in the next stage, and if ID1 is present in the inner code string, the data for 1 MDU_LINE is lost.

When erroneous detection occurs due to the error detection code in ID2, the correct ID1 cannot be detected, and the correctly decoded data may be destroyed.

Furthermore, when an error remains in ID1, the ID
If the flag in the 1Flag Check circuit 207 is correct, it can be protected by the counter 209. However, if the flag is incorrect due to erroneous detection and correction, the correct ID1 cannot be detected and there is a risk that the correctly decoded data will be destroyed. is there.

In the above case, the decoded image is 1 MDU.
Since an error more than _LINE occurs on the screen, the reproduced image is very unsightly.

(Object of the Invention) An object of the present invention is to provide an image coding apparatus and an image decoding apparatus capable of minimizing the deterioration of the quality of a reproduced image even when an error occurs on a transmission line. To do.

[0027]

In order to achieve the above object, according to the present invention, an image coding apparatus for variable-length coding a block-coded image signal in a plurality of coding modes, wherein the block Error detection coding means for performing error detection coding on the coding mode information for the, the variable length coded image information, the coding mode information, and the first error detection code as a first information string. Means, a second information string generating means for fixing the multiplexed plurality of first information strings to a fixed length, and a boundary information adding means for the plurality of first information strings. A second error detection coding means for the boundary information; a means for multiplexing the second information sequence, the boundary information and the second error detection code as a third information sequence; The third error for the information sequence of Means for detection coding or error correction coding, and the structure provided with a transmission synchronization adding means, the coding mode information includes a coding mode and motion information and the address on the screen.

Also in order to achieve the above object, according to the present invention, the boundary information adding means for the first information sequence, if not present on the second information code sequence for adding the boundary information, Number of information columns up to the second information sequence where the boundary of the first information sequence exists and an address on the second information sequence where the boundary of the next first information sequence exists In the image decoding device for decoding the coded image data by the image coding device provided with the boundary information adding means,
The first error detecting means for detecting an error of the second error detecting code, the boundary information detecting means for the first information string, the first error detecting means, and the boundary information detecting means for the first information string. Means for determining the boundary of the first information string based on the result, second error detecting means for detecting an error of the first error detecting code, and switching means for switching the output according to the result of the first error detecting means. Is provided.

In order to achieve the above object, according to the present invention, in the image decoding apparatus for decoding image data by the image coding apparatus according to claim 2, the error of the second error detecting code is First error detecting means for detecting
No. 1 according to the result of the boundary information detecting means of the information string, the first error detecting means and the boundary information detecting means of the first information string.
Means for determining the boundary of the information sequence, second error detecting means for detecting an error in the first error detecting code, coding mode and motion information detecting means on the coding mode information, and coding mode information. The address detecting means on the upper screen, the counting means for counting the boundary value from the boundary detecting result of the first information sequence, and the output of the address detecting means and the counting means on the screen according to the result of the second error detecting means. The first switching means for switching and the second switching means for switching the output of the image information according to the result of the means for determining the boundary of the first information string are provided.

Also in order to achieve the above object, according to the present invention, in the image decoding apparatus for decoding the image data by the image coding apparatus according to claim 3, the error of the second error detecting code is First error detecting means for detecting
No. 1 according to the result of the boundary information detecting means of the information string, the first error detecting means and the boundary information detecting means of the first information string.
Means for determining the boundary of the information sequence, second error detecting means for detecting an error in the first error detecting code, coding mode and motion information detecting means on the coding mode information, and coding mode information. The address detecting means on the upper screen, the counting means for counting the boundary value from the boundary detecting result of the first information sequence, and the output of the address detecting means and the counting means on the screen according to the result of the second error detecting means. The first switching means for switching and the second switching means for switching the output of the image information according to the result of the means for determining the boundary of the first information string are provided.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on illustrated embodiments.

FIG. 1 is a block diagram showing a schematic configuration of an image data encoding / decoding device according to an embodiment of the present invention.

In FIG. 1, an analog image signal is input to the input terminal 401 and converted into a digital signal by the A / D conversion circuit 402.

The digitized image signal is processed by a block dividing circuit 403 into blocks each having m pixels in the horizontal direction and n lines in the vertical direction, for example, m as shown in FIG.
= N = 8, that is, it is divided into blocks of 8 × 8 pixels,
Further, the luminance signal is converted into MDU block data composed of data of 16 × 16 pixels and the color signal of 16 × 8 pixels. Further, as shown in FIG. 5B, 15 MDU blocks are set as 1 MDU_LINE, and 1 screen is set to 8 Phases.
It is divided into e and processed in parallel.

The block signal divided for each phase is the high efficiency encoding circuit 4 of FIG. 1 for each phase.
It is encoded in 04, and the amount of information is reduced. In the encoding circuit 404, motion compensation predictive encoding is performed in order to improve encoding efficiency, and the encoded data is output in a format as shown in FIG. 2A, for example.

Here, the motion information written in ID1 indicates motion mode information and a motion vector, and an error detection code is added.

The ID1 and the variable length coded data are shown in FIG.
Of the formatter 405. Formatter 40
In 5, the ID1 and the variable length coded data described above are sequentially packed in a fixed length transmission block as shown in FIG.

LINE in which ID1 exists in ID2
No. And ID1 symbol position information and error detection code are written. For example, LINE No. In the same LINE, "0" is written when ID1 exists, and when ID1 does not exist, the number of LINEs up to the next ID1 is written. When the ID1 exists, the symbol position is written in the symbol position information, and when the ID1 does not exist, the next symbol position of the ID1 is written.

Further, a sync signal for transmission synchronization is added, and the error correction coding circuit 406 of FIG. 1 performs error correction coding and sends out to the transmission line 407.

On the receiving side, the data transmitted through the transmission line 407 is transmission-synchronized by the synchronization detection circuit 408, and the data is stored in the memory 4
It is stored in 09. The error correction circuit 310 corrects the error generated on the transmission line 407 to the stored data. The data in which the code error is corrected is output from the memory 409 and supplied to the ID detection circuit 411. I
In the D detection circuit 411, the ID is detected from the error detection result of ID2.
1 is detected and the MDU_LINE No. in ID1 is detected. And P
case No. To the high-efficiency decoding circuit 412 for each Phase from the variable-length coded data.

The high-efficiency decoding circuit 412 decodes the original block signal by a process opposite to that of the high-efficiency encoding circuit 404 described above. This block signal is supplied to the LS conversion circuit 4
It is converted into a digital signal having a line scan structure at 13, and is converted into an analog signal at the D / A conversion circuit 414 and output to the output terminal 415.

FIG. 3 is a block diagram showing a schematic configuration of the ID detection circuit 411 shown in FIG. 1. The operation here will be described in detail below.

Data corrected for code error is input from the memory 409 of FIG. 1 from the input terminal 101 of FIG.
ID2 error detection circuit 102 and ID1_LINE N
o. It is supplied to the detection circuit 103.

The ID2 error detection circuit 102 detects an error in the ID2 and supplies the detection result to the ID1 position determination circuit 104. Also, at the same time, ID1_LINE
No. The detection result of the detection circuit 103 is also supplied to the ID1 position determination circuit 104.

The ID1 position determination circuit 104 selects ID2 having no error, that is, the ID2 error detection circuit 102.
ID1_LINE from the block determined to have no error in
No. Based on the detection result of the detection circuit 103, the symbol position of ID1 is detected, and when this can be confirmed, the ID1 error detection circuit 105, MDU_LINE No. & Pha
se No. It is supplied to the detection circuit 106 and the counter 107.

MDU_LINE No. & Phase
No. In the detection circuit 106, the MDU_LINE No. written in the ID1. And Phase No. Is detected and ID1 No. The signal is supplied to the terminal a of the changeover switch 108, and the counter 107 outputs the MDU_LINE No. And Phase No. Is incremented sequentially and ID1
No. It is supplied to the terminal b of the changeover switch 108.

The ID1 error detection circuit 105 detects an error from the error detection code added in the ID1, and the ID1 No. The changeover switch 108 is controlled.

When there is an error, ID1 No. The changeover switch 108 is changed over to the terminal b, the output of the counter 107 is supplied to the ID changeover switch 112, and when there is no error, the ID1 No. The changeover switch 108 is changed over to the end a, and the ID1 No. The output of the detection circuit 106 is I
It is supplied to the D changeover switch 112.

Next, when the ID1 position is not determined in the ID1 position determination circuit 104, that is, when all the ID2s have an error for one ID1, the ID1 search circuit 1
The data is sequentially searched by 09, and the ID1 CRC check circuit 110 detects an error. When there is an error, the next data is searched, and when there is no error, MDU_LINE
No. And Phase No. The check circuit 111 performs a pattern check of whether the data is ID1. If it is not ID1, the data is searched again, and ID1
When it is determined that it is supplied to the ID changeover switch 112.

The ID changeover switch 112 is controlled by the judgment result of the ID1 position judgment circuit 104, and is switched to the a terminal when the ID1 position is fixed and to the b terminal when the ID1 position is not fixed.

The determination circuit 113 is the ID1 position determination circuit 1
04 result and MDU_LINE No. & Phase check circuit 111 results from data switch 114
Control.

The data changeover switch 114 is controlled by the symbol information from the decision circuit 113 as described above, and switches between the variable length coded data and the ID1 information to output the output terminal 1.
15 is output.

With the above configuration, for example, ID
In the detection circuit 411, when an error remains in the ID2, the error is detected by the error detection code in the ID2, but the ID1 can be detected from other ID2.
Even when erroneous detection occurs due to the error detection code in 2, ID1 can be detected from other ID2.

If all ID2 have an error, ID1 can be detected by searching all the data.
Further, by adding an error detection code to ID1, accurate ID1 can be detected.

[0055]

As described above, according to the present invention,
When decoding variable-length coded data, an error that exceeds the correction capability occurs, and even when an error remains in the boundary information of the variable-length coded data on the fixed-length format, the variable-length coded data can be accurately encoded. It becomes possible to detect data, and it is possible to prevent deterioration of the reproduced image after decoding the variable length coded data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an image data encoding / decoding device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a variable length code format and a fixed length transmission format according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of an ID detection circuit in FIG.

FIG. 4 is a block diagram showing a schematic configuration of a conventional image data encoding / decoding device.

FIG. 5 is a diagram showing a data block format.

FIG. 6 is a diagram showing a variable length code format and a fixed length transmission format according to a conventional example.

7 is a block diagram showing a configuration example of an ID detection circuit of FIG.

[Explanation of symbols]

102 error detection circuit 103 ID1_LINE No. Detection circuit 104 ID1 position determination circuit 105 ID1 error detection circuit 106 MDU_LINE No. & PhaseN
o. Detection circuit 107 Counter 108 ID1 No. Changeover switch 109 ID1 search circuit 110 ID1 CRC check circuit 111 MDU_LINE No. & PhaseN
o. Detection circuit 112 ID changeover switch 113 Judgment circuit 114 Data changeover switch 404 High efficiency coding circuit 406 Error coding circuit 410 Error correction circuit 411 ID detection circuit 412 High efficiency decoding circuit

Claims (6)

[Claims] 1. An image coding apparatus for variable-length coding a block-coded image signal in a plurality of coding modes, comprising: first error detection coding for error-detecting coding mode information for the block. Means and means for multiplexing the variable length coded image information, the coding mode information and the first error detection code as a first information sequence,
Second information sequence generating means for fixing the plurality of multiplexed first information sequences to a fixed length, boundary information adding means for the plurality of first information sequences, and first boundary information adding means for the boundary information. Second error detection coding means, means for multiplexing the second information sequence, the boundary information and the second error detection code as a third information sequence, and a third information sequence for the third information sequence. 3. An image coding apparatus comprising the error detection coding or error correction coding unit 3 and the transmission synchronization adding unit. 2. The image coding apparatus according to claim 1, wherein the coding mode information includes a coding mode, motion information, and an address on a screen. 3. The boundary information adding means for the first information string, if not present on the second information code string to which the boundary information is added, has a boundary for the next first information string. 3. The image coding apparatus according to claim 1, wherein the number of information rows up to the information row and the address on the second information row where the boundary of the next first information row exists are added. 4. An image decoding device for decoding the image data encoded by the image encoding device according to claim 1, wherein the first error detecting means detects an error of the second error detecting code. A first information string boundary information detecting means; a means for determining a boundary of the first information string based on the results of the first error detecting means and the first information string boundary information detecting means; 2. An image data decoding device, comprising: a second error detecting means for detecting an error of the error detecting code and a switching means for switching an output according to a result of the first error detecting means. 5. An image decoding device for decoding image data encoded by the image encoding device according to claim 2, wherein the first error detecting means detects an error of the second error detecting code. A first information string boundary information detecting means; a means for determining a boundary of the first information string based on the results of the first error detecting means and the first information string boundary information detecting means; Second error detecting means for detecting an error in the error detecting code, the encoding mode and motion information detecting means on the encoding mode information, the address detecting means on the screen on the encoding mode information, and the first Counting means for counting the boundary value from the boundary detection result of the information string, first switching means for switching the output of the address detecting means and the counting means on the screen according to the result of the second error detecting means, and the first information string. By the result of the means of establishing the boundaries of Image decryption apparatus characterized in that a second switching means for switching the output of the image information. 6. An image decoding device for decoding the image data encoded by the image encoding device according to claim 3, wherein the first error detecting means detects an error of the second error detecting code. A first information string boundary information detecting means; a means for determining a boundary of the first information string based on the results of the first error detecting means and the first information string boundary information detecting means; Second error detecting means for detecting an error in the error detecting code, the encoding mode and motion information detecting means on the encoding mode information, the address detecting means on the screen on the encoding mode information, and the first Counting means for counting the boundary value from the boundary detection result of the information string, first switching means for switching the output of the address detecting means and the counting means on the screen according to the result of the second error detecting means, and the first information string. By the result of the means of establishing the boundaries of Image decryption apparatus characterized in that a second switching means for switching the output of the image information.