JPH09238144A - Atm switching system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM switching system constituting a high-speed large- capacity ATM switch by using a low-speed memory for a method for constituting the switch of an ATM exchange network. SOLUTION: In the ATM switching system, there is provided with common output type cross point buffer sections respectively provided with filters 2 which only pass effective cells addressed to relevant output highways, sorting switches 3 which transfer the cells by selectively connecting a plurality of input ports to a plurality of output ports, buffer sections 4 to which addresses are give in the rising order in both the column and row directions, and multiplexing sections 5 which output the cells read out from the sections 4 in a multiplexing way in corresponding to a plurality of output highways. The sorting switches 3 successively write data in parallel effective cells in the ascending order of addresses from the memory corresponding to the leading edge of the vacant addresses of the buffer sections 4, successively read out the effective cells from the address '0', and output the cells to relevant output highways in multiplexing states.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode) The present invention relates to a method of configuring a switch in a switching network, and particularly to a method of configuring a high speed and large capacity ATM switch.

The ATM communication system is a communication mode in which various media such as voice, data, and images are transferred in a unified manner using fixed-length packets (cells).
At various stages, small-scale commercial services targeting narrow-band services such as trial systems and data have been launched, but in the future, large-scale services including broadband information such as image communication will be available. Is desired,
Therefore, development of a large capacity and high speed ATM switch is required.

The ATM switch uses a low-speed device (especially memory) without increasing the buffer capacity.
It is necessary to be able to configure a high-speed, large-capacity switch.

[0004]

2. Description of the Related Art In an ATM switch, cells arrive asynchronously, so a buffer memory for waiting is required. Regarding the location of the buffer memory in this case, the following four types are typical as typical configurations. (1) Common buffer type switch (2) Input buffer type switch (3) Output buffer type switch (4) Crosspoint type switch

FIG. 8 shows an arrangement method of buffer memories in an ATM switch. (A) is a common buffer type switch, (b) is an input buffer type switch,
(c) shows an output buffer type switch, and (d) shows a crosspoint type switch.

The crosspoint type switch has a structure in which a cell buffer for waiting is arranged at each crosspoint position of the input / output highway (HW). At an ATM switch, traffic from one input highway to one output highway may temporarily increase because cells arrive asynchronously. Therefore, in the crosspoint type switch, all cell buffers must have a capacity that can withstand a temporary increase in traffic.

The input buffer type switch installs a cell buffer common to all output highways for each input highway. That is, in the crosspoint type buffer, among the buffers that are individually installed, the horizontally arranged buffers (for example, # 1-1 to 1-n) are
It has a configuration of one common memory.

In an ATM switch, the traffic from one input highway to some output highways may increase temporarily, but the traffic from one input highway to all output highways does not increase. In the input buffer type switch, since the buffer for waiting for all output highways is shared for each input highway, compared with the crosspoint type buffer,
The buffer amount can be reduced as a whole.

The output buffer type switch has a structure in which a buffer common to all input highways is installed for each output highway. That is, in the cross-point type buffer, among the buffers that are individually installed, vertically arranged buffers (for example, # 1-1 to # n-1)
Is a common memory. Therefore, for the same reason as in the case of the input buffer type switch, it is possible to reduce the buffer amount as a whole as compared with the cross point type.

The common buffer type switch has a structure in which a common buffer is installed for all input / output highways.
Therefore, the buffer can be shared for a temporary increase in the traffic of all I / O.
The effect of reducing the buffer amount is the largest.

[0011]

In the crosspoint type switch, all cell buffers must have a capacity that can withstand a temporary increase in traffic, and the problem that the overall capacity increases increases. is there. The common buffer type switch and the output buffer type switch are not suitable for a large-capacity and high-speed switch because it is necessary to multiplex the highways in front of or in front of the buffer to increase the speed.

Further, in the input buffer type switch, it is necessary to schedule the reading of the buffer so that the collision of the ATM cells read from the buffer does not occur, which complicates the processing and at present there is no efficient scheduling method. Therefore, there is generally a problem that the throughput of the switch decreases.

The present invention is intended to solve such a problem of the prior art, and to realize a switch capable of performing high speed processing in an ATM switch while suppressing an increase in a buffer amount as much as possible. The purpose of the present invention is to provide an ATM switch system.

[0014]

In the ATM switch system of the present invention, a buffer memory (1 to m) is installed in parallel for each output highway, and each of the N input highways is placed in parallel with the buffer memory. A cell sorting switch is installed between and. In this case, the operating speed of the memory is generally slower than the operating speed of the logic, so N ≦ m.

If the ATM switch of the present invention is m = N
And there is no sorting switch, it corresponds to a crosspoint type buffer. As described above, by operating the vertically arranged buffers in the crosspoint type buffer as if they were the output type buffers, it is possible to achieve both reduction of the buffer amount and high speed.

Specific means for solving the problems of the present invention will be given below.

(1) Each of the filter 2 and the filter 2 which has an input / output port corresponding to a plurality of input highways and passes only valid cells to the corresponding output highway among the input cells from the plurality of input highways. A sorting switch 3 for selectively connecting an input port corresponding to an output port and a plurality of output ports to transfer cells
A plurality of memory cells each of which stores information for one cell are arranged in parallel corresponding to each output port of the sorting switch 3, and each memory element sequentially increases in the column direction. , An output common type cross composed of a buffer unit 4 which is given addresses in ascending order from 0 so as to be sequentially and repeatedly increased in the row direction, and a multiplexing unit 5 which multiplexes and outputs the cells read from the buffer unit 4. A point buffer unit is provided for multiple output highways,
In each output common type cross point buffer unit, the sorting switch 3 sequentially addresses the valid cells input from the filter 2 from the output port connected to the memory corresponding to the beginning of the empty address of the buffer unit 4 for each output port. The cells are rearranged in ascending order and are written in parallel in a plurality of memories of the buffer unit 4, and the multiplexing unit 5 multiplexes cells read out in an address order from the plurality of memories in a predetermined format and outputs the cells to a corresponding output highway.

(2) In the case of (1), when the number of input highways and the number of output highways are two, the sorting switch 3 and the matrix switch 3 ₁ which can switch between the input and output ports to the cross or straight state. It has a valid cell detection / control unit 3 ₂ that determines valid cells in each of the two input ports, and a holding register 3 ₃ that holds information on whether the beginning of an empty address of the buffer unit 4 is an even number or an odd number. , With the beginning of the empty address odd,
If a valid cell to the input port corresponding to the matrix-switch 3 ₁ of the even address arrives, or if a valid cell to both input ports of the matrix switch 3 ₁ arrives, or in the state top even the vacant address, the matrix set the matrix switch 3 ₁ to the state of the cross if a valid cell to the input port corresponding to the odd-numbered address of the switch 3 ₁ arrives, otherwise, to set the matrix switch 3 ₁ to the state of the straight.

(3) In the case of (1), when the number of input highways and the number of output highways each consist of arbitrary N, the sorting switch 3 sets the address offset value L (k) from the beginning of the empty address to the memory. An address offset value calculation unit 11 for calculating, a valid cell number calculation unit 12 for calculating the number x of valid cells arriving simultaneously from a plurality of input ports, and a cell input port number calculation for calculating an input port number y at which valid cells arrive Part 14 and offset value L
Match detection unit 1 that detects a match between (k) and the number x of valid cells
5, accommodates a control unit ₃₅ that includes a selected port number calculation unit 16 for outputting a selection port SEL (k) latches the input port number y of time coincidence detection, each input port, the input port A selector 3 ₄ for selecting an input port according to the selection number SEL (k) is provided.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows the basic structure of an ATM switch of the present invention. In the figure, 1 _0-1
N-1 is an output common type crosspoint buffer unit,
The output highways # 0 to # (N-1) are installed respectively.

Crosspoint buffer unit 1 for each output common type
₀ to 1 _N-1 includes a filter 2, respectively, and the sorting switch 3, the memory (# 0) that is installed in parallel 4 ₀ -
The buffer unit 4 is composed of (# (m-1)) 4 _m-1 and the multiplexing unit 5.

The filter 2 has a function of passing only valid cell information to the corresponding outgoing line among the input cells from each input highway. In the buffer unit 4 composed of m memories, the address 0 of the # 0 memory is the whole address 0, the address 0 of the # 1 memory is the whole address 1, ...,
# (M-1) Address 0 of the memory is the entire address (m
-1), the address 0 of the # 1 memory is the entire address m,
Addresses are assigned according to the rule "...". However, it is assumed that one address can store information for one cell.

In the buffer section 4, a maximum of m valid cell data input from the sorting switch 3 are simultaneously written in parallel. In addition, for reading, one cell is read from the # 0 memory in the order of addresses.

The sorting switch 3 connects valid cell data of cells input from the input highways # 0 to # (N-1) to a memory corresponding to the beginning of an empty address in the buffer unit 4. , From the output port of the sorting switch to each output port,
It has a function of sorting and outputting in ascending order of addresses.

FIG. 2 shows the structure of an output buffer type switch which is logically equivalent to the ATM switch of the present invention. In the ^{_{figure, 1 0 '~1 N-1}} ' is an output common cross-point buffer, respectively multiplexing unit 6 consists of a memory 7.

FIG. 3 shows an embodiment (1) of the present invention, showing a sorting switch section when N = m = 2, where (a) is a configuration example and (b) is an operation example. Is. As shown in the figure, the sorting switch unit 3 is composed of a 2 × 2 matrix switch 3 ₁ , a valid cell detection / control unit 3 ₂ and a holding register 3 ₃ which holds an empty start address of the buffer memory. . The holding register 3 ₃ holds 1-bit information indicating whether it is an even number or an odd number.

In the initial state, since the empty top address is 0, the holding register also holds 0 (even number). When a valid cell having the destination of the output highway arrives only in the input highway # 1 in the first cycle, as shown in FIG.
As shown in (b), the switch is in the cross state and the arriving cell is written to the address 0 of the # 0 memory (and hence the address 0 of the whole memory). The next start address is
Inversion (that is, the holding register of the free top address is 1
(Odd)).

In the next cycle, when a valid cell having the destination of the output arrives only at the input highway # 0, the switch remains in the cross state as shown in FIG. 3 (b) and arrives. The cell is written to address 0 of the # 1 memory (and thus the overall address 1). Further, the next start address is inverted (that is, the holding register of the empty start address is set to 0 (even number)).

In the next cycle, # 0 and # 1 of the input highway
If the valid cells with the destination of the output arrive at the same time, the switch changes to the straight state and the cells from the input highway # 0 are
0 memory is written to address 1 (and therefore overall address 2), and cells from input highway # 1 are
It is written to memory at address 1 (and therefore at address 3).

Thereafter, by performing the same operation, 2
The memories installed in parallel operate logically as one buffer memory.

FIG. 4 shows another principle structure of the present invention, which is another sort of sorting switch when the number of input highways and the number of memories installed in parallel are more generally N. The structural example is shown.

Now, the number of input highways = the number of parallel memories =
N input / output port number = i (k) / o (k) where 0 ≦ k ≦ (N−1) buffer free start address = j where 0 ≦ j ≦ (N−1), each output Letting L (k) be the distance from the empty start address of port [o (k)] (corresponding to the offset from the empty start address of the memory connected to each output port), L (k) is It is expressed by the following formula. When k <j l (k) = (k + N) -j ... When k ≧ j l (k) = k-j.

At this time, when x valid cells arrive in a certain period, the input port number [SEL (k)] selected by each output port is expressed by the following equation. When L (k) ≦ x SEL (k) = f (L (k)) ... When L (k)> x SEL (k) None (No input port is selected) ... However, f (y) is , Counting from the lowest number of input ports, y
The input port number having the th valid cell is shown.

FIG. 5 shows an example of selecting each output port in the sorting switch having the configuration shown in FIG. 4, where N = m = 4 and j = 2, and input ports i (0), i.
When cells arrive at (1) and i (3) at the same time (thus, x = 3, f (0) = 0, f (1) = 1, f (2) =
3 (without f (4)). in this case,~
From the formula, as shown in the table in FIG. 5, the corresponding input port is selected in each output port.

[0035] Figure 6, there is shown an embodiment of the present invention (2), when the operation principle shown in Fig. 4, shows a circuit configuration example of the entire sorting switch unit, 3 ₄ input ports selector for selecting, ₃₅ is a control unit for the selector 3 _4.

In FIG. 6, the selector 3 _4, the controller 3
Select the input port according to the instructions from ₅ . Control unit 3
₅ determines the input port number [SEL (k)] to be selected based on the expressions (1) to (5). Valid / invalid flag (C
N) is a flag indicating whether the input cell is valid or invalid.

FIG. 7 shows an example of the circuit configuration of the control section. In the figure, an L (k) calculation unit (address offset value calculation unit) 11 is a free top address register (ADR).
The address offset value L (k) is calculated from the empty top address held in the above and the self output highway port number [o (k)] based on the equation.

In the x calculator (effective cell number calculator) 12,
The number of valid cells x is calculated by the shift register (SFR) and the counter (CNT1) using the valid / invalid information (CN # 0 to CN # (N-1) of the cells arriving at each input highway. The free top address calculation unit 13 adds this x value and the address value of the free top ADR, and thereby holds the next free top address in the free top ADR.

The y calculator (cell input port number calculator) 14 calculates the input port number y to which the x-th valid cell is input by the counter (CNT2). Here, CT indicates the beginning of the cell. The match detection unit 15 compares the address offset value L (k) with the number x of valid cells, and when L (k) = x is determined, an output is generated, and SEL is generated.
(K) The calculation unit (selected port number calculation unit) 16 latches the value of the input port number y at that time based on the output of the match detection unit 15 to obtain the selected port number SEL (k), Notify the selector 3 ₄ .

[0040]

As described above, according to the present invention, it is possible to construct a high-speed and large-capacity ATM switch using a low-speed device (especially memory) without increasing the buffer amount. .

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of an ATM switch of the present invention.

FIG. 2 is a diagram showing a configuration of an output buffer type switch which is logically equivalent to the ATM switch of the present invention.

FIG. 3 is a diagram showing an embodiment (1) of the present invention, in which (a)
Is a configuration example, and (b) is an operation example.

FIG. 4 is a diagram showing another principle configuration of the present invention.

5 is a diagram showing an example of selecting each output port in the sorting switch having the configuration shown in FIG.

FIG. 6 is a diagram showing an embodiment (2) of the present invention.

FIG. 7 is a diagram illustrating a circuit configuration example of a control unit.

FIG. 8 is a diagram showing a layout method of buffer memories in an ATM switch, where (a) is a common buffer type switch, (b) is an input buffer type switch, (c) is an output buffer type switch, and (d) is Cross-point switches are shown respectively.

[Explanation of symbols]

2 Filter 3 Sorting switch 3 ₁ Matrix switch 3 ₂ Effective cell detection / control unit 3 ₃ Holding register 3 ₄ Selector 3 ₅ Control unit 4 Buffer unit 5 Multiplexing unit

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Naoki Matsuoka 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Within Fujitsu Limited (72) Inventor, Koji Amano 1-4-4 Hakata-ekimae, Hakata-ku, Fukuoka, Fukuoka FUJITSU Kyushu Communication System Co., Ltd.

Claims (3)

[Claims] 1. A filter comprising an input / output port corresponding to a plurality of input highways, wherein only a valid cell to the corresponding output highway among the input cells from the plurality of input highways is passed, and each output port of the filter. A switching switch that selectively connects between an input port corresponding to the above and a plurality of output ports to transfer cells, and a memory including a plurality of element rows that stores information for one cell. A plurality of memory cells are arranged in parallel corresponding to each output port of the buffer unit, and the memory units sequentially increase in the column direction and are sequentially and repeatedly increased in the row direction. And an output common type cross point buffer unit, which is composed of a multiplexing unit that multiplexes the cells read from the buffer unit and outputs the multiplexed cells. In each output common type crosspoint buffer section, corresponding to the way, the sorting switch outputs valid cells input from the filter from an output port connected to a memory corresponding to the beginning of an empty address of the buffer section. The output ports are sequentially sorted in ascending order of addresses and written in parallel to a plurality of memories of the buffer unit, and the multiplexing unit multiplexes the cells read out in the address order from the plurality of memories into a predetermined format and applies. An ATM switch system characterized by outputting to an output highway. 2. The ATM switch system according to claim 1, wherein when the number of the input highways and the number of the output highways are two, the sorting switch 3 can switch the input / output ports to a cross or straight state. Matrix switch and effective cell detection that determines the effective cells at each of the two input ports
A control unit and a holding register for holding information on whether the head of the empty address of the buffer unit is even or odd, and an input corresponding to the even address of the matrisk switch when the head of the empty address is odd When valid cells arrive at a port, or when valid cells arrive at both input ports of the matrix switch, or when the start of an empty address is an even number, valid cells arrive at an input port corresponding to an odd address of the matrix switch. Is set, the matrix switch is set to a cross state, and in other cases, the matrix switch is set to a straight state. 3. The ATM switch system according to claim 1, wherein when the number of the input highways and the number of output highways are each N, the sorting switch sets an address offset value from the beginning of a vacant address to a memory. An address offset value calculation unit, a valid cell number calculation unit that calculates the number of valid cells that simultaneously arrive from a plurality of input ports, and a cell input port number calculation unit that calculates the input port number at which the valid cells arrive. A control including a coincidence detection unit that detects a coincidence between the address offset value and the valid cell number, and a selection port number calculation unit that latches the input port number at the time of the coincidence detection and outputs a selection port number And a selector that accommodates each input port and selects an input port according to the input port selection number. ATM switch system, characterized in that it consists.