JPH09237813A - Method and device for testing semiconductor substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and a device for test with which accurate dislocation generating stress on the surface of a semiconductor substrate is obtained. SOLUTION: To the surface of a semiconductor substrate 23 which is kept at lower temperature than evaluation temperature, test load is applied with an indenter 25 in between, and at this state, the temperature of the semiconductor substrate 23 is raised up to the evaluation temperature and held whole specified time, and then the temperature is lowered, and then generation state of dislocation is confirmed with a means which detects variation in crystal lattice in the semiconductor substrate 23, and, from the relationship among the evaluation temperature, contact stress caused by application load and dislocation generation state, dislocation generation stress is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate testing method and apparatus, and more particularly to a testing method and apparatus for obtaining dislocation generation stress of a semiconductor substrate.

[0002]

As is well known, a semiconductor substrate such as a silicon wafer is used as a starting material for manufacturing a semiconductor device. As such a semiconductor substrate, a dislocation-free substrate having no disorder in the crystal lattice is usually used. However, some semiconductor substrates have dislocations after the device manufacturing process is performed many times. Dislocations have a great influence on electrical characteristics. For example, when a dislocation exists near the device active layer on the surface of the semiconductor substrate, the dislocation attracts metal impurity atoms such as iron and copper in the substrate to the surroundings. If these dislocations are present between the regions that require electrical isolation, electrical dislocations tend to be mediated by metal impurity atoms, and a leak current is generated to lower the electrical reliability. When the electrical characteristics are lowered, the product yield is inevitably lowered.

From the above, suppression of dislocation generation is one of the most important issues for semiconductor device manufacturing. In order to suppress the generation of dislocations, it is necessary to accurately know the stress at which dislocations occur. Since dislocations tend to occur mainly in semiconductor substrates at temperatures above 600 ° C, it is necessary to conduct a test in advance to obtain the critical stress for dislocation generation at high temperatures.

FIG. 5 shows an apparatus for carrying out a conventional test method for obtaining the critical stress for dislocation generation at high temperature.
In the conventional test method, first, the semiconductor substrate 3 is placed on the sample support base 2 provided in the test heating furnace 1. A load rod 5 having an indenter 4 at its tip is provided above the sample support base 2 so as to penetrate the upper wall of the heating furnace 1. The load rod 5 is supported by a balance 6 having a knife edge, and is driven by an electromagnetic load mechanism 7.

Prior to the test, the vacuum furnace 8 was used to heat the furnace 1.
The inside is evacuated. Then, the temperature inside the heating furnace 1 is raised to raise the semiconductor substrate 3 to the evaluation temperature. After reaching the evaluation temperature, the load rod 5 is displaced by the electromagnetic load mechanism 7 to bring the indenter 4 into contact with the surface of the semiconductor substrate 3, and the indenter 4 is applied with a test load.
Press and hold for 10 seconds, for example.

Then, after the temperature inside the heating furnace 1 is lowered, the semiconductor substrate 3 is taken out from the heating furnace 1, immersed in a selective etching solution containing hydrofluoric acid as a main component, and the surface of the semiconductor substrate 3 is etched by an etch pit method. Observe whether dislocations have occurred. When dislocations occur, they are observed as dislocation pits. Then, the dislocation generation stress at the evaluation temperature is acquired from the relationship between the pushing load of the indenter 4 and the dislocation generation.

However, the above-mentioned conventional test method has the following problems. That is, the conventional test method employs a method in which the indenter 4 is brought into contact with the semiconductor substrate 3 when the semiconductor substrate 3 reaches the evaluation temperature. Therefore, when the load rod 5 serves as a heat transfer path and the indenter 4 contacts the semiconductor substrate 3, a temperature gradient may occur between the semiconductor substrate 3 and the indenter 4. The occurrence of dislocations is greatly affected by temperature. Therefore, the above-mentioned temperature gradient becomes detrimental in obtaining accurate dislocation generation stress.

Further, in the conventional test method, a method of pushing the indenter 4 into the semiconductor substrate 3 up to a predetermined load at high temperature is adopted. The generation of dislocations is greatly influenced by the speed at the time of pushing, that is, the strain speed given to the semiconductor substrate 3.
In the actual semiconductor device manufacturing process, the strain rate acting on the semiconductor substrate is expected to be as small as about 10 ⁻⁹ per second. Therefore, in the test in which the indenter 4 is pushed in like the conventional test method, it is difficult to compare with the actual manufacturing process, and it is difficult to obtain data that can be fed back to the manufacturing process.

[0009]

As described above, the conventional test method has a problem that it is difficult to obtain accurate dislocation generation stress in consideration of the environmental conditions under which the semiconductor substrate is actually handled. Therefore, the present invention can carry out a test that can suppress the temperature gradient that tends to occur between the load application system and avoid the influence of strain rate, and thus can accurately feed back to the semiconductor manufacturing process to contribute to the improvement of yield. An object of the present invention is to provide a semiconductor substrate test method and a device therefor capable of easily obtaining stress.

[0010]

In order to achieve the above object, in the test method according to the present invention, a test load is applied to the surface of the semiconductor substrate kept at a temperature lower than the evaluation temperature through an indenter, In this state, the semiconductor substrate is heated to the evaluation temperature and held for a certain period of time and then cooled, and then the dislocation generation state is confirmed by means for detecting the disorder of the crystal lattice in the semiconductor substrate, and the evaluation temperature and applied load The dislocation generation stress of the semiconductor substrate is acquired from the correlation between the contact stress and the dislocation generation state.

The test load is preferably applied by placing the indenter on the semiconductor substrate or placing the indenter and the load adjusting weight. Further, in order to achieve the above object, in the test apparatus according to the present invention, a sample container having a support base for supporting a semiconductor substrate therein and the semiconductor substrate supported by the support base are brought into contact with the semiconductor substrate. A load applying means for applying a predetermined load to the semiconductor substrate, a heating means for heating the semiconductor substrate, and a predetermined time after heating the semiconductor substrate to an evaluation temperature while applying the load by the load applying means. Heating control means for controlling the heating means so as to lower the temperature after holding, and detection means for detecting the occurrence state of dislocations in the semiconductor substrate after the temperature is lowered,
And a calculation means for obtaining the dislocation generation stress of the semiconductor substrate from the correlation between the evaluation temperature, the contact stress due to the applied load, and the dislocation generation state.

In the test method according to the present invention, a procedure is adopted in which a test load is applied to the surface of the semiconductor substrate kept at a temperature lower than the evaluation temperature through an indenter, and then the semiconductor substrate is heated to the evaluation temperature. Therefore, the influence of the strain rate at the evaluation temperature can be avoided. Further, since the test load is applied to the surface of the semiconductor substrate via the indenter and the temperature of the semiconductor substrate is raised to the evaluation temperature, it is difficult for the semiconductor substrate and the indenter to have a temperature gradient. When a load is applied by using the drive mechanism, if a heat insulating material is interposed in the middle of the load applying system, the occurrence of temperature gradient can be suppressed. Further, by adopting a method of applying a test load by placing the indenter on the semiconductor substrate or placing the indenter and the load adjusting weight on each other, it is possible to eliminate the temperature gradient.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an apparatus for carrying out the test method of the present invention. A sample support base 22 is provided in a test heating furnace (sample container) 21 provided with a heating means such as a heater and a heating control means for controlling a heating temperature.
The semiconductor substrate 23 is horizontally placed on the sample holder 22. In the test, a load application tool 24 as a load application means is placed on the semiconductor substrate 23 placed on the sample support base 22.

The load application tool 24 is placed directly on the semiconductor substrate 23, and the indenter 25 is placed on the semiconductor substrate 23 in a state where the indenter 25 is housed inside and is thin to regulate the rolling of the indenter 25. Holding cylinder 26 and this holding cylinder 26
It is composed of a weight 27 for adjusting the load, which is placed on the indenter 25 in a necessary number.

The indenter 25 is made of metal, ceramics, quartz, or the like that can maintain its strength even at high temperatures, and is formed into a shape having a spherical or spherical surface, and the surface of the contact portion with the semiconductor substrate 23 is polished smoothly. Similarly to the indenter 25, the holding cylinder 26 and the load adjusting weight 27 are also made of metal, ceramics, quartz, or the like that can maintain strength even at high temperatures.

The sum of the weight of the indenter 25 and the weight of the load adjusting weight 27 is applied to the surface of the semiconductor substrate 23 as a test load. Mainly weight adjustment weight 27
The test load to be applied is adjusted by changing the number and size of the. The weight of the indenter 25 and the weight 27 for adjusting the load is measured by an electronic balance in advance, and the stress generated in the semiconductor substrate 23 is calculated from the measured weight and the shape of the contact portion of the indenter 25 with the semiconductor substrate 23.

The inside of the heating furnace 21 can be evacuated by a vacuum pump 28. Next, a procedure of a test for acquiring the dislocation generation stress of the semiconductor substrate 23 using the above-mentioned device will be described.

First, the semiconductor substrate 23 is placed on the sample support base 22 in the heating furnace 21. Then, the semiconductor substrate 23
The indenter 25, the holding cylinder 26, and the weight 27 for adjusting the load are provided on the upper side.
The load applying tool 24 consisting of is placed. At this time,
The number and size of the load adjusting weights 27 are selected so that the sum of the weight of the indenter 25 and the weight of the load adjusting weights 27 becomes the test load.

Next, the inside of the heating furnace 21 is evacuated to a predetermined pressure by the vacuum pump 28. Then, the heating control means is operated to raise the temperature in the heating furnace 21 at a constant rate of increase. After raising the temperature to the evaluation temperature, it is kept at this temperature for a fixed time, for example, 10 seconds.

Next, the temperature in the heating furnace 21 is lowered at a constant rate of decrease. Next, from the inside of the heating furnace 21, the semiconductor substrate 23
Then, the disorder of the crystal lattice of the semiconductor substrate 23 is detected. As a method of detection, for example, the semiconductor substrate 23 taken out is dipped in a selective etching solution containing hydrofluoric acid as a main component, and whether or not dislocations are generated on the surface of the semiconductor substrate 23 is observed by an etch pit method. If dislocations have occurred, only the portion pressed by the indenter 25 is preferentially melted, so that dislocation pits can be observed with an optical microscope or the like. Detection of disorder of the crystal lattice is not limited to selective etching, but X-ray observation or a transmission electron microscope can be used.

Next, the indenter 25 and the weight 27 for adjusting the load.
The load generated when the load is applied, that is, the relationship between the decomposed shear stress and the dislocation generation, the dislocation generation stress at the evaluation temperature is acquired through the calculation means.

FIG. 2 shows the relationship between dislocation generation stress and temperature of the silicon wafer obtained by the above method. The vertical axis represents stress and the horizontal axis represents temperature. The solid line is a curve dividing the dislocation generation region and the dislocation generation region. It can be seen that the dislocation generation stress tends to decrease as the temperature increases.

As described above, according to the method of the present invention, a predetermined load is applied to the semiconductor substrate 23 placed at room temperature through the indenter 25, and the temperature is raised to the evaluation temperature in this state. The temperature gradient between the semiconductor substrate 23 and the indenter 25 can be made smaller than in the conventional example shown in FIG. In addition, since a predetermined load is applied to the semiconductor substrate 23 via the indenter 25 in advance, the pushing speed, that is, the strain speed can be brought close to zero without limit. Therefore, it is possible to easily obtain the accurate dislocation generation stress that can be fed back to the semiconductor manufacturing process and contribute to the improvement of the yield.

The test may be conducted in a load application mode as shown in FIGS. In the example shown in FIG. 3, a plurality of, for example, three load applying tools 24a, 24b, 24c are mounted on a single semiconductor substrate 23. The load applying tools 24a, 24b, and 24c are configured similarly to the example shown in FIG. 1 and are independent of each other. Therefore, the test can be performed under a large number of load conditions at one time, so that the efficiency of the test can be improved. In addition,
The contact stress due to the indenters 25 is abruptly attenuated at about 10 μm from the contact center, so that there is no mutual influence between the indenters 25.

In the example shown in FIG. 4, one semiconductor substrate 23
Three indenters 25 are placed on top, and a load adjusting disc 29 is placed on top of that. The load adjusting disc 29 is shown in FIG.
As shown in (b), conical recesses 30 for fixing the negative part of the indenter 25 are provided at 120 ° equidistant positions on the same circumference. Like the indenter 25, the load adjusting disc 29 is made of metal, ceramics, quartz, or the like that can maintain its strength even at high temperatures. At the three load points on the semiconductor substrate 23, the weight of the indenter 22 and the load adjusting disc 2 are provided.
The weight of 9 plus the weight of 1/3 is applied as the test load. If a heat insulating material is interposed in the middle of the load applying system, a method of applying a test load using a drive mechanism may be adopted.

[0026]

As described above, according to the test method and the apparatus therefor of the present invention, it is possible to obtain accurate dislocation generation stress on the surface of the semiconductor substrate. Therefore, by feeding back this dislocation generation stress data to the semiconductor device manufacturing process and controlling the process so as not to exceed the above stress, dislocation generation in the manufacturing process can be prevented and the product yield can be improved.

[Brief description of drawings]

FIG. 1 is a sectional view showing an example of an apparatus for carrying out the method of the present invention.

FIG. 2 is a diagram showing an example of dislocation generation stress characteristics obtained by the method of the present invention.

FIG. 3 is a cross-sectional view showing another embodiment of the apparatus for carrying out the method of the present invention.

FIG. 4 (a) is a sectional view showing still another embodiment of the apparatus for carrying out the method of the present invention, and FIG. 4 (b) is a plan view of a load adjusting disc used in the apparatus.

FIG. 5 is a cross-sectional view of an apparatus for performing a conventional method.

[Explanation of symbols]

 21 ... Test heating furnace (sample container) 22 ... Sample support 23 ... Semiconductor substrate 24, 24a to 24d ... Load applying tool 25 ... Indenter 26 ... Holding cylinder 27 ... Load adjusting weight 28 ... Vacuum pump 29 ... Disc for load adjustment

Claims (3)

[Claims] 1. A test load is applied to the surface of a semiconductor substrate, which is kept at a temperature lower than the evaluation temperature, through an indenter, and in this state, the semiconductor substrate is heated to the evaluation temperature and held for a certain period of time and then cooled. After that, the dislocation generation state is confirmed by means for detecting the disorder of the crystal lattice in the semiconductor substrate, and the dislocation generation stress of the semiconductor substrate is acquired from the correlation between the evaluation temperature and the contact stress due to the applied load and the dislocation generation state. A method for testing a semiconductor substrate, comprising: 2. The semiconductor substrate according to claim 1, wherein the test load is applied by placing the indenter on the semiconductor substrate or placing the indenter and a weight for weight adjustment. Test method. 3. A sample container having a support base for supporting a semiconductor substrate therein, and a load applying means for contacting the semiconductor substrate supported by the support base and applying a predetermined load to the semiconductor substrate. And heating means for heating the semiconductor substrate, and controlling the heating means to raise the temperature of the semiconductor substrate to an evaluation temperature with a load applied by the load applying means, hold the semiconductor substrate for a predetermined time, and then lower the temperature. Heating control means, detecting means for detecting the occurrence of dislocations in the semiconductor substrate after the temperature decrease, and the dislocation occurrence stress of the semiconductor substrate from the correlation between the evaluation temperature, the contact stress due to the applied load and the dislocation occurrence An apparatus for testing a semiconductor substrate, comprising: an arithmetic means for obtaining