JPH09237219A - High speed memory controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high speed memory controller which efficiently reads/ writes data into/from a high speed memory. SOLUTION: When a read start signal is received, a state shift is sequentially performed from an idle 66 and a read request packet is transmitted to the high speed memory in a read request 63. When a negative response is received from the high speed memory in a read acknowledgment judgment 65 and a write start signal is generated, the state shifts to a write transaction (bus enable write 72) without waiting for the lapse of prescribed time in a misdelay read 68. The state similarly shifts to the other transaction even if the negative response is received while the write transaction is executed and the read start signal is previously generated at that time. Since the other transaction is executed during waiting time, access efficiency improves.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high speed memory control circuit for controlling reading and writing to a high speed memory capable of continuously reading and writing a plurality of words by designating a start address and a count number, and particularly to a high speed memory control circuit. The present invention relates to a high-speed memory control circuit that controls reading and writing to a high-speed memory that needs to be accessed again after a predetermined waiting time has elapsed when there is no data to access the sense amplifier cache memory in the memory.

[0002]

2. Description of the Related Art As one of the techniques for increasing the speed of a data write operation or a data read operation to a memory, there is a method of accessing data in block units. In such a memory, reading / writing of data is performed by designating the start address of the data to be accessed and the number of words to be continuously accessed. A high-speed memory that performs reading and writing in block units includes a memory cell array in which memory cells that store one bit of information are arranged in an array, and a sense amplifier cache memory that has a storage capacity for one column of the memory cell array. Then, the access to the memory cell array is performed for each column via the sense amplifier cache.

For example, when a block-unit read request is received and the corresponding data exists in the sense amplifier cache, the data is immediately sent from the sense amplifier cache. On the other hand, when the requested data does not exist in the sense amplifier cache, the requested data is once read from the memory cell array to the sense amplifier cache and then block-transferred to the request source. Therefore, when the requested data does not exist in the sense amplifier cache, the requesting device is kept waiting until it is read from the memory cell array.

In order to allow the device that has issued the read request to execute other processing during such a waiting time, a response indicating whether or not the read request can be immediately met is sent. There is a high speed memory that is supposed to be returned. In such a high-speed memory, a protocol for accessing the memory is defined, and according to this, a read / write request, a response thereto, and further, data to be read / written is transferred by various packets. As a high-speed memory that defines a transfer protocol and block-transfers data in packets, for example, RAMBUS (RAMBU
There is a Rambus dynamic memory (referred to as RDRAM) using an S) interface.

In the Rambus interface, a read / write request is transferred by a request packet, and read / write data is transferred by a data packet. The response to the request packet is notified by the response packet.
By combining these three types of packets,
One transaction is formed that accesses the fast memory. The transaction includes a memory space read transaction for reading data in the memory cell array and a memory space write transaction for writing data in the memory cell array. Further, there are a register space read transaction for reading a register inside the high-speed memory such as an operation mode register, a register space write transaction for writing to an internal register, and a register space broadcast write transaction.

FIG. 5 shows an example of the bit structure of the request packet. Request packet 20
1 has a structure of 10 bits × 6 rows. 1 in each row
Data of 0 bits is transferred in parallel between the high speed memory and the bus master. The cycle of transferring each row is called an interval, and one request packet is transferred at six intervals. In the figure, the first bit 20 of each line
2 is transferred by a signal line called bus control. The remaining 9 bits 203 are transferred by a signal line called bus data.

The start bit 203 is information indicating the beginning of the request packet. The 4 bits from option "0" to option "3" are operation codes for designating the type of requested data transfer. The address specifies the address of the first byte to be transferred, and 36 bits are prepared. The count represents the number of bytes of data transferred in one transaction. The count is prepared for 8 bits, and up to 256 bytes can be specified. Reserves are unused bits. Upon receiving such a request packet, the high speed memory returns a response packet indicating whether or not the request can be immediately met to the bus master.

FIG. 6 shows an example of the bit structure of the response packet. The response packet 211 is each head bit portion transferred through the bus control signal line in the 10-bit width signal, and is composed of two bits transferred in two intervals. It is also possible to transfer the data packet at the same time as the response packet by using the remaining 9 bits 212 of the 10-bit width signal transferred through the bus data signal line.

FIG. 7 shows the values of the two bits of the response packet and the notification contents of the response packet indicated by them. When the value of two bits of the response packet is "00", it indicates that there is no slave (high speed memory) corresponding to the destination of the request packet. When it is "01", it is a permission response indicating that the request of the request packet can be immediately met. “1
When it is "0", it is a negative response indicating that the request cannot be responded. When the negative response is received, the bus master again sends the request packet after a certain period of time and retries. 11 ″ is undefined.

FIG. 8 shows an example of the structure of a data packet. The data packet 221 is transferred with a 9-bit width through the bus data signal line. One data packet contains one to two 9-bit wide data bytes.
Any number between 56 can be included. A response packet can be sent by bus control signal line 222 in parallel with the transfer of the data packet.

FIG. 9 shows a transfer procedure of each packet in a read transaction. This figure is
Data 231 transferred by the bus control signal line and data 232 transferred by the bus data signal line are shown according to the transfer procedure. In the figure, data is not transferred at the shaded areas. First, the read request packet 233 is output from the bus master to the high speed memory by using both the bus control signal line and the bus data signal line. After the ACK (acknowledge) delay 234 has elapsed since the read request was output, the response packet 235 is returned from the high speed memory to the bus master.

When the response packet 235 indicates request permission, the high speed memory transfers the requested read data 237 to the bus master after the read delay packet 233 is transmitted after the read request packet 233 is transmitted. AC
The lengths of the K delay 234 and the read delay 236 are set in the internal registers of all devices in advance during system initialization. A read pipe delay 241 in which data is not transferred is provided between one transaction 238 and the next transaction 239.

The read pipe delay 241 ensures that the Rambus device, such as a high speed memory, has time to complete the process corresponding to the previous transaction before starting to process the next transaction. After the read pipe delay 241 has elapsed, the bus master can send a read request packet 242 for the next transaction.

FIG. 10 shows the transfer procedure of each packet in the write transaction. Similar to FIG. 9, the data 251 transferred by the bus control signal line and the data transferred by the bus data signal line are shown according to the transfer procedure in the write transaction. Further, the shaded area is a portion where data is not transferred. The bus master sends the write request packet 253 to the high speed memory using both the bus control signal line and the bus data signal line. Then, after the ACK delay 254 has passed, the response packet 255 is returned from the high speed memory.

In the case of a write transaction, if the write delay 256 elapses after the write request packet 253 is sent, the bus master sends the write data 257 even before the response packet is returned. You can start. When the response packet from the high-speed memory indicates the permission response, the transfer of the write data 257 is continued.
If the response from the high-speed memory is a negative response, the write data 257 that was sent before the response packet was received.
Is discarded on the high-speed memory side. The lengths of the ACK delay 254 and the write delay 256 are set in the internal registers of all devices in advance during system initialization, as in the case of the read transaction.

A write pipe delay 2461 in which data is not transferred is provided between one transaction 258 and the next transaction 259. The write pipe delay 261 as well as the read pipe delay 261 ensures that the Rambus device has time to complete the process corresponding to the previous transaction before starting to process the next transaction. The bus master can send the next write request packet 262 after the read pipe delay 261 has elapsed.

Next, the structure of a high speed memory for reading and writing data according to such a protocol will be described.

FIG. 11 shows an outline of the structure of the high speed memory. The high-speed memory 271 includes an application layer 272 that stores data, a logical layer 273 that controls reading and writing in the high-speed memory, and a physical layer 274 that sends and receives signals to and from the bus master. The application layer 272 is provided with a 0th DRAM (dynamic memory) array 275 and a first DRAM array 276. The DRAM arrays 275 and 276 are memory cell arrays each having a storage capacity of 9 megabits.

The 0th DRAM array 275 is connected to a 0th sense amplifier cache 277 capable of storing 9-bit wide data for 2 kilowords.
Further, a first sense amplifier cache 278 having a similar storage capacity is connected to the first DRAM array 276. These sense amplifier caches 277, 2
78 can store data for one column of DRAM arrays 275, 276.

The logic layer 273 includes a mode register 281 for setting the operation mode of the high speed memory 271, a control register group 282 for storing control information, and a control circuit for controlling the operation of the high speed memory 271 according to the operation mode. 283 is provided. The physical layer 273 is the Rambus 28.
4 includes a receiver 285 that receives a bus enable signal, a bus control signal, and a bus data signal sent from the bus master through No. 4, and a transmitter 286 that sends the bus control signal and the bus data signal to the bus master through the Rambus 285. Transmitter 2
From the 86, 10-bit width data including the bus control signal and the bus data signal is output. Further, the receiver 285 receives 11-bit width data obtained by adding a bus enable signal thereto.

A clock signal 287 used for receiving data from the bus master is input to the physical layer 274 from the bus master side. Further, a clock generation circuit 28 that generates a clock signal 288 when transmitting data to the bus master
9 is provided. The clock signals 287 and 288 are transferred with a 1-bit width, respectively.

Next, a high speed memory control circuit for controlling the reading / writing of data from / to the high speed memory will be described.

FIG. 12 shows an outline of the structure of a conventional high speed memory control circuit. The high speed memory control circuit 291 is arranged between the high speed memory 292 and a CPU (central processing unit) 293 that reads and writes data. The high-speed memory control circuit 291 is the CPU 2
The interface circuit receives a read / write instruction from 93 and transmits / receives a packet to / from the high-speed memory 292 according to the protocol described above.

From CPU 293 to high speed memory control circuit 29
Reference numeral 1 denotes an address signal 294 representing an address of data to be accessed and a CPU control signal 29 representing various control information such as effective timing of each signal and an operation mode.
5 is input. A data signal 296 representing data to be read from and written to the high speed memory 292 is transmitted and received between the high speed memory control circuit 291 and the CPU 293.

The ready signal 297 indicating the end of the read / write operation to the high speed memory and the synchronous clock 298 are input to the CPU 293 from the high speed memory control circuit 291.
A Rambus 299 as a bus for transmitting a bus control signal and a bus data signal is provided between the high speed memory 292 and the high speed memory control circuit 291, and various packets are transferred through the Rambus 299.

The high speed memory control circuit 291 includes a request packet generator 301 for generating a request packet.
And an internal register 302 for storing various operating conditions that are initially set such as the length of miss delay and a ready signal 2
A CPU controller 303 that outputs 96 is provided. An address signal 294 and a CPU control signal 295 are input from the CPU 293 to the request packet generator 301. Request packet generator 3 based on these signals
01 generates a request packet 305 to be transferred to the high speed memory 292.

The transmission selector 304 has a request packet 305 output from the request packet generator 301.
, The data signal 296, and the level signal 3 as no signal
06 is input. The transmission selector 305 transmits the transmission data (TData) and the transmission control signal (TCtrl) for transmitting any one of these input signals to the high-speed memory.
This is a circuit selected as 307. The interface circuit 308 is a physical interface circuit that converts the signal level between the TTL level in the high speed memory control circuit 291 and the Rambus signal level used in the Rambus 299.

The state control circuit 311 is a circuit for managing the state transition of the operation of the high speed memory control circuit 291.
The ACK deciding unit 312 analyzes the content of the response packet from the high speed memory 292 and outputs an ACK signal 313 representing a permission response or a negative response. Reception gate 314
Is the data read from the high speed memory 292 to the CPU 2
This is a circuit for buffering when transferring to 93.

FIG. 13 shows state transitions managed by the state controller shown in FIG. After the system is initialized, it is in the idle 331 state when no transaction is performed. CP in this state
When a read or write transaction request is received from U293, the start signal 315 is input from the CPU controller 303 to the state controller 311. When the start signal 315 is received, the state of the bus enable signal 332 is changed to the low level. As a result, various packets can be transferred through the Rambus 299.

Next, a request 3 for sending out the request packet generated by the request packet generator 301.
The state transits to 33. After that, high speed memory 292
ACK waiting 334 for the arrival of a response packet from
Transition to the state of. In the Acknowledge 334, packets are not transmitted / received through the Rambus 299. ACK
After the delay time elapses, the state transitions to the ACK determination 335, and the content of the response packet sent from the high speed memory 292 is analyzed. In the case of a write transaction, the write data is transferred to the high speed memory 292 in the ACK determination 335.

When the content of the response packet is a permission response for permitting the request, the ACK determination unit 312 outputs an ACK signal 313 indicating that, and this is input to the state controller 311. When the permission response is received from the high speed memory 292, the state of the finish data 336 is entered. In the finish data 336, write data or read data is transferred by a data packet. In the state of the finish data 336, the number of transferred data is checked, and when the remaining number of transferred data becomes “0”, the state transits to the state of the AC CPU 337.

In the AC CPU 337, the state controller 311 activates the Done signal 316. Upon receiving this, the CPU controller 303 sends a ready signal 297 to the CPU 293. This completes the operation of one transaction, and the state controller 3
11 returns the state to the idle 331 again.

On the other hand, when a negative response is received in the ACK determination 335 state, the state shifts to the miss delay 338 state. In the miss delay 338, the value of the miss delay count set at the initialization is subtracted according to the clock 297 according to the waiting time at the time of the negative response, and when the value becomes “0”, the state of the bus enable 332 is entered. Then, the request packets are transmitted again in order from the bus enable 332. When a negative response is thus received, the miss delay 338 waits for a certain period of time, and then the request packet having the same content as the denied one is transmitted again.

When the negative response is returned from the high speed memory 292, the data addressed by the request packet does not exist in the sense amplifier cache of the high speed memory 292. At this time, the high speed memory 292 sends a response packet and then reads the data requested by the request packet from the DRAM array to the sense amplifier cache. The state of Miss Delay 338 is
This is for waiting for the data necessary for the sense amplifier cache to be read.

FIG. 14 shows an example of various signals transmitted and received between the CPU and the high speed memory control circuit when a transaction is performed. In this figure, a write transaction is performed once after a read transaction is performed once. The CPU 293 outputs the read address 341 as an address signal (c in the same figure) indicating the address on the high-speed memory of the data to be accessed at time T ₁₁ . At the same time, the address strobe signal (a in the same figure) indicating that the address signal is valid and the read / write signal (b in the same figure) indicating the distinction between the read operation and the write operation are set to the high level to be the read transaction. Indicates.

When the address strobe signal is input,
The CPU controller 303 of the high-speed memory control circuit sets the start signal (f in the figure) 315 to a low-level active state. When the start signal 315 is input, the state controller 311 sequentially transits the states from the idle 331 and performs a read sequence. When received from the high-speed memory read data packet to the time T ₁₂ is completed, the state controller 311 proceeds to ACK CPU337 to a completion signal (FIG g) 316 to a low level in the active state.

In response to the completion signal 316 being activated, the CPU controller 303 sends a low level ready signal (e in the figure) to the CPU 293 from the time T ₁₃ to the time T.
Output over ₁₄ . Also, the read data 342 received from the high speed memory 292 is converted into a data signal (d in the figure) 297
Is sent to the CPU 293. At time T ₁₄ , the completion signal and the ready signal return from low level to high level. As a result, the CPU 293 recognizes the end of the read transaction.

At time T ₁₅ after the end of the read transaction, the CPU 293 outputs the write address 343 as an address signal. At the same time, the address strobe signal is output and the read / write signal is set to the low level to indicate that the writing operation is performed. At the same time that the address strobe signal is output, the CPU 293 starts sending the write data 344. When the address strobe signal is input, the CPU controller 303 of the high-speed memory control circuit 291 activates the start signal (f in the figure) 315 indicating the start of the transaction.

In response to this, the state controller 311 sequentially transits the states from the idle 331 and performs the write sequence. When the transmission of the write data packet ends at time T ₁₆ , the state controller 311 sets the completion signal (g in the figure) 316 to the active state. CPU controller 3
In response to the activation of the completion signal 316, 03 outputs a low-level ready signal (e in the figure) to the CPU 293 at time T ₁₇ . After that, the completion signal and the ready signal return from the low level to the high level, and the write transaction ends.

FIG. 15 shows an example of waveforms of various signals transmitted and received between the high-speed memory control circuit and the high-speed memory when a transaction is performed according to the sequence shown in FIG. Further, the high speed memory control circuit 291 when the transaction shown in FIG. 14 is performed.
The state of state transition in the state controller 311 is shown together with signal waveforms transmitted and received between the high speed memory 291 and the high speed memory 291. Times T ₁₁ , T ₁₂ , T ₁₄ , T ₁₅ shown in the figure.
And T ₁₆ respectively correspond to the times indicated by these symbols shown in FIG. Further, in order to facilitate the correspondence with the waveforms shown in FIG. 14, the start signal of FIG. 14f is shown in FIG. 15a and the completion signal of FIG. 14g is shown in FIG.
b respectively.

Here, the data count value indicating the number of data to be accessed by one transaction is set to "1" and the miss delay count is set to "4". Also, a case is shown in which the first transaction is a negative response and the request is permitted in the second transaction. When the start signal (FIG. 15a) from the CPU controller 303 becomes active at time T ₁₁ in the read transaction, the state of the state controller 311 (e in the figure) changes from the idle 351 to the bus enable 3 state.
52, request 353, waiting for ACK 354, and ACK determination 355. In the figure, idle is "I", bus enable is "B", request is "R", ACK wait is "W", ACK judgment is "E", miss delay is "D", finish data is "F", The AC CPU is shown as "C".

The data transfer rate on the Rambus is performed in synchronization with the bus clock (c in the same figure). Further, the state transition is performed in synchronization with the synchronous clock (d in the figure). In the state of the bus enable 352, the bus enable signal (f in the figure) changes to low level and becomes active. In the request 353 state, the high-speed memory control circuit 291 sends the high-speed memory 292 through the bus control signal (g in the figure) and the bus data signal (h in the figure).
The first request packet 356 is sent to the. In the state of ACK wait 353, nothing is done and the bus control signal and the bus data signal do not change.

In the state of ACK determination 355, the response packet 357 is transferred from the high speed memory 292 to the high speed memory control circuit through the bus control signal, and the content thereof is analyzed. In this example, the first-time response packet 357 represents a negative response, and therefore the process proceeds to the miss delay 358. Since the miss delay count value is "4", the miss delay state is repeated for 5 states until the value becomes "0". After that, the state returns to the bus enable 359 state again, and the response packet 362 corresponding to which the second request packet 361 is transmitted is the permission response, so the state of the finish data 364 is changed to the state of the finish data 364 after the state of the ACK determination 363. Transition.

In the state of the finish data 364, four times until the read data packet 365 is received,
Repeat the same state. Then AC CPU 366
In this state, the completion signal (b in the figure) is output.
In response to this, the CPU controller 303 sends a ready signal to the CPU 293 at time T ₁₃ as shown in FIG. After finishing the state of the ac CPU 366, the process returns to the idle 367.

Upon receiving the ready signal, the CPU 293 starts the write transaction at time T ₁₅ , and the CPU controller 303 activates the start signal. As in the read transaction, the states are Idle (I), Bus Enable (B), Request (R),
The process sequentially shifts to ACK waiting (W) and ACK determination (E). In the request 368 state, the request packet 369 is output. In the state of the ACK determination 371, the write data is transferred to the high speed memory 292 by the write data packet 372. At the same time, the response packet 373 is returned from the high speed memory 292 through the bus control signal.

Here, since the response packet 373 represents the permission response, the state shifts to the state of the finish data 374. Since the write data is 1 byte and has already been transferred in the state of the ACK determination 372, the data count is already "0" in the finish data state. As a result, the state immediately transits to the AC CPU 375 and the idle 376.
In the state of the AC CPU 375, the completion signal is activated. In response to this, the CPU controller 303 sends a ready signal to the CPU 291 to complete the write transaction.

[0047]

When there is no data to be read / written in the sense amplifier cache of the high speed memory and a negative response is received, the request is made again after waiting for a certain time in the miss delay state. Sending a packet. Therefore, there is a problem that the high-speed memory is not accessed during the miss delay state, and the data transfer efficiency is reduced accordingly.

Therefore, an object of the present invention is to provide a high speed memory control device capable of efficiently reading and writing data to and from a high speed memory.

[0049]

According to another aspect of the invention, when an access request representing one of a data read request and a data write request is received, the request is waited until a predetermined waiting time elapses. If it cannot respond to the request, it returns a negative response, and if it responds immediately, it returns a permission response.Request sending means for sending an access request to the high speed memory, and a negative response from the high speed memory to the sent access request. When a response is received, it is determined whether or not there is another access request to be sent to the high speed memory, and when this determination means determines that another access request exists, the access request is sent to the high speed memory. The other request sending means for sending and the access request for which a negative response is received when it is judged by the judging means that there is no other access request, after a predetermined waiting time. The high-speed memory includes a resending means for later resending to the high-speed memory and a data reading / writing means for reading / writing data according to the access request from the high-speed memory when a permission response is received from the high-speed memory. It is equipped in the control device.

That is, according to the first aspect of the invention, when a negative response is received from the high-speed memory in response to the sent access request, if there is another access request to be sent to the high-speed memory, the waiting state is not entered. The other access request is sent to the high speed memory. As a result, the read / write operation corresponding to another access request can be advanced during the waiting time until the access request receiving the negative response is retransmitted, and the access efficiency can be improved.

According to the second aspect of the present invention, when an access request representing one of a data read request and a data write request is received, the request cannot be met until a predetermined waiting time elapses. Returns a negative response, and returns a permission response if it can be responded immediately. A request sending unit that sends an access request to the high-speed memory, and a high-speed operation when a negative response is received from the high-speed memory in response to the access request sent. A discriminating means for discriminating whether or not there is another access request to be sent to the memory, and a first other means for transmitting the access request to the high speed memory when the discriminating means judges that there is another access request. Request sending means,
When the discriminating means discriminates that there is no other access request and when a negative response is received and another access request to be sent to the high-speed memory occurs before the elapse of a fixed time shorter than a predetermined waiting time, this is speeded up. When the other access request is not sent by the second other request sending means for sending to the memory and the judging means determines that the other access request does not exist and before the lapse of a certain time after receiving the negative reply, the negative answer is given. Retransmitting means for retransmitting the received access request to the high-speed memory after a lapse of a predetermined waiting time after receiving a negative response, and data according to the access request when the permission response is received from the high-speed memory for the transmitted access request. The high-speed memory controller is provided with a data read / write means for reading and writing data from and to the high-speed memory.

That is, according to the second aspect of the present invention, when a negative response is received from the high speed memory in response to the sent access request, if there is another access request to be sent to the high speed memory, the waiting state is not entered. This access request is sent to the high speed memory. Further, even if there is no other access request at the time of receiving the negative response, when a new access request is generated within a certain time during the waiting state, it is sent to the high speed memory. As a result, the processing can be started immediately even for a new access request generated during the waiting time, so that the access efficiency to the high speed memory can be further improved.

According to the third aspect of the invention, the request sending means is provided with a buffer memory for temporarily holding the data to be written in the high speed memory.

That is, according to the third aspect of the present invention, the data to be written in the high speed memory is temporarily stored in the buffer memory. As a result, the write data corresponding to the write transaction that occurred during the execution of the read transaction can be held.

In the invention according to claim 4, the other access request is an access request of a kind different from the previously sent access request among the data read request and the data write request.

That is, in the invention described in claim 4, when a negative response is received in response to the write access request,
It is checked whether or not there is a read access request. On the other hand, when a negative response is received in response to the read access request, the presence or absence of the write access request is checked.

[0057]

BEST MODE FOR CARRYING OUT THE INVENTION

[0058]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an outline of the structure of a high speed memory control circuit according to an embodiment of the present invention. The high-speed memory control circuit 11 is arranged between the high-speed memory 12 and the CPU 13 that reads and writes data. The high-speed memory control circuit 11 receives a read / write instruction sent from the CPU 13 and sends / receives various packets to / from the high-speed memory 12. The structure of each packet is the same as that shown in the section of the prior art, and the description thereof will be omitted.

The high-speed memory control circuit 11 is capable of accepting read transaction and write transaction instructions in parallel from the CPU 13 as a bus master. When a negative response is returned from the high-speed memory 12 for one of the read or write transactions, and when a request for the other transaction arrives from the bus master 13, the other does not enter the wait state. It is supposed to execute the transaction.

The CPU 13 outputs the instruction of the other transaction to the high speed memory control circuit 11 even after the completion notification is output from the high speed memory control circuit 11 after the instruction of the write transaction or the read transaction is output. It can be sent out. Although such a function may be provided in a single CPU, for example, the high-speed memory control circuit 11 is a multi-CPU.
2 or more CPUs like systems and multi-bus systems
It may be the case where a transaction instruction is received from the (bus master).

The configuration of the high speed memory 12 shown in FIG. 1 includes DRAM arrays of the 0th bank and the 1st bank similarly to the structure shown in FIG. 11, and a sense amplifier cache is provided for each of them. There is. These can operate independently. Therefore, for example, one sense amplifier cache memory and the high-speed memory control circuit 1
While the data packet is being sent to and received from 1, the read / write operation can be performed in parallel with the other sense amplifier cache and the corresponding DRAM array.

Since only one bus is provided between the high-speed memory circuit 11 and the high-speed memory 12, it is not possible to transfer packets of write transaction and read transaction at the same time. However, high speed memory 1
While the data necessary for the sense amplifier cache is being read inside the DRAM array 2 inside, the high speed memory control circuit 11 can access the data stored in the other sense amplifier cache. Therefore, the high speed memory control circuit 11 reads or writes data to the other sense amplifier cache during the waiting time for reading the corresponding data from the DRAM array to the sense amplifier cache after the high speed memory 12 returns a negative response. You can perform embedded transactions.

The CPU 13 inputs to the high-speed memory control circuit 11 an address signal 14 representing the address of the data to be accessed and a CPU control signal 15 representing the effective timing of the signal and the operation mode. Further, the data to be read from and written to the high speed memory 12 is the data signal 16
Is transmitted and received between the high-speed memory control circuit 11 and the CPU 13 through. High-speed memory control circuit 11 to CPU 13
A read ready signal 17 indicating the end of the operation of reading data from the high-speed memory 12, a write ready signal 18 indicating the end of the write operation, and a synchronous clock 19 are input to the.

High-speed memory 12 and high-speed memory control circuit 11
A RAM bus 21, which is a bus for transmitting a bus control signal and a bus data signal, is provided between and, and various packets are transferred through the RAM bus 21.

The high speed memory control circuit 11 includes a write request packet generator 3 for generating a write request packet.
1, a read request packet generator 32 for generating a read request packet, and a transmission latch 33 for temporarily buffering write data sent from the CPU 13 during a write transaction. Even when a write transaction instruction is received from the CPU 13 during execution of a read transaction, the write data from the CPU 13 is stored in the transmission latch. As a result, the high speed memory control circuit 11 can accept instructions for a write transaction and a read transaction from the CPU 13 in parallel.

The high-speed memory control circuit 11 further includes an internal register 34 for storing various operating conditions such as the length of the miss delay delay that is initially set, a high-speed memory according to the output of a control signal to the CPU 13 and an instruction from the CPU 13. The CPU controller 35 for activating the access operation to the. The write request generator 31 and the read request packet generator 32 send the address signal 1 from the CPU 13.
4 and the CPU control signal 15 are input. By inputting these signals, the write request packet generator 31 generates the write request packet 36 and the read request packet generator 32 generates the read request packet 37.

A write request packet 36, a read request packet 37, write data 39 read from the transmission latch 33, and a level signal 41 as no signal are input to the transmission selector 38. The transmission selector 38 is a circuit that selects any one of these input signals as transmission data (TData) and transmission control signal (TCtrl) 42 to be sent to the high-speed memory 12.

The interface circuit 43 is a physical interface circuit for mutually converting the signal level of the TTL level signal in the high speed memory control circuit 11 and the Rambus signal level used in the Rambus 21. The state control circuit 44 is a circuit that manages the states in the high speed memory control circuit 11. The ACK determination unit 45 analyzes the content of the response packet from the high speed memory 12 and outputs an ACK signal 46 representing a permission response or a negative response. The reception gate 47 is a circuit that buffers the data read from the high-speed memory 12 when transferring the data to the CPU 13.

When the CPU controller 35 receives a write transaction command from the CPU 13, it receives a write start signal 51 for instructing the start of a write sequence, and when it receives a read transaction command, it starts a read sequence. A read start signal 52 for instructing is output. These signals 51 and 52 are input to the state controller 44. When the write operation to the high speed memory 12 is completed, the state controller 44 indicates that the write completion signal 53.
When a read operation from the high-speed memory is completed, a read completion signal 54 indicating that is output. These completion signals 53 and 54 are input to the CPU controller 35.

When the write completion signal 53 is input, the CPU controller 35 sends out the write ready signal 18 and the CPU
13 is notified of the end of the write transaction. Also,
When the read completion signal 54 is input, the CPU controller 35 sends the read ready signal 17 to notify the CPU 13 of the end of the read transaction. CPU controller 35
Is a load signal 5 indicating that the write data is held when the write data is sent from the CPU 13 through the data signal 16 in response to the instruction of the write transaction.
5 is output. The transmission latch 33 internally stores the write data from the CPU 13 when the load signal 55 is input.

FIG. 2 shows transitions of states managed by the state controller shown in FIG. There are a transition path for performing a read transaction and a transition path for performing a write transaction starting from the state of the idle 61. If the response packet from the high-speed memory is a negative response and there is a request to execute the other transaction, it moves to the transition path of the other transaction instead of performing the waiting operation in the miss delay state. ing.

The transition path of the read transaction returns from the idle 61 to the idle 61 via the bus enable read 62, the read request 63, the read ACK wait 64, the read ACK determination 65, the finish data read 66, and the ACK CPU read 67. It is a thing. The transition path of the write transaction is from the idle 61,
It returns to the idle 61 again via the bus enable write 72, read request 73, read ACK wait 74, read ACK determination 75, finish data write 76, and ACK CPU write 77.

When the response packet from the high-speed memory 12 indicates a negative response in the states of the read-ac determination 65 and the write-ac determination 75, the read finish data 66 or the write finish data 76.
Does not shift to the state. When the response is negative and there is a request to start the other transaction, the state transits to the bus enable state of the transition path of the other transaction.

That is, in the state of the read-ac determination 65, a negative response is received and the write start signal 51 is CP.
When the U controller 35 is input, the bus enable light 72 transits to the state. Similarly, in the state of the write-ac determination 75, when the negative response is received and the read start signal 52 arrives, the state of the bus enable read 62 is entered.

Even if a negative response is received, if there is no start request for the other transaction, the state shifts to the state of miss delay read 68 or miss delay write 78 and waits until the miss delay count value becomes "0". Enter the state. After that, the state returns to the bus enable state on the original transition path, and the same transaction is tried again.

After the system is initialized, the state controller 4
The state of 4 becomes idle 61. When a write transaction or read transaction instruction is received from the CPU 13, the CPU controller 35 outputs a write start signal 51 or a read start signal 52. In response to this, the state controller 44 sequentially executes transactions according to the state transitions shown in FIG.

For example, when the read start signal 52 becomes active, the state shifts from the idle 61 to the state of the bus enable lead 62. Bus enable 6
In the 2 state, the state controller 44 activates the transmission permission signal (TEenable). As a result, the interface circuit 43 sets the bus enable signal on the Rambus 21 to the low level. Rambus 2
1, the packet can be transferred.

After making the bus enable signal active at a low level, the state controller 44 transits the state to the request lead 63. In the state of the request read 63, the read request packet generator 3
The read request packet generated by 2 is sent to the high speed memory 12 through the Rambus 21. In the read ACK wait state 64, nothing is done and the ACK delay time elapses. After the ACK delay time has elapsed, the state shifts to the read ACK determination 65. Readac judgment 6
In state 5, the response packet returned from the high speed memory 12 is received and the content thereof is analyzed.

When the response packet indicates a permission response, the state of the finish data read 66 is entered. In the finish data read state, the data packet sent from the high speed memory 12 is received while checking the number of transfer data. When the number of remaining data transfers becomes "0", the state of the AC CPU read 67 is entered. In the state of the AC CPU lead 67, the state controller 44 outputs the read completion signal 54. Receiving this, the CPU controller 35 outputs the read ready signal 17 to the CPU 13.

When the state controller 44 receives a negative response packet in the state of the read-ac determination 65, the state controller 44 determines whether or not the write start signal 51 is input from the CPU controller 35. Write start signal 51
If is not input, miss delay lead 68
Transition to the state of. In the state of the miss delay read 68, the value of the miss delay count preset at the time of initialization is sequentially subtracted based on the synchronous clock 19, and the state of the miss delay read remains until the value becomes “0”. When the miss delay count value becomes “0”, it shifts to the state of the bus enable read 62,
Perform a read transaction again.

When a negative response is received in the read-ac determination 65 state and the write start signal 51 is input, the read-ac determination 65 shifts to the bus enable write 72 state and a write transaction is performed. Since the write transaction is executed by using the waiting time in the miss delay state as described above, the access efficiency of the high speed memory can be improved.

Similarly, when the write start signal 51 becomes active in the idle 61 state, the state shifts to the bus enable write 72 state and the transmission enable signal (TEenable) becomes active. After that, the state shifts to the state of the request write 73, and the write request packet generated by the write request packet generator 31 is sent to the high speed memory 12. After waiting the ACK delay time in the state of waiting for write ACK 74, the process moves to the write ACK determination 75 and analyzes the contents of the response packet returned from the high speed memory.

When the response packet indicates permission of the request, the state of the finish data write 76 is entered. In the case of a write transaction, the write data packet can be transferred to the high speed memory through the bus data signal line in the state of the write ACK determination 75. If write data to be transferred still exists in the high speed memory 12 when the request permission response packet is received, the remaining data is transferred in the state of the finish data write 76. When the number of remaining data transfers becomes "0", the state shifts to the state of the ACK CPU write 77, and the write completion signal 53 is output. CP that received this
The U controller 35 sends a write ready signal 1 to the CPU 13.
8 is output.

When a negative response is received in the state of write-ac determination 75 and the read start signal 52 is inactive, the state of the miss delay write 78 is entered. Then, after waiting until the value of the miss delay count becomes "0", the state transits to the state of the bus enable write 72 and the write transaction is performed again. When a negative response is received in the state of the write-ac determination 75 and the read start signal 52 is input, the write-ac determination 7
Transition from 5 to the state of bus enable lead 62,
Perform a read transaction.

FIG. 3 shows an example of waveforms of various signals transmitted and received between the CPU and the high speed memory control circuit. This figure shows a case where after receiving a read transaction instruction from the CPU 13, a write transaction instruction is subsequently received. The CPU 13 sets the time T _21.
The read address 81 is output to the address signal (c in the figure), the read / write signal (b in the figure) is set to the high level, and the address strobe signal (a in the figure) is activated. As a result, a read transaction instruction is sent to the high-speed memory control circuit 11.

High-speed memory circuit 1 receiving these signals
The CPU controller 35 of No. 1 reads the start signal (g in the figure).
Is set to a low level active state at time T ₂₁ . Further, the read request packet generator 32 has the CPU 13
Read request packet 37 with contents according to the instruction from
Generate According to the state transition shown in FIG. 2, the state controller 44 performs a process of reading the data at the address designated by the CPU 13 from the high speed memory 12 by the designated number of bytes.

While such an operation is being performed, the CP
U13 sends an indication of the write transaction to the high-speed memory control circuit 11 at time T _22. That is, time T ₂₂
In addition, the CPU 13 sets the read / write signal (b in the figure) to the low level and outputs the write address 82 and the write data 83 as a data signal (d in the figure). At the same time, the address strobe signal is activated.
The CPU controller 35 outputs a write start signal (i in the figure) to the state controller 44 at time T ₂₂ when the instruction of the write transaction is received from the CPU 13. The writing request packet generator 31 generates a write request packet 36 at time T _22. Further, the CPU 13
The write data 83 sent from is temporarily stored in the transmission latch 33.

Here, it is assumed that a negative response packet is returned from the high speed memory 12 in response to the request packet sent by the high speed memory control circuit 11 in the process of executing the read transaction instructed by the CPU 13. . Since the state controller 44 has received a negative response and the write start signal 51 has been input from the CPU controller 35 in the read-ac determination state 65 (FIG. 2), the state controller 44 shifts to the state of the bus enable write 72. .

As a result, the write transaction request packet is transmitted. In addition, the write data stored in the transmission latch 33 is read and the high speed memory 1
2 is transmitted as a write data packet. It is assumed that the response packet from the high speed memory 12 for the write request packet indicates the permission of the request. In this case, according to the state transition shown in FIG. 2, the state transitions from the write-ac determination 75 to the finish data write 76 and the ac CPU write 77.

At the time T _{23 when} the state of the ACK CPU write 77 is executed, the state controller 44 outputs the write completion signal (FIG. 3j) 53, and at the time T ₂₄ , the CPU controller 35 writes the signal. A ready signal (f in the figure) 18 is output to the CPU 13. In this way, when a negative response is returned from the high-speed memory to the read transaction instructed earlier, the write transaction instructed later is performed while waiting for the miss delay.

The state controller 44 stores that the read start signal has been output from the CPU controller 35 in response to the instruction of the read transaction previously received. As a result, after the write transaction is completed and the state returns to the idle state 61, the state controller 44 executes the read transaction in the order of the bus enable read 62 and the read request 63. If the response packet to the second read request packet indicates permission of the request, the state of the read ack determination 65 is shifted to the finish data read 66, and the high speed memory 12
The read data packet is received from. Time T at which data reception ends until the data count reaches "0"
_{At 25} , the state transitions to the state of the AC CPU lead 67, and the read completion signal (FIG. 3h) is output from the state controller 44.

In response to this, the CPU controller 35 makes the time T
The read ready signal (FIG e) to a low level in the active state _26, data 84 read from the fast memory 12
Is transferred to the CPU 13 via the reception gate 47. In this way, a negative response is received by the first access, and
When another transaction is requested, it is processed first and then the second transaction is executed.

FIG. 4 shows an example of waveforms of various signals transmitted and received between the high speed memory control circuit and the high speed memory. This figure shows the high-speed memory control circuit 11 and the high-speed memory 1 when the transaction shown in FIG. 3 is performed.
2 shows a state of a signal transmitted to and received from the device 2 and a state transition in the state controller 33. Time T ₂₁ shown in FIG, T _22, T ₂₃ and T ₂₅ correspond to the time indicated by these codes shown in FIG. 3, respectively. Also, the signals shown in FIGS. 3g-j are shown in FIGS. 4a-d, respectively, for ease of association with the waveforms shown in FIG.

Here, the number of data accessed by one transaction, that is, the data count value is "1". The first read transaction is a negative response, and the request is permitted in the second read transaction. Also, write transaction is 1
It shows the case of obtaining the request permission at the second time. When the read start signal (a in the figure) from the CPU controller 35 becomes active at the time T ₂₁ in the read transaction, the state of the state controller 44 (j in the figure) changes from the state of the idle 61 to the bus enable lead 62,
The process sequentially shifts to the read request 63, the read-ac wait 64, and the read-ac determination 65.

In FIG. 4j, idle is "I", read bus enable is "B", read request is "R", read ack wait is "W", read ack determination is "E",
The finish data read is represented by "F" and the ACK CPU read state is represented by "C". The write bus enable is represented by “b”, the write request is represented by “r”, the write acknowledgment wait is represented by “w”, the write acknowledgment is represented by “e”, the finish data write is represented by “f”, and the ac CPU write state is represented by “c”. ing.

The data transfer rate on the Rambus 21 is synchronized with the bus clock (e in the figure). Further, the state transition is performed in synchronization with the synchronous clock (f in the figure). In the state of the read bus enable 91, the bus enable signal (h in the figure) changes to low level and becomes active. In the read request 92 state,
The first request packet 93 is sent from the high-speed memory control circuit 11 to the high-speed memory 12 via the bus control signal (i in the figure) and the bus data signal (j in the figure). Nothing is done in the state of the read-ac wait 94.

In this example, since a negative response is returned to the first request, the negative acknowledgment response packet 96 is received in the read-ac determination 95. At this time, the CPU 13 has already issued a write transaction instruction, and at time T ₂₂ , the CPU controller 35 has output a write start signal (c in the figure). Therefore, instead of the miss delay read 68, the state of the bus enable write 97 is entered, the bus enable signal becomes active again, and then the write request packet 99 is sent in the state of the write request 98.

The state controller 44 receives the response packet 102 indicating permission of the request from the high speed memory 12 in the state of the ACK determination write 101. Further, in the state of the ACK determination write 101, the high speed memory control circuit 11 sends the write data packet 103 through the bus data signal. Having received the permission response, the state controller 44 sequentially executes the states after the finish data write 104. Here, since the data count value is “1” and all the write data has been transferred in the state of the ACK determination write 101, the write data packet is not transferred in the state of the finish data write 104.

After that, at time T ₂₃ when the state of the AC CPU write 105 shifts, the write completion signal (d in the figure) is output. After returning to the idle state 106 once, the read transaction is retried. Read ack judgment 10 in the second read transaction
6, the response packet 1 of the permission response from the high speed memory 12
07 is received.

Therefore, the finish data read 10
8 and receives the read data packet 109
This state is repeated until. Read data packet
When the reception of the packet 109 is completed, the AC CPU lead
Start at time 111 _{twenty five}Read completion signal
b) is output. After that, as shown in Figure 3, CP
A read ready signal is output from the U controller 35 and the CPU 13
When the transfer of read data to the
End.

For example, when a read transaction and a write transaction occur at the same time, a negative response is received by either transaction, and waiting processing is simply performed for the miss delay time, 26 clocks are required to complete the two transactions. I needed it. By executing the other transaction during the waiting time after receiving the negative response, it becomes possible to execute this in 20 clocks.

In the embodiment described above, the transition to the bus enable of the other transaction is made only from the read ACK determination state and the write ACK determination state.
The state may be changed from the miss delay read or miss delay write state.

For example, when a negative response is received in the read ACK determination state and there is no instruction to start writing, the state transits to the miss delay read state once. When a write start signal is generated while the miss delay read state is being executed, the state immediately shifts to the bus enable write state and a write transaction is performed. In this way, when the start signal of the other transaction arrives in the miss delay state, the high-speed memory can be accessed more efficiently by shifting to the requested transaction and advancing the state.

Further, when the remaining time until exiting the miss delay state is a fixed value or less, the transition to the transaction may be prohibited even if the other start signal arrives. For example, when the initial value of the miss delay count is "4" and the value is "2" or less, the transaction is prevented from proceeding to the other transaction. In this way, the execution of the transaction that has received the negative response is not kept waiting longer than the execution time of the other transaction plus the length of two clocks. If there is no limitation, the execution time of the other transaction is delayed by 4 clocks.

In the embodiment, the presence / absence of a transaction of a different type from the transaction for which a negative response is received among the write transaction and the read transaction is checked, but the presence / absence of the same type of transaction may be checked. Good. For example, when a negative response is received for the read request packet and there is another read request, the corresponding read request packet may be transmitted. In this case, the state transition is not distinguished according to the type of operation like the transition path for writing and the transition path for reading, but the state transition is performed for each transaction like the first transaction and the second transaction. It will be managed.

Then, whether each transaction is a write or a read is stored in a predetermined register and managed. Also, although two request packets of the same type are generated, the generated request packets may be stored in the buffer memory.

[0107]

As described above, according to the first aspect of the present invention, if another access request exists when a negative response is received from the high-speed memory, the other access request is not entered in the waiting state. Sent to high speed memory. As a result, the read / write operation corresponding to another access request can be advanced during the waiting time until the access request that receives the negative response is sent again, and the data access efficiency can be improved.

According to the invention described in claim 2, even if there is no other access request at the time of receiving the negative response,
When a new access request is generated within a fixed time, it is sent to the high speed memory. Thereby, the access efficiency to the high speed memory can be further improved. Also, if the waiting time for the generation of a new access request is set to a fixed time shorter than the waiting time after receiving a negative response, it takes a long time to finish the transaction that receives a negative response due to the execution of another transaction. It can be prevented from becoming too much.

Further, according to the invention described in claim 3, since the buffer memory for temporarily storing the write data is provided, for example, both the write instruction and the read instruction from the bus master device can be accepted in parallel. .

According to the fourth aspect of the invention, since only the write operation and the read operation can be processed in parallel, state management is facilitated and the circuit configuration can be prevented from becoming complicated.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a high speed memory control circuit according to an embodiment of the present invention.

FIG. 2 is a state transition diagram showing transitions of states managed by the state controller shown in FIG.

FIG. 3 is a waveform diagram showing an example of waveforms of various signals transmitted and received between a CPU and a high-speed memory control circuit.

FIG. 4 is a waveform diagram showing an example of waveforms of various signals transmitted and received between the high speed memory control circuit and the high speed memory.

FIG. 5 is an explanatory diagram showing an example of a bit configuration of a request packet.

FIG. 6 is an explanatory diagram showing an example of a bit configuration of a response packet.

FIG. 7 is a truth table showing the values of two bits of a response packet and the notification content of the response packet indicated by them.

FIG. 8 is an explanatory diagram showing an example of the configuration of a data packet.

FIG. 9 is an explanatory diagram showing a transfer procedure of each packet in a read transaction.

FIG. 10 is an explanatory diagram showing a transfer procedure of each packet in a write transaction.

FIG. 11 is a block diagram showing an outline of a configuration of a high speed memory.

FIG. 12 is a block diagram showing an outline of a configuration of a conventional high-speed memory control circuit.

13 is a state transition diagram showing state transitions managed by the state control circuit shown in FIG.

FIG. 14 is a waveform chart showing an example of waveforms of various signals transmitted and received between the CPU and the high-speed memory control circuit when a transaction is performed.

15 is a waveform diagram showing an example of waveforms of various signals transmitted and received between the high-speed memory control circuit and the high-speed memory when a transaction is performed according to the sequence shown in FIG.

[Explanation of symbols]

 11 high-speed memory control circuit 12 high-speed memory 13 CPU 14 address signal 15 CPU control signal 16 data signal 17 read ready signal 18 write ready signal 19 clock signal 21 Rambus 31 write request packet generator 32 read request packet generator 33 transmission latch 34 Internal Register 35 CPU Controller 38 Transmission Selector 43 Interface Circuit 44 State Controller 45 Ac Judgment Device 47 Reception Gate

Claims (4)

[Claims] 1. A negative response is returned when an access request representing one of a data read request and a data write request is received and the request cannot be satisfied until a predetermined waiting time elapses. , Request sending means for sending the access request to the high speed memory, which returns an authorization response when immediately responding, and sending to the high speed memory when the negative response is received from the high speed memory for the sent access request Determination means for determining whether or not there is another access request to be issued, and another request transmission means for transmitting the access request to the high-speed memory when this determination means determines that there is another access request, When the determination unit determines that there is no other access request, the access request that has received the negative response is returned after the predetermined waiting time. And a data read / write unit for reading / writing data according to the access request from the high speed memory when receiving the permission response from the high speed memory. A high-speed memory control device characterized by: 2. A negative response is returned when an access request representing one of a data read request and a data write request is received and the request cannot be satisfied until a predetermined waiting time elapses. , Request sending means for sending the access request to the high-speed memory that returns an authorization response when immediately responding, and the high-speed memory when the negative response is received from the high-speed memory for the sent access request Discriminating means for discriminating whether or not there is another access request to be transmitted, and when the discriminating means judges that there is another access request, the first other request for transmitting the access request to the high-speed memory. The sending means and the determining means determine that there is no other access request, and a fixed time shorter than the predetermined waiting time after receiving the negative response. When another access request to be sent to the high-speed memory occurs before the lapse of time, a second other request sending means for sending this to the high-speed memory, and the determining means determines that there is no other access request. And when no other access request occurs before the lapse of the certain time after receiving the negative response, the high-speed memory after the lapse of the predetermined waiting time after receiving the negative response of the access request receiving the negative response And a data read / write unit for reading / writing data according to the access request from the high speed memory when the permission response is received from the high speed memory. High-speed memory controller. 3. The high speed memory control device according to claim 1, wherein the request sending means comprises a buffer memory for temporarily holding data to be written in the high speed memory. 4. The another access request is an access request of a type different from the previously sent access request of the data read request and the data write request. High speed memory controller.