JPH09237076A - Picture display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a picture display system and to attain alternating, colorful and complex picture display in which continuous picture processing can be performed by overcoming slight malfunction such as inversion of data delivered between ICs without performing a measure for malfunction such as periodical reset for a extremely short period (it cannot be helped to reset a system at the time of runaway of a CPU) on the assumption that malfunction by an external noise can be hardly prevented. SOLUTION: When data indicating processing contents to registers RP0-RP7 of a video processor 3 is written, a host processor 6 generates check codes for detecting an error for each prescribed data block and adds them, and writes the check codes. After the prescribed check codes are written in the registers RP0-RP7, the video processor 3 examines whether the data has an error or not utilizing a check code added to the data block, when an error is detected, repeat is requested.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display system, and more particularly to a technique for realizing complicated image processing in an electrically poor environment.

2. Description of the Related Art As an example of an image display system of the present invention, the present invention can be applied to a game display on a pachinko machine which displays an image simulating a throttle machine, shogi, go, person, vehicle, and the like. A CRT or a liquid crystal display panel is used as an image display of this pachinko machine, and various ingenious game images are displayed on it, for example, such as a throttle machine, shogi, go, person, vehicle, etc. It A microprocessor (CPU), which is the center of various electronic controls, is mounted on the pachinko machine (a microcomputer system is incorporated), and image display control relating to the game display is performed by the CPU.

[Problems to be Solved by the Invention] The electrical environment in a pachinko parlor, where a large number of pachinko balls move around at high speed, is poor, and the electronic circuit is apt to malfunction due to electromagnetic induction noise or electrostatic discharge noise. ing.
There is also a tradeoff with the cost required for noise countermeasures such as electromagnetic shielding, and it is extremely difficult to fully protect the individual microcomputer systems incorporated in each pachinko machine from a bad noise environment. For this reason, the conventional pachinko machine microcomputer system takes inevitable malfunctions due to intense and frequent disturbance noise, and takes measures so as not to hinder practical use even if an abnormality caused by disturbance is induced. The countermeasure is to reset the microcomputer system periodically in a very short period.
As is well known, a sprite method is generally used as image processing for displaying a fast-moving image for a game on a CRT or LCD display at high speed. In this method, a large number of graphics (image element data) to be moved on the screen are registered in a memory in advance (called a cast ROM), and if only the graphics and their display positions are specified, the graphics designated as the background can be used as hardware. And display it on the screen. That is, the process of reading the data of the specified figure from the cast ROM and writing it to the specified position of the video RAM is repeated at high speed. Also in this sprite type image processing, periodic resetting is performed as a countermeasure against the above-mentioned noise. The reset cycle is several tens of milliseconds.
Next, the system saves information about which figure is to be placed where, resets the system, and when the system returns from the reset, the specified figure is displayed at the specified position based on the saved information.
Even if a part of the image being processed is destroyed by the disturbance noise as described above, the next image data is immediately updated by resetting every several tens of milliseconds. Therefore, the microcomputer
Even if the displayed image is often disturbed due to the malfunction of the system, the user (pachinko player) hardly notices it. However, there is a problem that it is difficult to realize a complicated game image display that is rich in changes by a malfunction countermeasure that is a periodic reset with an extremely short cycle. It is necessary to use a combination of continuous multi-step processes to realize a variety of colorful and complicated image displays. If you increase the number of consecutive processing steps,
You can create more advanced display effects. However, if the reset is periodically repeated within a short time, the number of continuous processing steps is uniquely limited by the reset cycle. When performing advanced image processing, a method of interrupting the continuity of image processing such as system reset cannot be used. Further, the above-mentioned problem is not limited to the image display system of the pachinko machine, and similar problems occur in other game machines, TV games and the like. Moreover,
The same problem occurs in a system that displays a predetermined image on a CRT or the like attached to a terminal for configuring a TV conference system, a surveillance system, or other systems. Due to the circumstances described in detail above, the conventional image display system for pachinko machines and the like cannot realize complicated and varied game image display. The object of the present invention is based on the premise that malfunctions due to disturbance noise are unavoidable, and does not take measures against malfunctions such as periodic resets with a very short cycle (it is unavoidable to reset the system when the CPU is out of control). ), Overcoming a minor malfunction such as inversion of data transferred between ICs and performing continuous image processing, and therefore providing an image display system capable of realizing a variety of complex and complex image displays. is there.

The image display system of the present invention has, as a basic configuration, a first storage means in which a large number of image element data are stored in advance, and a first storage means for storing image data to be displayed. Second storage means, a video processor which reads out the image element data from the first storage means and edits and edits the image element data as appropriate to generate image data in the second storage means, and the video processor is the second storage means.
A display controller for receiving the image data read from the storage means and displaying the image on a display, and a host processor for instructing the video processor about the processing contents of the image editing process. The invention described in each claim is based on such a basic configuration and has the following characteristic requirements. When the host processor writes data instructing the contents of processing to the register of the video processor, it generates and adds a check code for error detection for each predetermined data block, and also writes the check code. Whether the video processor receives a predetermined data block written in the register by the host processor and uses the check code added to the data block to determine whether or not there is a data error. When it detects an error, it requests the host processor to retransmit the data block. The invention according to claim 1 satisfies the requirements. The image element data stored in the first storage means is added with a check code for error detection for each predetermined data block. When the video processor reads the data from the first storage means, the video processor checks whether or not there is an error in the data by using the check code added to each of the data blocks, and detects the error. In that case, the data is read again. Then, the invention according to claim 2 satisfies the requirements. When writing data in the second storage means, the video processor generates and adds a check code for error detection for each predetermined data block, and also writes the check code. The video processor, when reading the data from the second storage means, checks whether or not there is an error in the data by using the check code added to each of the data blocks, and detects the error. In that case, the data is read again. The invention according to claim 3 satisfies the requirements. When the host processor reads data from a predetermined register of the processor, the video processor generates a check code for error detection for each predetermined data block read, and the check code is used as the check code for the data block. Then, write to a predetermined register so that it can be read continuously. When reading data from a predetermined register of the video processor, the host processor also reads the check code added to a predetermined data block and uses the check code to determine whether there is a data error. And if an error is detected, the data is read again. The invention according to claim 4 satisfies the requirements. Then, in the description of the embodiments described below, the invention described in each claim, that is, what has all the requirements ~ is described, but the present invention is independent of any claim, or arbitrary Of course, the combination of the claims may be realized. Further, the video processor according to claim 3,
When a data error is detected by using the check code as in the requirement when reading the data from the second storage means, the data is read again and the error detection event is detected by the host. A report is sent to the processor, and based on the report, the host processor is configured to monitor the data abnormality status of the second storage means over time (claim 5). Further, in the configuration of claim 5, when the host processor determines that a large data abnormality has occurred as a result of monitoring the data abnormality state of the second storage means based on the report, The video processor may be instructed to recreate the image data (claim 6). Further preferably, the host processor writes resuming operation information for ending the runaway in a predetermined register of the video processor in a timely manner, and in the recovery process when the runaway occurs and ends, the video processor A function is provided for reading the restart operation information from the register and restarting the operation according to the information (claim 7).

BEST MODE FOR CARRYING OUT THE INVENTION First, an example applied to a pachinko machine image system, which is one of the usage modes of the image processing system according to the present invention, will be described. (A) Basic Configuration of System The basic configuration of an image display system for a pachinko machine according to an embodiment of the present invention is shown in FIG. As described above, the system stores the cast ROM 1 which is the first storage means in which a large number of image element data (corresponding to the above-mentioned figures) are stored in advance, and the bitmap image data to be displayed. The second storage means, video R
AM2, a video processor 3 that reads image element data from the cast ROM 1 and appropriately edits and processes it to generate bitmap image data in the video RAM 2, and a CRT that receives the bitmap image data that this video processor 3 reads from the video RAM 2 A CRT controller 5 for displaying the image on the display unit 4 and a host processor 6 for instructing the video processor 3 on the processing content of the image editing processing are provided. The host processor 6 is a CPU that is the center of electronic control of each part of the pachinko machine. These are mounted on one or several wiring boards and incorporated into one pachinko machine. (B) Data transfer from host processor 6 to video processor 3 CP of host processor 6 in video processor 3
FIG. 2 shows a configuration example of the interface circuit section with the U bus 7. The data transferred from the host processor 6 to the video processor 3 is an instruction (instruction) of a process executed by the video processor 3 and a parameter accompanying the instruction. Since the total amount of data of one instruction and its associated parameter is limited, the number of registers corresponding to it is set in the video processor 3. In this example, the number of required registers is eight. As shown in FIG.
The eight registers have a two-stage configuration including an input / output register RP (0 to 7) directly connected to the CPU bus 7 and an actual register RS (0 to 7) connected to the internal bus of the video processor 3. Further, a register RCS for storing the checksum transferred from the host processor 6, an adder 8, a register SUM for storing the output of the adder 8, the contents of the checksum register RCS and the addition register SU.
A comparator 9 for comparing the contents of M, a flag register FAIL for transmitting the comparison result to the host processor 6,
A buffer 10 that outputs the contents of the addition register SUM to the host processor 6 and a timing control unit 11 associated with these are provided. The contents of the addition register SUM and the flag register FAIL are set to "0" in the initial state. Input / output registers RP0-R from the host processor 6
When data is transferred to P7, every time one data is received, the data is accumulated in the adder register SUM while being added by the adder 8. The host processor 6 generates a checksum of the series of data (for example, 8 pieces of data) at the end, transfers the checksum to the video processor 3, and stores the checksum in the register RCS.
Input / output registers RP0 to RP7 from the host processor 6
When 8 pieces of data are transferred to the addition register SU
The addition result of eight pieces of data is stored in M. Immediately after that, the host processor 6 sends the checksum register RC
Eight data checksums are transferred to S. At this stage, in the video processor 3, the contents of the checksum register RCS and the contents of the addition register SUM are compared by the comparator 9, and if they match, the contents of the input / output registers RP0 to RP7 are changed to the actual register RS0. ~ RS
7, the video processor 3 advances the processing according to the contents. If the contents of the checksum register RCS and the contents of the addition register SUM do not match, the contents of the input / output registers RP0 to RP7 are changed to the actual register RS0.
~ Without moving to RS7, the comparator 9 sets the flag register FA
By setting IL to “1”, the host processor 6
Request to retransmit data. The contents of the addition register SUM are cleared immediately after the comparison operation. The set flag register FAIL is cleared by the host processor 6 writing "0" in it. As described above, error detection processing is performed at the time of data transfer from the host processor 6 to the video processor 3, and when an error in the data received by the video processor 3 is detected, the same data is retransferred from the host processor 6. get. (C) Operation in which the host processor 6 reads out data from the video processor 3 The video processor 3 outputs data to be transmitted to the host processor 6 via the actual register RS to the input / output register RP.
, And the host processor 6 reads the data of the input / output register RP from the CPU bus 7. As the host processor 6 sequentially reads the data from the input / output registers RP0 to RP7, the video processor 3 sequentially adds the data by the adder 8 and stores it in the addition register SUM. When all the data are read, the checksums of those data are stored in the addition register SUM. The host processor 6 reads the data (checksum) of the addition register SUM immediately after reading all the data from the input / output register RP, compares the checksum with the checksum generated inside the host processor 6, and reads the data. To verify. If an error is detected, read the data again. (D) Operation of Video Processor 3 Reading Data from Cast ROM 1 The video processor 3 operates in response to an instruction from the host processor 6, reads predetermined image element data from the cast ROM 1 and performs an appropriate editing process. Even when the video processor 3 reads data from the cast ROM 1, the data is verified by the checksum. Here, as an example, one checksum is added to every seven original data (image element data) of the cast ROM 1. The data array in the cast ROM 1 is as shown in FIG. The seven data stored between the addresses = x000 to x110 are original data, and the data of x111 is a checksum of these seven data (x is an arbitrary value). In this example, since 8 data including the checksum is used as one unit, each data in the cast ROM 1 is stored with the address of the lower 3 bits of the address being (000) as the head. Cast R in video processor 3
An example of the configuration of the data reading portion of the OM1 is shown in FIG. The video processor 3 sequentially reads 7 pieces of data starting from the address = x000 in the cast ROM 1 and stores them in the 7 input registers CP0 to CP6. At that time, simultaneously, seven pieces of data are sequentially added by the addition register SUM. Further, the data (checksum) at the address = x111 is read into the checksum register RCS after the seven data. Then, the contents of the addition register SUM and the contents of the checksum register RCS are compared by the comparator 91 (the addition register SUM is initialized immediately after the comparison). If they match, the contents of the input registers CP0 to CP6 are transferred to the actual registers CS0 to CS6 and the next process is performed. If they do not match, the same data read operation is performed again. (E) Video RAM 2 Access Operation by Video Processor 3 The video processor 3 frequently accesses the video RAM 2 to create bitmap image data, reads the image data, and transfers it to the CRT controller 5. In the write / read access, the video processor 3 verifies the data by the parity check as follows. At the time of write access, as shown in FIG. 5, the specified number of bits of data to be written is stored in the data register 51, and the address to be written is stored in the address register 52. Register 51
The data set in 1 is input to the parity generation circuit 53, a parity bit corresponding to the data is created, and set in the parity register 54. Similarly, the address set in the register 52 is input to the parity generation circuit 55, a parity bit corresponding to the address is created, and set in the parity register 54. Then, the specified number of bits of data set in the register 51 and the two parity bits set in the parity register 54 are written to the address indicated by the register 52 of the video RAM 2. On the other hand, in the case of read access, as shown in FIG. 6, the address to be accessed is set in the register 61, and the data read from the address (with two parity bits) is stored in the data register 62 and the parity register 63. Set.
The address that accessed the video RAM 2 is also input to the parity generation circuit 66, a parity bit corresponding to the address is created and transmitted to the comparator 67. Video RA
The address / parity bit of the data read from M2 is supplied from the register 63 to the comparator 67, and is compared and verified with the bit from the parity generation circuit 66. In addition, the register 6 read from the video RAM 2
Data stored in 2 (data with originally specified number of bits)
Is also supplied to the parity generation circuit 64, a parity bit corresponding to the data is created and transmitted to the comparator 65. At the same time, the data parity bit of the data is supplied from the register 63 to the comparator 65 and is compared and verified with the bit from the parity generation circuit 64. If both the address parity check and the data parity check are correct, the output of the AND circuit 68 is "1".
Then, the read data is processed. If an error is detected in one of the parity checks, the data read process is performed again. When an error is detected in this parity check, the video processor 3 reports the error detection event to the host processor 6 in a predetermined procedure. Based on the report, the host processor 6 monitors the data abnormal situation of the video RAM 2 over time. As a result of the monitoring, when it is determined that a large data abnormality has occurred in the video RAM 2, the host processor 6 instructs the video processor 3 to recreate the image data. The above function works extremely effectively in the following cases. It is conceivable that the bit map image data on the video RAM 2 is largely destroyed by the large disturbance noise. In that case, a parity error frequently occurs in the process of the video processor 3 reading and accessing the video RAM 2. The host processor 6 monitors such an abnormal situation based on the report from the video processor 3, and if it judges that the degree of the data abnormality is too severe, it prompts to recreate (repair) the image data. , A terrible image of destruction C
You can create and display a restored image in a very short time without displaying it on RT4. (F) Execution State Saving Register By the processing with the requirements described in detail above, the reliability of the data transferred from the host processor 6 to the video processor 3 is sufficiently improved even in an environment where there is a great deal of disturbance. When the host processor 6 runs out of control, the probability of transferring a normal checksum is extremely low, so that the probability that data normally written immediately before the runaway will be rewritten by the runaway is also extremely low. In case the host processor 6 itself runs out of control using this characteristic, a register for writing the status of the host processor 6 as needed is installed in the video processor 3 (this is called an execution status saving register). . When the host processor 6 runs out of control, the host processor 6 reads the contents of the execution state storage register of the video processor 3 in the recovery process at the end of the runaway, thereby knowing the state immediately before the runaway, and executing the best recovery process. Alternatively, immediately before the host processor 6 executes a certain process, a return state in the case of a runaway during the execution of the process is stored in the save register, and the save register of the save register is stored in the return process from the runaway state. The contents are read out, the initial state of the host processor 6 is set, and the process is re-executed. Next, an example in which the image processing system according to the present invention is applied to a videotex, which is one of usage forms, will be described. As is well known, Videotex is one of the systems for retrieving text / image information in an information center using a public telephone line. FIG. 7 shows a block diagram of a control unit of a terminal device which constitutes such a videotex. The CPU 10 includes a ROM 11 that stores programs and the like via an internal bus, a RAM 12 that stores an image control code correspondence table and various data, and a CRT.
Video RAM 1 for storing screen data to be displayed on 13
4, NCU / modem 15 for communicating with the center 20,
A keyboard interface 17 that receives an input from the keyboard 16 including a numeric keypad and a start key and a video disk interface 19 for controlling the operation of the video disk 18 are connected. The video disk 18 is an example of an image signal output device. The NC
The U / modem 15 is connected to the center 20 via a line,
The keyboard interface 17 is the keyboard 16
Is connected. The video RAM 14 has a CRT.
13 is connected to the video disc interface 19
Outputs an operation control signal to the video disk 18, and switches the screen of the CRT 13 to the contents of the video RAM 14 or the image signal of the video disk 18. The basic videotex communication system concerned
For example, it is disclosed and disclosed in Japanese Patent Publication No. 7-105944. In the relationship with the present invention, the ROM 11 and the video disk 18 in the above configuration are the first
The first storage means corresponds to the cast ROM 1 in the embodiment. Then, image element data such as a menu screen is recorded in the ROM 11 and is displayed on the CRT 13 as necessary, so that the time required for the display is shortened. The video RAM 14 is a second storage means. The CPU 10 has the functions of the video processor 3 and the host processor 6. Therefore, the CPU 10 monitors the data as in the above-described embodiment of the pachinko machine, and performs a predetermined process when there is an abnormality. Although not shown in FIG. 7, CR
T13 is controlled by the CRT controller.
FIG. 8 shows an example in which the image processing system according to the present invention is used in a video conference system. That is, the video conference system is a system in which a conference room at a remote place is alternately connected by audio and video so that a conference can be held while staying in different places. This figure is a block diagram of each terminal that constitutes the video conference system, and for example, one using a workstation as a host computer can be used. The structure of the input unit 2 will be described below.
Reference numeral 1 is a keyboard or the like, and is provided with various code keys and function keys in addition to character keys. Various control commands and information / messages to conference participants can be input. In addition, the input unit 21
The first storage unit 28 is connected, and the first storage unit 28 is connected.
The image data stored in it can be read and transferred. The first storage unit 28 corresponds to the cast ROM 1 in the embodiment of the pachinko machine, and stores various basic image data (image element data). This basic image data is, for example, data relating to the profile of the participant, graphs and image data (moving image / still image) necessary for giving a certain explanation, and the like. In other words, in the case of a video conference, the video image data obtained by capturing the image with a video camera installed in each conference room is transferred to the other party as it is, and the terminal that receives it displays it as it is. However, in this example, a part of the basic image data is stored in the first storage unit 28, and by displaying it, the time required for image display can be shortened. Further, the input unit 2
The mode flag identifying section 22 connected to 1 identifies the mode of the input destination at the time when various input signals are obtained. The communication control unit 23 controls communication with other terminals, and sends and receives necessary signals when communication with other terminals is required. The second storage unit 24 is composed of a RAM or the like, and stores the type of set mode, input data, received data, and the like. Furthermore, the image data to be displayed on the display unit is also stored. The voice control unit 25 controls voice input and voice output. Video processor 2
Reference numeral 9 acquires the predetermined image element data stored in the first storage unit 28 and edits and processes it as necessary to generate a display image, and stores the display image in the second storage unit 24. It has a function of outputting the data stored in the storage unit 24 to the display unit 27. In addition, the calculation unit 26 performs various calculations, and is composed of a CPU or the like, for example, when a vote is made in a video conference, the data from each terminal is totaled and a calculation process is performed. Further, it also has a function as a host processor for instructing the video processor 29 to perform edit processing. The specific functions of the video processor 29 and the host of the arithmetic unit 26 are the same as those of the pachinko machine. In addition, the display unit 27 is CR
It is composed of a TV screen such as T, and displays the set function information, calculation results and the like. And
When compared with each of the above-described embodiments, for example, the display unit 27
It is equipped with a CRT controller and a CRT.

According to the present invention, each of the host processor, the video processor, the cast ROM, the video RAM, and the display controller constituting the image display system can be used even in an environment with a lot of electromagnetic disturbance such as a pachinko machine. The reliability of data transferred between ICs is kept sufficiently high. Therefore, as in the past,
It is not necessary to repeat the system reset at a cycle of several tens of milliseconds on the assumption that the data to be transferred is often destroyed by the disturbance. In other words, in this invention,
There is no need to adopt a method of interrupting the continuity of image processing by periodical reset of a very short cycle, advanced image processing can be performed by a combination of continuous multi-step processing, and a variety of complicated game image display Can be realized. The present invention is not limited to a pachinko machine, and can be applied to not only various pachislot machines and other game machines and TV games, but also video conferencing systems, videotex and other image processing as shown in the embodiment section. It can be applied to the system. That is, even in a video conference system, a videotex, etc., there is also a need to install a terminal used for the device in a place where there is a lot of disturbance noise such as a factory, so that the above-described various effects can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of an image display system for a pachinko machine according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an interface circuit unit with a CPU bus 7 of a host processor 6 in the video processor 3 of the above embodiment.

FIG. 3 is a block diagram showing a configuration example of a data reading portion of a cast ROM 1 in the video processor 3 of the above embodiment.

FIG. 4 is a conceptual diagram showing an example of data arrangement in the cast ROM 1 of the above embodiment.

FIG. 5 is a block diagram of a write access circuit unit of the video RAM 2 in the video processor 3 according to the embodiment.

FIG. 6 is a block diagram of a read access circuit section of the video RAM 2 in the video processor 3 according to the embodiment.

FIG. 7 is a block diagram showing a basic configuration of an image display system (terminal) of Videotex according to an embodiment of the present invention.

FIG. 8 is a block diagram showing a basic configuration of an image display system (terminal) of a video conference system according to an embodiment of the present invention.

[Explanation of symbols]

 1 cast ROM (first storage means) 2 video RAM (second storage means) 3 video processor 3 4 CRT display 5 CRT controller (display controller) 6 host processor

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location G06F 11/14 310 G06F 11/14 310G 12/16 320 7623-5B 12/16 320A (72) Invention Person Masahiro Abe, Omron Co., Ltd., 10 Hanazono-Tudo-cho, Ukyo-ku, Kyoto-shi, Kyoto (72) Inventor Kenshi Mino, 10 Ohana-Hakuzono-Tudo-cho, Ukyo-ku, Kyoto-shi, Kyoto (72) Inventor Haruo Tate, Kyoto Omron Co., Ltd. 10 Hanazono-Tudo-cho, Ukyo-ku, Kyoto Prefecture (72) Inventor Takanori Oka 10 Ohana Ryodou-cho, Hanazono-Tudo-cho, Ukyo-ku, Kyoto City, Kyoto Prefecture (72) Inventor Kazuo Honda Kyoto 10, Hanazono-Tudo-cho, Ukyo-ku Omron Co., Ltd. (72) Inventor Yasuo Kasahara 10, Hanazono-Tudo-cho, Ukyo-ku, Kyoto-shi, Kyoto Omron Corporation Within the company

Claims (7)

[Claims] 1. A first storage means in which a large number of image element data are stored in advance, a second storage means for storing image data to be displayed, and image element data from the first storage means. A video processor that reads out the image data and appropriately edits the image data to generate image data in the second storage means, and the video processor receives the image data read from the second storage means and displays the image on a display. An image display system comprising: a display controller; and a host processor for instructing the video processor of processing contents of image editing and processing, and the following requirements. When the host processor writes data instructing the contents of processing to the register of the video processor, it generates and adds a check code for error detection for each predetermined data block, and also writes the check code. Whether the video processor receives a predetermined data block written in the register by the host processor and uses the check code added to the data block to determine whether or not there is a data error. When it detects an error, it requests the host processor to retransmit the data block. 2. A first storage means in which a large number of image element data are stored in advance, a second storage means for storing image data to be displayed, and image element data from the first storage means. A video processor that reads out the image data and appropriately edits the image data to generate image data in the second storage means, and the video processor receives the image data read from the second storage means and displays the image on a display. An image display system comprising: a display controller; and a host processor for instructing the video processor of processing contents of image editing and processing, and the following requirements. The image element data stored in the first storage means is added with a check code for error detection for each predetermined data block. When the video processor reads the data from the first storage means, the video processor checks whether or not there is an error in the data by using the check code added to each of the data blocks, and detects the error. In that case, the data is read again. 3. A first storage means for storing a large number of image element data in advance, a second storage means for storing image data to be displayed, and image element data from the first storage means. A video processor that reads out the image data and appropriately edits the image data to generate image data in the second storage means, and the video processor receives the image data read from the second storage means and displays the image on a display. An image display system comprising: a display controller; and a host processor for instructing the video processor of processing contents of image editing and processing, and the following requirements. When writing data in the second storage means, the video processor generates and adds a check code for error detection for each predetermined data block, and also writes the check code. The video processor, when reading the data from the second storage means, checks whether or not there is an error in the data by using the check code added to each of the data blocks, and detects the error. In that case, the data is read again. 4. A first storage means for storing a large number of image element data in advance, a second storage means for storing image data to be displayed, and image element data from the first storage means. A video processor that reads out the image data and appropriately edits the image data to generate image data in the second storage means, and the video processor receives the image data read from the second storage means and displays the image on a display. An image display system comprising: a display controller; and a host processor for instructing the video processor of processing contents of image editing and processing, and further comprising the following requirements. The video processor, when the host processor reads data from a predetermined register of the processor, generates a check code for error detection for each predetermined data block to be read, and outputs the check code to the data block. Write to a predetermined register so that it can be read continuously. When reading data from a predetermined register of the video processor, the host processor also reads the check code added to a predetermined data block and uses the check code to determine whether there is a data error. And if an error is detected, the data is read again. 5. The video processor according to claim 3, wherein when the data error is detected by using the check code as in the requirement at the time of reading the data from the video RAM, the video processor reads the data again. In addition to the above, the error detection event is reported to the host processor, and based on the report, the host processor monitors the data abnormal condition of the video RAM with time, based on the report. . 6. The method according to claim 5, wherein when the host processor determines that a large data abnormality has occurred as a result of monitoring the data abnormality state of the second storage means based on the report, An image display system characterized by instructing a video processor to recreate image data. 7. The method according to claim 1, wherein
The host processor writes resuming operation information for ending the runaway into a predetermined register of the video processor in a timely manner, and the resuming operation is performed from the register of the video processor in a recovery process when the runaway occurs and is ended. An image display system characterized by reading information and restarting operation in accordance with the information.