JP2981010B2 - Terminal control method for disaster prevention monitoring device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a CPU for each of a host control device installed at a monitoring center or the like and a terminal control device installed at a site, and transmits a control command by specifying a terminal address from the host. The present invention relates to a terminal control method of a disaster prevention monitoring device that controls a disaster prevention device or the like connected to a terminal side.

[0002]

2. Description of the Related Art In a conventional disaster prevention monitoring device, a plurality of terminal control devices are connected via a transmission line to a host control device installed at a central monitoring center or the like, and a fire or the like is connected to the terminal control device.
A sensor such as a gas leak is connected, and a control device such as a smoke control device is connected. In such a disaster prevention monitoring device, a CPU circuit is provided in the host control device and the terminal control device,
Monitoring of terminal information and control of terminal equipment are performed by program control of the CPU circuit.

In other words, terminal information is monitored by sending a terminal information response command by designating a terminal address from an upper CPU circuit, and returning terminal information detected by a sensor from a terminal CPU circuit that has determined an address match. The return data is analyzed and, for example, in the case of a fire, a fire alarm is issued together with the fire occurrence area. Also, by transmitting a control command together with the terminal address from the upper CPU circuit, the terminal C having received the address designation is transmitted.
The PU circuit can output a control signal to its own terminal device for control.

[0004]

In the transmission of commands and data between the host controller and the terminal controller, for example, an error detection code such as a checksum is provided in the transmission format to improve transmission. The obstacle has been eliminated in theory. However, the elimination of such transmission failures is based on the premise that the upper CPU circuit and the terminal CPU circuit are operating correctly in terms of software and hardware, including execution of a microprogram,
Failures caused by malfunctions due to noise or bugs in the program cannot be excluded.

For this reason, in a normal monitoring mode for monitoring terminal information, when a response command of terminal information is transmitted from the host controller, the command data is destroyed during transmission due to noise or the like, and the command data is transformed into a control command. In such a case, an abnormal operation in which the terminal device is suddenly controlled occurs, and the reliability of the control cannot be guaranteed. A similar problem may occur suddenly due to a bug in the program, and is a major problem in operation of the disaster prevention monitoring device.

The present invention has been made in view of such a conventional problem, and has been made to reliably prevent a terminal device from malfunctioning due to a transmission failure between a host CPU and a terminal CPU or a bug in a program. An object of the present invention is to provide a highly reliable terminal control method for a disaster prevention monitoring device.

[0007]

In order to achieve this object, the present invention is configured as follows. The reference numerals in the drawings of the embodiments are also shown. First, the present invention relates to a host controller 1 provided with a host CPU circuit 7 installed in a monitoring center or the like, and one or more terminals provided with a terminal CPU circuit 13 connected to the host controller 1 via a transmission line 4. Having a control device 5 and transmitting a desired control command to the terminal control device 5 by designating an address from the host CPU circuit 7 of the host control device 1;
This control command is decoded by the terminal CPU circuit 13 of the terminal control device 5 that has obtained the address match, and the terminal control method of the disaster prevention monitoring device that controls the terminal device 6 connected thereto is targeted.

In the present invention, such a terminal control system of the disaster prevention monitoring device is provided in the host controller 1 by the terminal device 6.
And an adder circuit 11 for adding a predetermined signal voltage to a command transmission signal transmitted from the host CPU circuit 7 to the terminal when the assertion switch 10 is operated. Each of the terminal control devices 5 includes a detection circuit 16 for detecting the operation of the assertion switch 10 when the signal voltage of the transmission line 4 exceeds a predetermined value, a detection signal of the detection circuit 16 and control by the terminal CPU circuit 13. A gate circuit (20a, 20b) for outputting a control signal to the terminal device (6a, 6b) when both the terminal control signal and the terminal control signal output by decoding the command are obtained is provided.

[0009]

According to the terminal control method of the disaster prevention control device of the present invention having such a configuration, the terminal C is controlled by the host CPU circuit.
When a response command of terminal information is transmitted to the PU circuit, if it becomes a control command due to a failure in transmission such as noise, a detection signal of a signal voltage can be obtained by operating the assertion switch realized by hardware. Therefore, even if the terminal CPU circuit erroneously outputs the terminal control signal, control of the terminal device can be prevented.

Further, even if a control command is transmitted due to a soft error due to a bug in a program or the like, a detection signal indicating that the assertion switch has been operated cannot be obtained, so that malfunction of the terminal device due to the soft error can be reliably prevented.

[0011]

FIG. 1 is a block diagram showing the overall configuration of the present invention. In FIG. 1, reference numeral 1 denotes a higher-level control device, which includes a CRT 2 and a man-machine interface 3 for inputting and outputting data to an operator. As the man-machine interface 3, for example, a keyboard or a mouse is used.

The host controller 1, together with the CRT 2 and the man-machine interface 3, is installed in a monitoring center or the like. A terminal control device 5 installed at the site, for example, as a repeater, is connected to the host control device 1 via a transmission line 4. This embodiment shows a case where four terminal control devices 5 are connected to the host control device 1. Each of the terminal control devices 5 is connected to a control device 6.
For example, fire prevention equipment such as fire doors and smoke outlets are targeted. Further, a fire detector, a gas leak sensor, and the like (not shown) are connected to the terminal control device 5 so that terminal information can be returned in response to a request from the host control device 1.
Also, a unique address is set in each of the terminal control devices 5, and the higher-level control device 1 sends a command specifying the terminal address and responds to the terminal information detected by the sensor or controls the control device 6. .

That is, transmission data having a format including an address, a command, and a checksum is sent from the host controller 1. If the command from the host control device 1 is a response command for terminal information, the terminal control device 5 sends back transmission data having a format configuration including an address, data as terminal information, and a checksum. When the command from the host controller 1 is a control command, the terminal controller 5 does not basically respond, but if necessary, a command indicating the operation state of the control device 6, Data having a format configuration including data and a checksum may be returned.

FIG. 2 is a block diagram showing an embodiment of the present invention, taking one of the host control device 1 and the terminal control device 5 of FIG. 1 as an example. In FIG. 2, the host controller 1 is provided with a host CPU circuit 7, while the terminal controller 5 is provided with a terminal CPU circuit 13. The host CPU circuit 7 and the terminal CPU circuit 13 include a CPU main body, a RAM,
M, a transmission interface, and an input / output interface.

A host CPU provided in the host controller 1
The circuit 7 is provided with a transmission receiver 8 that receives transmission data from the transmission line 4 and a transmission driver 9 that outputs transmission data to the transmission line 4. The output of the transmission driver 9 is connected to the transmission line 4 via the addition circuit 11. The other input of the adder circuit 11 is provided with a voltage dividing circuit of resistors R3 and R4 in which the assertion switch 10 is connected in series. When the assertion switch 10 is turned on during terminal control, the addition voltage signal Va
Is given. A switch 21 is provided in conjunction with the assertion switch 10. When the switch 21 is turned on, a resistor R5
, A terminal control command signal is input to the host CPU circuit 7, and at this time, the host CPU 7 outputs transmission data including a control command for the terminal to the transmission driver 9.

When the assertion switch 10 is not operated, the contact is opened as shown in the figure, and one input terminal of the adder circuit 11 is set to 0V. When the assertion switch 10 is turned on, the switch contact is closed and an addition voltage signal Va is supplied to the addition circuit 11. At this time, the host CPU circuit 7 receives a terminal control command signal by turning on the switch 21 interlocked with the assertion switch 10, and executes a control Is output via the transmission driver 9, and the addition circuit 11 outputs a signal obtained by adding the addition voltage signal Va to the output signal from the transmission driver 9 to the transmission line 4.

When the terminal is controlled by operating the assertion switch 10, the terminal address is set.
Host CPU using keyboard etc. prior to operation of
What is necessary is just to set it in the circuit 7. Further, the host CPU circuit 7
, A communication indicator light 12 is provided, and is turned on in a transmission state of transmission data by the host CPU circuit 7 to indicate a transmission operation.

Next, the terminal controller 5 will be described. A transmission receiver 14 and a transmission driver 15 are provided for the terminal CPU circuit 13. Further, a detection circuit 16 for detecting an increase in the signal voltage due to the operation of the assertion switch 10 is provided on the transmission receiver 14 side. The detection circuit 16 includes a voltage comparator 17, and sets the reference voltage Vref by a divided voltage of the resistors R1 and R2. When the signal voltage from the transmission line 4 exceeds the reference voltage Vref, the host control device 1
A detection output indicating that the assertion switch 10 on the side has been operated is output to the latch circuit 19 via the noise removal circuit 18.

The noise removal circuit 18 prevents erroneous detection due to pulse noise added to the transmission signal. Latch circuit 1
9 is a terminal CPU control circuit 13 via a transmission receiver 14.
Receives latch control when a control command based on address matching is determined. In this embodiment, the detection signals latched by the latch circuit 19 are two control devices 6a and 6
b, the corresponding AN
It is input to one of the gate circuits 20a and 20b using a D gate. The other input of the gate circuits 20a and 20b is supplied with a control output from the terminal CPU circuit 13 based on the result of decoding the control command.

Relays L1 and L2 are connected to the outputs of the gate circuits 20a and 20b, and their relay contacts l1 and l2 are connected to control lines of the control devices 6a and 6b.
The control devices 6a and 6b can be driven by turning on the relay contacts l1 and l2 by the driving of L1 and L2. Next, the operation of the embodiment of FIG. 2 will be described.

FIG. 3 is an explanatory view showing a normal transmission operation in which a response command of terminal information is transmitted from the host controller 1 to monitor the terminal state. From the transmission output from the host CPU circuit 7 of the host controller 1, the transmission receiver 14 of the terminal controller 5 shown in FIG.
2 shows the time flow of the signal up to the point. In FIG. 3, first, the host CPU 7 of the higher-level control device 1 specifies a terminal address at regular intervals, for example, and outputs transmission data in a format including a control command for responding to the terminal information to the transmission driver 9. At this time, since the mode is the normal mode, the output of the voltage increase signal Va is not performed.
Also, the control command indicator lamp 12 is off.

The transmission driver 9 receiving the transmission signal from the host CPU circuit 7 supplies the driver output to the adder circuit 11 and outputs a prescribed command voltage to the transmission line 4 as shown in FIG. The command voltage output to the transmission path 4 is sent to the terminal side as shown in FIG. 3C, and the command voltage is compared by the voltage comparator 17 of the detection circuit 16 in FIG. 3D. Since the command voltage at this time is smaller than the reference voltage Vref, no detection output is obtained from the voltage comparator 17 of the detection circuit 16 and the transmission driver 15 outputs a transmission command to the terminal CPU circuit 13 based on the received signal.

The terminal CPU circuit 13 interprets that the transmission command is a response command of the terminal information, sends data of a format including detection information of the illustrated sensor to the transmission line 4 via the transmission driver 15, and The data is received by the transmission receiver 8 of the control device 1 and read by the host CPU circuit 7 to perform necessary data processing. Next, the host controller 1
The operation when the control switch is operated and the assertion switch 10 is operated at the same time will be described with reference to FIG.

When an alarm is displayed in the host CPU circuit 7 due to, for example, detection of fire in the terminal response information, the observer turns on the assertion switch 10 to control the terminal, and at the same time, the switch 21 is also turned on in conjunction with it. . The host CP receives a terminal control command signal when the switch 21 is turned on.
The U circuit 7 outputs the transmission data to the transmission driver 9 as shown in FIG. 4A, and the addition circuit 1 as shown in FIG.
Given to one.

At this time, a voltage addition signal Va accompanying the ON operation of the assertion switch 10 is input to the addition circuit 11, and the addition circuit 11 outputs the output signal of the transmission driver 9 and the voltage addition signal Va from the host CPU circuit 7. Is output to the transmission line 4 as shown in FIG. For this reason, as shown in FIG.
For example, a signal voltage which is about twice that of the normal state shown in FIG. 3 is transmitted and received by the terminal control device 5 side.

The detection circuit 16 of the terminal control device 5 determines that the assertion switch 10 has been operated when the reception voltage from the transmission line 4 becomes higher than the reference voltage Vref as shown in FIG. The detected output (H level output) is output to the latch circuit 19 via the noise removing circuit 18. At the same time, as shown in FIG. 4E, a reception voltage including a control command is supplied from the transmission receiver 14 to the terminal CPU circuit 13, and the latch circuit 19 performs a latch operation based on the result of decoding the control command. And outputs a control signal as a result of decoding the control command. Therefore, the gate circuit 20a receives both the detection signal latched by the latch circuit 19 and the control signal from the terminal CPU circuit 13, drives the relay L1, and operates the control device 6a by closing the relay contact l1.

Next, in the normal state shown in FIG. 3, for example, a response command of the terminal information is turned into a control command due to the incorporation of noise on the transmission line 4, a program bug in the host CPU circuit 7 or the terminal CPU circuit 13, or the like. When an erroneous control signal is output to the gate circuits 20a and / or 20b, the signal voltage of the transmission line 4 at this time is a normal command voltage,
No detection output indicating the operation of the assertion switch 10 is obtained, and the gate circuit 20a, 2
0b is set to the prohibited state and an erroneous control signal is output to the terminal CPU.
Even if output from the circuit 13, the control devices 6a and 6b are not operated.

[0028]

As described above, according to the present invention, the control of the terminal equipment is performed only after both the control command and the operation detection of the assertion switch are obtained. Can be reliably converted to control commands, or even if an erroneous control command is issued due to a bug in the program, etc. Can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is an embodiment configuration diagram showing one embodiment of the present invention.

FIG. 3 is an explanatory diagram showing a transmission operation in a normal mode of the present invention.

FIG. 4 is an explanatory diagram showing a transmission operation when an assertion switch is operated according to the present invention.

[Explanation of symbols]

 1: host controller 2: CRT 3: man-machine interface 4: transmission line 5: terminal controller 6, 6a, 6b: terminal equipment 7: host CPU circuit 8, 14: transmission receiver 9, 15: transmission driver 10: assertion Switch 11: Addition circuit 12: Control command indicator light 13: Terminal CPU circuit 16: Detection circuit 17: Voltage comparator 18: Noise removal circuit 19: Latch circuit 20a, 20b: Gate circuit (AND gate) 21: Switch (assertion switch 10) L1, L2: Relay

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G08B 29/18 G06F 9/00 360 G06F 13/00 354 G08B 23/00 530

Claims (1)

(57) [Claims] A host controller provided at a monitoring center or the like and having a host CPU circuit, and one or more terminal controllers connected to the host controller via a transmission line and having a terminal CPU circuit. Then, a desired control command is transmitted to the terminal control device by designating an address from the host CPU circuit of the higher-level control device, and the control command is decoded by the CPU circuit of the terminal control device having obtained the address match, and the self control is performed. In the terminal control method of the disaster prevention monitoring device that controls the terminal device connected to the host controller, an assertion switch for directly instructing the host controller to control the terminal device, and the host CPU when the assertion switch is operated. An addition circuit for adding a predetermined signal voltage to a command transmission signal sent from the circuit to the terminal side, wherein each of the terminal control devices has a transmission line signal voltage exceeding a predetermined value. The terminal CP a detection circuit for detecting the operation of the assertion switch, and the detection signal of the detection circuit and
A terminal control system for a disaster prevention monitoring device, comprising: a gate circuit that outputs a control signal to the terminal device when both a terminal control signal output by decoding a control command by a U circuit are obtained.