JPH09232375A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH09232375A
JPH09232375A JP8031035A JP3103596A JPH09232375A JP H09232375 A JPH09232375 A JP H09232375A JP 8031035 A JP8031035 A JP 8031035A JP 3103596 A JP3103596 A JP 3103596A JP H09232375 A JPH09232375 A JP H09232375A
Authority
JP
Japan
Prior art keywords
solder
semiconductor device
printed wiring
wiring board
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8031035A
Other languages
Japanese (ja)
Other versions
JP2762982B2 (en
Inventor
Hirofumi Nakajima
宏文 中島
Kojiro Shibuya
幸二郎 渋谷
Chikako Higuchi
千賀子 樋口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8031035A priority Critical patent/JP2762982B2/en
Publication of JPH09232375A publication Critical patent/JPH09232375A/en
Application granted granted Critical
Publication of JP2762982B2 publication Critical patent/JP2762982B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49109Connecting at different heights outside the semiconductor or solid-state body
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof

Abstract

PROBLEM TO BE SOLVED: To absorb the warp of a printed wiring board, enable obtaining connection of high reliability, and obtain a semiconductor device of low cost, by arranging a plurality of solder connecting members wherein tin having a spherical outline and specified surface tension is used for main material, to which lead is added. SOLUTION: A plurality of solder connecting members 1 which protrude from the surface of a board 4 and have a spherical outline are arranged. In the solder connecting members 1, tin which is fused again while applying self weight and has surface tension maintaining the height at least 75% of the original height of the outline is used as main material, to which lead is added. The loadings of the lead is preferably set to be 5-20%. For example, solder material turning to a solder bump is composed of Sn as main material and Pb whose content is 10%. A solder ball (sphere whose diameter is 0.67mm) is composed of eutectic solder (Pb 37%, Sn 63%). Then the solder material and a semiconductor device having the solder ball are prepared. Solder paste is spread on pads arranged on a printed wiring board 2, a board 4 of the semiconductor device is positioned on the pads and mounted, and reflow is performed. Thereby the sinking of a solder ball 1 whose main material is Sn is little, and its ratio is about 10%.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、基板より突出し球
形の外郭をもつ半田接続部材(以下単に半田バンプと記
す)の複数を具備する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a plurality of solder connection members (hereinafter simply referred to as solder bumps) projecting from a substrate and having a spherical outline.

【0002】[0002]

【従来の技術】基板面上に縦横に並べ配置される多数の
半田バンプをもつこの種の半導体装置として、例えば、
そのパッケージがボールグリッドアレイと呼ばれる半導
体装置が挙げられる。このボールグリットアレイは、電
子回路を形成する素子の増大や素子の高密度化に伴ない
パッケージの大型化および半田バンプの数の増大および
狭ピッチ化が進んできた。
2. Description of the Related Art As a semiconductor device of this type having a large number of solder bumps arranged vertically and horizontally on a substrate surface, for example,
A semiconductor device whose package is called a ball grid array is given. In this ball grid array, the size of the package, the number of solder bumps, and the pitch have been reduced with the increase in the number of elements forming the electronic circuit and the increase in the density of the elements.

【0003】この大型化したパッケージの半田バンプと
プリント配線板の導電パッドとの接続は、通常、フェー
スダウンと呼ばれる方法で行なわれていた。この方法
は、例えば、赤外線加熱炉のステージにプリント配線板
を置き、半田バンプを下向きにしそれぞれのプリント配
線板の導電パッドに当接させパッケージをプリント配線
板に乗せてから、赤外線加熱により半田バンプを溶融さ
せ接続する方法である。
[0003] The connection between the solder bumps of the large package and the conductive pads of the printed wiring board is usually performed by a method called face-down. In this method, for example, a printed wiring board is placed on a stage of an infrared heating furnace, the solder bumps are turned downward, and the conductive bumps are brought into contact with the conductive pads of each printed wiring board, and the package is placed on the printed wiring board. Is a method of melting and connecting.

【0004】従来、この半田バンプの材質は、主原料で
ある鉛に錫63%を含む共晶半田が使われてた。この共
晶半田による半田バンプの利点は、リフロー時のリラク
ゼーションが大きく外郭の高さは元の高さの60%程度
しか維持できないものの、プリント配線板に反りがあっ
ても、溶融部がその反りを吸収しプリント配線板のコプ
ラナテイ(平坦度)が得られるとともに溶融される半田
の表面張力によりセルフアライメント作用が働き位置ず
れが起ず接続できることであった。
Conventionally, a eutectic solder containing 63% of tin in lead, which is a main material, has been used as a material of the solder bump. The advantage of the solder bump made of the eutectic solder is that the relaxation at the time of reflow is large and the outer height can be maintained only about 60% of the original height, but even if the printed wiring board is warped, the melted portion is warped. Thus, coplanarity (flatness) of the printed wiring board can be obtained, and the self-alignment function works due to the surface tension of the melted solder, so that the connection can be performed without any positional displacement.

【0005】しかしながら、この共晶半田によるバンプ
の外郭の高さでは、プリント配線板への接続部の信頼性
が問題となってきた。この問題は、基板とプリント配線
板との熱膨張差によるバンプの接続部に働くストレスが
バンプの高さが低いため大きくなり、しかもこのストレ
スがIOポートへの通電および遮断が行なわれる毎に繰
返し加えられ、やがては、プリント配線板へのバンプの
接続部が疲労し剪断されることである。
[0005] However, the reliability of the connection portion to the printed wiring board has become a problem with the height of the outer contour of the bump made of the eutectic solder. This problem is caused by the fact that the stress acting on the connection portion of the bump due to the difference in thermal expansion between the substrate and the printed wiring board becomes large due to the low height of the bump, and this stress is repeated every time the power is supplied to and interrupted from the IO port. In addition, the connection of the bump to the printed wiring board will eventually fatigue and shear.

【0006】なお、この接続界面に作用するストレスσ
は、周知のように、σ=ΔαΔTGl/hである。ここ
で、Δαは熱膨張率の差、ΔTは変化する温度差、Gは
弾性係数、lはパッケージの中心からストレスが加わる
半田バンプまでの距離およびhは接続後の半田バンプの
高さである。このストレスを求める式は、リフロー後の
柱形状の半田バンプが弾性変形しないと仮定して成立す
るものの、リフロー時の半田バンプの高さが高く維持で
きれば、その分ストレスは小さくなり疲労破壊が起き難
い言える。
The stress σ acting on the connection interface
Is, as is well known, σ = ΔαΔTG1 / h. Here, Δα is the difference between the coefficients of thermal expansion, ΔT is the temperature difference that changes, G is the elastic coefficient, l is the distance from the center of the package to the solder bump to which stress is applied, and h is the height of the solder bump after connection. . The equation for calculating this stress is established assuming that the pillar-shaped solder bumps after reflow do not elastically deform.However, if the height of the solder bumps during reflow can be maintained high, the stress decreases and fatigue fracture occurs. Difficult to say.

【0007】そこで、近年、この半田バンプの高さを得
るために種々の試みがなされた。例えば、IEEE T
RANSACTIONS ON COMPONENT,
PA−CKAGING,AND MANUFACTUR
ING TECHNOLOG一YPARTB,VOL1
8,NO1,FEBURUARY 1995の53から
56ページに開示されている。この半田バンプは、鉛9
0%および錫10%の高融点の半田をコアにしプリント
配線板および基板の接続に比較的に低融点の共晶半田を
使用し接続する構造である。この半田バンプによれば、
リフローによる接続時にコアの溶解は少なくて済みスタ
ンドオフ(接続後のバンプ高さ)が稼げることを特徴と
するものである。
Therefore, various attempts have been made in recent years to obtain the height of the solder bump. For example, IEEE T
RANSACTIONS ON COMPONENT,
PA-CKAGING, AND MANUFACTUR
ING TECHNOLOG-YPARTB, VOL1
8, NO1, FEBURUARY 1995, pages 53-56. This solder bump is made of lead 9
In this structure, a high melting point solder of 0% and tin 10% is used as a core, and a relatively low melting point eutectic solder is used for connection between a printed wiring board and a substrate. According to this solder bump,
At the time of connection by reflow, core dissolution is small and standoff (bump height after connection) can be obtained.

【0008】また、他の例として、USパテントである
US5147084に開示されているように、目的がリ
ペアし易いように、あるいは、接続後に隣接する接続部
の接触やブリッジすることをを避けるために、高融点の
半田ボールを基板の低融点の半田に乗せその周囲をエポ
キシ樹脂で囲み、リフロー時に被接続板の低融点半田と
この高融点の半田ボールと接続し、半田ボールの高さを
維持するとともに接続部の周囲をエポキシ樹脂で取り囲
む構造である。
As another example, as disclosed in US Pat. No. 5,147,084, the purpose is to make it easy to repair the object, or to avoid contact or bridging of an adjacent connection part after connection. The high melting point solder ball is placed on the low melting point solder of the board, and the surrounding area is surrounded by epoxy resin. During the reflow, the low melting point solder of the connected board is connected to this high melting point solder ball, and the height of the solder ball is maintained. And a structure surrounding the connection portion with epoxy resin.

【0009】[0009]

【発明が解決しようとする課題】上述した高融点の半田
コアや半田ボールで形成される接続部は、剪断ストレス
を低くする高さの確保ができるものの、プリント配線板
の反りを吸収する低融点半田層の厚さを必要とする。こ
のように厚くしかも何百個という多数の半田層パターン
のそれぞれを一つも形状を崩さずに形成するのは、安価
な方法であるマスクを用いるスクリーン印刷するにして
も困難である。
The above-mentioned connection portion formed of a high melting point solder core or solder ball can secure a height to reduce shear stress, but has a low melting point to absorb warpage of a printed wiring board. Requires the thickness of the solder layer. It is difficult to form such a thick and hundreds of solder layer patterns without breaking their shapes even by screen printing using a mask which is an inexpensive method.

【0010】また、後者の半田ボールによるバンプで
は、予じめ絶縁材であるエポキシ樹脂を基板に被着させ
フォトリソグラフィ技術により穴を形成しその穴に低融
点半田を充填してやれば、前述の半田層パターンの形崩
れは解消できるかもしれない。しかしながら、樹脂を所
定の厚みにコーティングし穴開けを行なうという工程が
増えることになり、この工程の増加による歩留の低下や
コストが上昇することは否めない。
[0010] In the latter case of a solder ball, if an epoxy resin as an insulating material is applied to a substrate in advance and a hole is formed by photolithography, and the hole is filled with a low melting point solder, the solder described above will be used. Deformation of the layer pattern may be eliminated. However, the number of steps of coating a resin to a predetermined thickness and making holes is increased, and it is unavoidable that the increase in the number of steps decreases the yield and increases the cost.

【0011】さらに、このように組成の異なる二つの半
田部をリフローし接続する際に、不十分な洗浄により異
質な物質が残り温度上昇を伴なって接合面に気泡を発生
させ、この気泡が接続強度を低下させるという懸念があ
る。
Further, when two solder portions having different compositions are reflowed and connected as described above, foreign substances remain due to insufficient cleaning, and bubbles are generated on the joint surface with a rise in temperature. There is a concern that the connection strength is reduced.

【0012】従って、本発明の目的は、プリント配線板
の反りを吸収し信頼性の高い接続が得られるとともに安
価な半導体装置を提供することである。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an inexpensive semiconductor device capable of absorbing a warp of a printed wiring board and obtaining a highly reliable connection.

【0013】[0013]

【課題を解決するための手段】本発明の特徴は、基板表
面より突出し球形の外郭をもつとともに自重をかけなが
ら再溶融させ前記外郭の元の高さの少くなくとも75パ
ーセントに維持する表面張力をもつ錫を主材とし鉛を添
加した半田接続部材の複数を具備する半導体装置であ
る。また、前記鉛が5乃至20パーセント含むことが望
ましい。
SUMMARY OF THE INVENTION A feature of the present invention is that it has a spherical outer shell protruding from the substrate surface and is re-melted while applying its own weight to maintain the outer shell at its original height of at least 75%. A semiconductor device comprising a plurality of solder connection members containing tin as a main material and adding lead. Preferably, the lead contains 5 to 20%.

【0014】[0014]

【発明の実施の形態】次に、本発明について図面を参照
して説明する。
Next, the present invention will be described with reference to the drawings.

【0015】図1(a)および(b)は本発明の半導体
装置の一実施の形態を説明するための錫と鉛の組成比に
よる表面張力の変化を示すグラフおよび半田ボールによ
る半田バンプを示す図である。一般に、半田バンプの材
料は、鉛と錫の合金が使用されている。これら鉛と錫の
含有比によって融点が異なる他機械的性質も異なってく
る。例えば、1989年発行の「Handbook o
f PrintedCircuit Design」に
鉛と錫の含有率によって表面張力が変化することが開示
されている。すなわち、鉛(Pb)に対し錫(Sn)の
含有率が高くなると、図1(a)に示すように、表面張
力が大きくなっている。
FIGS. 1 (a) and 1 (b) are graphs showing a change in surface tension depending on the composition ratio of tin and lead, and solder bumps formed by solder balls, for explaining an embodiment of the semiconductor device of the present invention. FIG. Generally, an alloy of lead and tin is used as a material for the solder bump. Depending on the content ratio of lead and tin, the melting point differs and the mechanical properties also differ. For example, "Handbook o" published in 1989
f Printed Circuit Design discloses that the surface tension changes depending on the content of lead and tin. That is, as the content of tin (Sn) with respect to lead (Pb) increases, the surface tension increases as shown in FIG.

【0016】本発明は、半田における錫の含有率を高く
し表面張力を上げることによってリフローしたときに表
面張力で半田バンプの高さを高くできるとの推測のもと
になされたものである。試みに、半田バンプとなるべき
半田材料をSnを主としPb10%含有率と共晶半田
(Pb37%,Sn63%)による半田ボール(直径
0.67mmの球形)が取り付いた半導体装置をそれぞ
れを準備し、図1(b)に示すように、プリント配線板
2に設けられたパッドに半田ペーストを塗布しその上に
半導体装置の基板4を位置決め搭載しリフローしたとこ
ろ、Snを主とする半田ボール1の沈みが小さく10%
程度であった。これに対し共晶半田による半田ボール1
は大きく沈み高さが60%程度しか維持できなかった。
The present invention has been made on the assumption that the height of the solder bumps can be increased by the surface tension when reflowing by increasing the content of tin in the solder and increasing the surface tension. As a trial, a semiconductor device was prepared in which a solder material to be a solder bump was mainly Sn and a solder ball (spherical having a diameter of 0.67 mm) with a Pb content of 10% and a eutectic solder (Pb 37%, Sn 63%) was attached. Then, as shown in FIG. 1 (b), a solder paste is applied to the pads provided on the printed wiring board 2, the substrate 4 of the semiconductor device is positioned and mounted thereon, and reflowed. Sinking of 1 is small and 10%
It was about. On the other hand, solder ball 1 made of eutectic solder
Had a large sinking height of only about 60%.

【0017】また、共晶半田ボールのように40%と大
きく沈むことがなく、僅か10%程度の沈みで済むの
で、鼓状の半田ボールの横方向の広がりは、パッドの直
径と半田ボール1の高さと等しいと考えれば、単純に幾
何学的に試算してみても横方向に5%しか広がらず、隣
接する半田ボールが接触することはない。このことは、
半田ボールと半田ボールとの間に絶縁物を設ける必要が
なくさらに狭ピッチ化も可能になることが言える。
Further, unlike the eutectic solder ball, it does not sink as much as 40%, and only needs to sink by about 10%. Therefore, the horizontal spreading of the drum-shaped solder ball depends on the diameter of the pad and the solder ball 1. If it is considered to be equal to the height of the solder ball, even if it is simply calculated geometrically, it spreads only 5% in the lateral direction, and adjacent solder balls do not come into contact with each other. This means
It can be said that there is no need to provide an insulator between the solder balls and the pitch can be further reduced.

【0018】図2は形成された接続部の温度サイクル試
験の結果を示す表である。ちなみに、この二種類のサン
プルの複数個(15個)を温度サイクル試験(−40°
C/+125°C,1CYCLE/Hr)を行なったと
ころ、図2に示すように、共晶半田のものは500サイ
クル程度で3個のサンプルが接続部の破断を起している
のに対し90%の錫を含む半田の場合は1000サイク
ルでも破断を起すサンプルは皆無であった。また、接続
の信頼性が向上するとともに錫が主体となるため熱伝導
度や電気伝導度も向上し、半導体ペレットからの放熱を
必要としさらに電気抵抗を小さくしなければならないこ
の種の半導体装置には有利となる知見を得た。
FIG. 2 is a table showing the results of a temperature cycle test of the formed connection. Incidentally, a plurality (15) of these two types of samples were subjected to a temperature cycle test (−40 °).
C / + 125 ° C., 1 CYCLE / Hr), as shown in FIG. 2, three samples of the eutectic solder had a breakage of the connection part in about 500 cycles, whereas 90 In the case of the solder containing% tin, none of the samples broke even after 1000 cycles. In addition, since the reliability of the connection is improved and tin is mainly used, the thermal conductivity and the electrical conductivity are also improved, and heat dissipation from the semiconductor pellet is required. Obtained advantageous findings.

【0019】図3はリフロー時に異なる荷重をかけたと
き表面張力で維持できる高さと錫に含まれる鉛の含有率
との関係を示すグラフである。ここで、この種の半導体
装置におけるリフロー時における一半田バンプにかかる
荷重(P)の大小を調べ、それと平行して、錫を主原料
に種々の鉛の含有率の異なる半田ボールを準備し、重量
やパッド数の異なる基板のパッドに半田ボールのそれぞ
れを被着させ、プリント配線板にフェースダウンさせリ
フローし、半田ボールが維持できる高さ(H)を計測し
てみた。その結果、図3に示すようなグラフが得られ
た。
FIG. 3 is a graph showing the relationship between the height that can be maintained at the surface tension when different loads are applied during reflow and the lead content in tin. Here, the magnitude of the load (P) applied to one solder bump at the time of reflow in this type of semiconductor device is examined, and in parallel with this, various solder balls having different lead contents are prepared using tin as a main raw material. Each of the solder balls was adhered to pads of boards having different weights and the number of pads, face down to a printed wiring board, reflowed, and the height (H) at which the solder balls could be maintained was measured. As a result, a graph as shown in FIG. 3 was obtained.

【0020】図4(a)および(b)は本発明の半導体
装置をプリント配線板に接続する過程を説明するための
工程順に示す図である。次に、この半導体装置であるボ
ールグリッドアレイのプリント配線板への接続について
説明する。まず、半導体装置と接続するプリント配線基
板を準備する。このように準備されたプリント配線基板
の反りは、40mm平方の領域で、0.05〜0.12
mmあった。この測定は、精密定盤の上にプリント配線
板を乗せ、ダイアルゲージでプリント配線板の各点に触
針を接触させ、そのときのダイアルゲージの指針の最大
の読みを反り(δ)とした。
FIGS. 4 (a) and 4 (b) are views showing a process sequence for explaining a process of connecting the semiconductor device of the present invention to a printed wiring board. Next, connection of the ball grid array, which is the semiconductor device, to a printed wiring board will be described. First, a printed wiring board to be connected to a semiconductor device is prepared. The warpage of the printed wiring board thus prepared is 0.05 to 0.12 in a 40 mm square area.
mm. In this measurement, a printed wiring board was placed on a precision platen, and a stylus was brought into contact with each point of the printed wiring board with a dial gauge, and the maximum reading of the dial gauge pointer at that time was defined as warpage (δ). .

【0021】次に、図4(a)に示すように、予め、ヒ
ートスラグ3を取付けた基板4のパッドに半田ペースト
を塗布しその上に半田ボール1を載置したボールグリッ
ドアレイを、予めパッド5に半田ペーストが薄く塗布さ
れ反りδをもつプリント配線板2の上に位置決めする。
次に、赤外線炉でボールグリッドアレイの周囲が、例え
ば、220°C程度加熱し、半田ボールを完全に再溶融
させボールグリッドアレイを赤外線炉より引き出すこと
で冷却した。その結果、図4(b)に示すように、半田
ボールは沈み鼓状のある高さをもつ半田ボール1aに成
形され、ボールグリッドアレイは半田ボール1aを介し
てプリント配線板2に接続され、リフロー前のプリント
配線板2の反り(δ)も半分以上が吸収された。
Next, as shown in FIG. 4A, a ball grid array in which a solder paste is applied to the pads of the substrate 4 on which the heat slugs 3 are attached and the solder balls 1 are placed thereon is previously prepared. The solder paste is thinly applied to the pad 5 and positioned on the printed wiring board 2 having the warpage δ.
Next, the periphery of the ball grid array was heated by, for example, about 220 ° C. in an infrared furnace, and the solder balls were completely re-melted, and the ball grid array was pulled out of the infrared furnace and cooled. As a result, as shown in FIG. 4B, the solder ball is formed into a solder ball 1a having a sinking and drum-shaped height, and the ball grid array is connected to the printed wiring board 2 via the solder ball 1a. More than half of the warpage (δ) of the printed wiring board 2 before reflow was absorbed.

【0022】図5は種々の自重とピン数の異なるボール
グリッドアレイに対し鉛含有率の異なる半田ボールを用
いてプリント配線板と接続したときの基板の反りの吸収
および接続信頼性の結果を示す表である。ぞこで、前述
の接続方法を用いて、一半田ボール当りの荷重が異なる
ボールグリッドアレイと0.1mm程度の歪みのあるプ
リント配線板との接続を組成の異なる半田ボール(直
径、0.67mm)で行なってみた。
FIG. 5 shows the results of the absorption of the warpage of the substrate and the connection reliability when solder balls having different lead contents are connected to ball grid arrays having various weights and different numbers of pins. It is a table. Here, the connection between the ball grid array having a different load per solder ball and the printed wiring board having a distortion of about 0.1 mm was performed by using the above-described connection method with the solder balls having different compositions (diameter: 0.67 mm). ).

【0023】その結果、図5の表に示すように、自重の
軽いボールグリッドアレイ(1A〜1D)においては、
錫80,鉛20の半田ボールでも、パッケージ中央の半
田ボールが大きく沈み基板の反りを吸収し温度サイクル
において500サイクルまでは接続部の破断が認められ
なかった。
As a result, as shown in the table of FIG. 5, in the ball grid array (1A to 1D) having a light weight,
Even with the solder balls of tin 80 and lead 20, the solder ball at the center of the package sinks greatly and absorbs the warpage of the substrate, and no breakage of the connection portion was observed until 500 cycles in the temperature cycle.

【0024】また、前述のボールグリドアレイより稍重
い自重のボールグリッドアレイでは、鉛含有率が15%
以下のものが良く、最も自重のあるボールグリドアレイ
でも、鉛含有率が10%程度の半田ボールが良かった。
Further, in the ball grid array having its own weight slightly heavier than the above-mentioned ball grid array, the lead content is 15%.
The following were good, and the solder ball having a lead content of about 10% was good even for the ball grid array having the highest weight.

【0025】この表から言えることは、0.67mmの
高さをもつ半田ボールが自重をかけながらリフローした
とき、その表面張力である程度の高さ、ここでは、0.
52mmを維持できれば、所望の接続信頼度が得られる
ことである。すなわち、元の高さの0.52/0.67
×100=77%以上維持するように、錫に含まれる鉛
の含有率の半田材を選べば良いことになる。ピン当りに
対する自重の軽いボールグリッドアレイであれば、錫に
含まれる鉛の含有率は20%以下のもの、最も重いもの
では、鉛の含有率が10%程度のものを選らべば良い。
From this table, it can be said that when a solder ball having a height of 0.67 mm reflows while applying its own weight, the solder ball has a certain height due to its surface tension.
If 52 mm can be maintained, a desired connection reliability can be obtained. That is, 0.52 / 0.67 of the original height
It suffices to select a solder material having a lead content of tin so as to maintain × 100 = 77% or more. In the case of a ball grid array having a light weight per pin, a tin content of 20% or less should be selected for tin, and a lead content of about 10% should be selected for the heaviest one.

【0026】また、図3のグラフに示すように、もし、
錫95%および鉛5%のような半田ボールを使用したと
すれば、従来、後で取付けていた重いラジェータでも、
先に取付けてリフローしても半田バンプの高さを維持で
きる。このことは、プリント配線板への実装工程がより
簡単になるという利点がある。ただ、この場合は、ラジ
ェータによる熱容量が大きくなるので、リフローする際
に、温風赤外線炉でなく、ベーパーフェーズソルダリン
グ法を採ることが望ましい。
Also, as shown in the graph of FIG.
Given the use of solder balls such as 95% tin and 5% lead, heavy radiators, which were conventionally mounted later,
The height of the solder bumps can be maintained even if the solder bumps are attached first and reflowed. This has the advantage that the mounting process on the printed wiring board becomes simpler. However, in this case, since the heat capacity of the radiator increases, it is desirable to use a vapor phase soldering method instead of a hot air infrared furnace when reflowing.

【0027】[0027]

【発明の効果】以上説明したように本発明は、半導体装
置の基板表面から突出しプリント配線板のパッドと接続
する球状半田接続部材の組成を錫を主原料とし多くても
20%の鉛を添加させ前記接続部材を再溶融したときそ
の高さを高く維持し得るように表面張力を大きくし、特
別に高さを高く維持する手段を設けることなく接続部材
を高く維持することができ、接続部に加わる熱ストレス
を小さくし、繰返し熱ストレスが加わっても接続部が剪
断されることなく信頼性が向上するという効果がある。
As described above, according to the present invention, the composition of a spherical solder connecting member projecting from the substrate surface of a semiconductor device and connecting to a pad of a printed wiring board is composed mainly of tin and at most 20% of lead is added. When the connection member is re-melted, the surface tension is increased so that the height can be maintained high, and the connection member can be maintained high without providing a means for maintaining the height particularly high. This has the effect of reducing the thermal stress applied to the wire and improving the reliability without shearing the connection portion even when the thermal stress is applied repeatedly.

【0028】また、前記接続部材を高く維持することが
できるので、横方向への広がりが小さくて済み、隣接す
る接続部材の接触を防止する絶縁物が必要がなくなり、
それを設けることによる工程の増加や工程の増加による
歩留り低下もなく、コストを大幅に低減できるという効
果がある。
In addition, since the connecting members can be kept high, the spread in the lateral direction can be reduced, and there is no need for an insulator for preventing contact between adjacent connecting members.
There is an effect that the cost can be greatly reduced without increasing the number of steps due to the provision thereof and the yield reduction due to the increase in the number of steps.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体装置の一実施の形態を説明する
ための錫と鉛の組成比による表面張力の変化を示すグラ
フおよび半田ボールによる半田バンプを示す図である。
FIG. 1 is a graph illustrating a change in surface tension depending on a composition ratio of tin and lead and a diagram illustrating solder bumps formed by solder balls for describing an embodiment of a semiconductor device of the present invention.

【図2】形成された接続部の温度サイクル試験の結果を
示す表である。
FIG. 2 is a table showing a result of a temperature cycle test of a formed connection portion.

【図3】リフロー時に異なる荷重をかけたとき表面張力
で維持できる高さと錫に含まれる鉛の含有率との関係を
示すグラフである。
FIG. 3 is a graph showing the relationship between the height that can be maintained at the surface tension when different loads are applied during reflow and the lead content in tin.

【図4】本発明の半導体装置をプリント配線板に接続す
る過程を説明するための工程順に示す図である。
FIG. 4 is a diagram illustrating a process sequence for explaining a process of connecting a semiconductor device of the present invention to a printed wiring board.

【図5】種々の自重とピン数の異なるボールグリッドア
レイに対し鉛含有率の異なる半田ボールを用いてプリン
ト配線板と接続したときの歪みの吸収および接続信頼性
の結果を示す表である。
FIG. 5 is a table showing the results of strain absorption and connection reliability when solder balls having different lead contents are connected to a printed wiring board for various ball grid arrays having different weights and different numbers of pins.

【符号の説明】[Explanation of symbols]

1,1a 半田ボール 2 プリント配線板 3 ヒートスラグ 4 基板 5 パッド 1, 1a solder ball 2 printed wiring board 3 heat slug 4 board 5 pad

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 基板表面より突出し球形の外郭をもつと
ともに自重をかけながら再溶融させ前記外郭の元の高さ
の少くなくとも75パーセントに維持する表面張力をも
つ錫を主材とし鉛を添加した半田接続部材の複数を具備
することを特徴とする半導体装置。
1. A main material comprising tin, which has a spherical outer shape projecting from the substrate surface and has a surface tension maintaining at least 75% of the original height of the outer shape by remelting while applying its own weight. A semiconductor device comprising a plurality of solder connection members.
【請求項2】 前記鉛が5乃至20パーセント含むこと
を特徴とする請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the lead content is 5 to 20%.
JP8031035A 1996-02-19 1996-02-19 Semiconductor device Expired - Lifetime JP2762982B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8031035A JP2762982B2 (en) 1996-02-19 1996-02-19 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8031035A JP2762982B2 (en) 1996-02-19 1996-02-19 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH09232375A true JPH09232375A (en) 1997-09-05
JP2762982B2 JP2762982B2 (en) 1998-06-11

Family

ID=12320253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8031035A Expired - Lifetime JP2762982B2 (en) 1996-02-19 1996-02-19 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2762982B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268067B2 (en) 2002-04-15 2007-09-11 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
JP2008227439A (en) * 2007-03-15 2008-09-25 Hynix Semiconductor Inc Ball attachment device and solder ball attachment method using the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268067B2 (en) 2002-04-15 2007-09-11 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
US7276802B2 (en) * 2002-04-15 2007-10-02 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
US7342319B2 (en) 2002-04-15 2008-03-11 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
US7468559B2 (en) 2002-04-15 2008-12-23 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
US7851907B2 (en) 2002-04-15 2010-12-14 Micron Technology, Inc. Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
JP2008227439A (en) * 2007-03-15 2008-09-25 Hynix Semiconductor Inc Ball attachment device and solder ball attachment method using the same

Also Published As

Publication number Publication date
JP2762982B2 (en) 1998-06-11

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