JPH09231774A - Ferroelectric memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a ferroelectric memory device that can ensure a read margin best including when characteristics are varied due to the temperature change during the operation or being left at a high temperatures. SOLUTION: A bit line capacity Cb is set at a point where the difference of polarization amounts at intersections of the bit line capacity Cb and a hysteresis curve of a ferroelectric capacitor at a lowest temperature in a temperature range ensuring the operation of a device and a hysteresis curve at a highest temperature in the range is equal to or larger than the reduced amount of a remaining polarization. Accordingly, a potential difference ΔVb1 of bit lines can be set not to change or increase even by a rise of operation temperature in the temperature range. In other words, a read margin is not deteriorated even when the remaining polarization Pr is worsened due to the operation temperature rise.

Description

Detailed Description of the Invention

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a ferroelectric memory device utilizing polarization inversion of a ferroelectric.

[0002]

2. Description of the Related Art Various types of ferroelectric non-volatile memory utilizing the polarization inversion of a ferroelectric substance having a hysteresis characteristic as shown in FIG. 8 have been proposed at present. One that constitutes one bit by two switching transistors and two ferroelectric capacitors (referred to as 2Tr-2Cap method),
One bit is constituted by one switching transistor and one ferroelectric capacitor (1Tr-1Ca)
p type) have been proposed.

FIG. 9 is a diagram showing a basic 1-bit configuration of a ferroelectric nonvolatile memory adopting the 2Tr-2Cap system. As shown in FIG. 9, this memory cell includes one of switching transistors Tr1 and Tr2, which are n-channel MOS transistors whose drains are respectively connected to bit lines BL1 and BL2, and one of the sources of the switching transistors Tr1 and Tr2. One bit is formed by two sets of combinations with the ferroelectric capacitors FC1 and FC2 to which the electrodes of 1) are connected. The gates of the switching transistors Tr1 and Tr2 are connected to a common word line WL, and the ferroelectric capacitor FC
The other (second) electrode (plate electrode) of 1 and FC2 is connected to a common plate line PL. The bit lines BL1 and BL2 are connected to a write and read system circuit (not shown), and the word line WL and the plate line PL are connected.
Is connected to a row decoder (not shown).

2Tr-2Cap having such a structure
In the method, the ferroelectric films of the ferroelectric capacitors connected to the two pairs of bit lines in the write operation are polarized in opposite directions, and the polarization state is read in the read operation. Data writing and reading operations in the ferroelectric non-volatile memory adopting the 2Tr-2Cap method will be described below with reference to FIGS. 10 to 13.

First, referring to FIGS. 10 and 11,
The write operation will be described. FIG. 10 is a timing chart of the potential applied to each terminal at the time of writing, and FIG. 11 shows the polarization state of the ferroelectric capacitor at that time. At the time of writing, first, as shown by T1 in the figure, the ground GND level “0” V is applied to the bit line BL1.
Then, the power supply voltage V _CC is applied to the bit line BL2 and (V _CC + 1V) is applied to the word line WL. The word line WL
Is set to (V _CC + 1V) because the threshold voltage Vth of the switching transistor is Vth <1V, and therefore “+ 1V” is set to prevent potential drop due to the transistor. As a result, the switching transistors Tr1 and Tr2 are rendered conductive, and a ground GND level, that is, a voltage of "0" V is applied to the bit line side electrode (one electrode) of the ferroelectric capacitor FC1 and the ferroelectric capacitor FC2 The voltage V _CC is applied to the bit line side electrode. At this time, the plate line PL is held at "0" V (ground level). As a result, only the ferroelectric capacitor FC2 has a polarization state from the bit line side electrode toward the plate electrode.

Thereafter, as shown at T2 in the figure, a power supply voltage V _CC is applied to the plate line PL, and subsequently, as shown at T3 in the figure, "0" V is applied to the plate line PL. That is, while the word line WL is held at the power supply voltage V _CC level with respect to the plate line PL, GND (0 V)
→ Apply a pulse of V _CC → GND (0V). As a result, while the polarization state of the ferroelectric capacitor FC2 is maintained in a direction from the bit line-side electrode toward the plate line-side electrode, polarization occurs in the ferroelectric capacitor FC1, and the polarization state from the plate electrode toward the bit line-side electrode. A polarization state is reached. That is, the ferroelectric capacitors FC1,
FC2 is polarized in the opposite direction, the state moves to point D and point B in the hysteresis curve shown in FIG. 8, and the writing is completed.

Next, the read operation will be described with reference to FIGS.
This will be described with reference to FIG. First, FIG. 12 and FIG.
As shown by T1 in the figure, bit lines BL1 and BL2
"0" V is applied and then opened. At this time
In addition, (V _CC+1 V) is applied. Next
Then, as shown by T2 in the figure, the potential of the plate line PL is
"0" V to power supply voltage V_CCStart up. This
Output to the bit line BL depending on the polarization state of the ferroelectric substance.
The applied potential is different.

That is, the polarization state of the ferroelectric capacitor FC2 moves from point B to point C in the hysteresis curve shown in FIG. On the other hand, the polarization state of the ferroelectric capacitor FC1 moves from the point D to the point C and does not reverse the polarization. Accordingly, the amount of charge movement accompanying the change in polarization is larger in the ferroelectric capacitor FC2 whose polarization is inverted than in the ferroelectric capacitor FC1 whose polarization is not inverted, and the potential of the bit line BL2 is higher than that of the bit line BL1. The difference between the bit line potentials is referred to as bit line B.
Reading is performed by driving a differential type sense amplifier (not shown) to which L1 and BL2 are connected and latching it to V _CC and 0 V _{depending on} the magnitude of the potential. Finally, as shown by T3 in the figure, "0" is again applied to the plate line PL again.
By applying V, the ferroelectric capacitor FC2 whose polarization has been inverted is returned to the original polarization state. Thus, a series of read operations is completed.

FIG. 14 is a diagram showing a basic 1-bit configuration of a nonvolatile memory adopting the 1Tr-1Cap system. As shown in FIG. 14, the memory cell MC includes a switching transistor Tr1 including an n-channel MOS transistor having a drain connected to the bit line BL1 and a ferroelectric having one electrode connected to the source of the switching transistor Tr1. Body capacitor F
1 bit is configured by C1, the gate of the switching transistor Tr1 is connected to the word line WL, and the other electrode (plate electrode) of the ferroelectric capacitor FC1 is connected to the plate line PL. Then, in the nonvolatile memory adopting the 1Tr-1Cap system, the reference switching transistor RTr having the drain connected to the reference bit line BL2.
1 and a reference ferroelectric capacitor RFC1 having one electrode connected to the source of the switching transistor RTr1.
MC is provided, the gate of the switching transistor RTr1 is connected to the reference word line RWL, and the other electrode of the ferroelectric capacitor RFC1 is connected to the reference plate line RPL.

Next, the data writing and reading operations in the non-volatile memory adopting the 1Tr-1Cap system will be described with reference to FIGS. FIG.
5 and 16 show a timing chart and a polarization state at the time of writing, respectively, and FIGS. 17 and 18 show a timing chart and a polarization state at the time of reading, respectively.

In the case of the 1Tr-1Cap method, basically, writing and reading are performed by the same method as the 2Tr-2Cap method described above. The difference in this case is that a potential difference is detected between each bit line connected to a normal memory cell and a bit line connected to a reference cell. In this case, for example, by adjusting the capacitor area of the reference cell or the like, the bit line potential at the time of reading is set to the middle of the potential at the time of reading each polarization.

In data writing, the voltage control of each line as shown in FIGS. 15 and 16 is performed, and the polarization state of one ferroelectric capacitor is changed to the point D of state 0 (State 0) in the hysteresis curve of FIG. Or state 1 (St
1-bit writing is performed by setting point B of ate1).

In reading, as shown in FIGS. 17 and 18, in addition to the normal word line WL and plate line PL,
Word line RWL for reference cell, plate line RP
Driving L, the potential of the bit line BL2 connected to the reference cell RMC and the bit line B connected to the memory cell
The difference from the potential according to the polarization state of L1 is detected. Therefore, since the reference cell RMC is used without polarization inversion, the reference word line RWL is set to the reference plate line R so as not to enter the rewriting operation.
It is set to fall at a timing earlier than PL.

[0014]

As is clear from the above description, in the data reading of the memory of this system, the polarization side and the non-polarization side (in the case of 2Tr-2Cap), the read cell and the reference cell (1Tr-1Cap). In the case of 1), it is necessary to take a large difference in the potential change of the bit line connected to. This is because if the difference is small, the characteristic variation of the ferroelectric capacitor cannot be compensated and some bits cannot be read.

Further, in the case of a non-volatile memory, it is generally from 0 ° C to
Data retention at operating temperature of 70 ℃ and high temperature (70 ℃ ～ 12
(5 ° C., 10 years) must be guaranteed, but since the shape of the hysteresis curve changes due to these changes in operating temperature and high temperature standing treatment, the bit line potential also changes.
Therefore, the bit line potential change difference must be guaranteed including these reliability aspects. However, up until now, the memory configuration has not been such that the read margin including the operating temperature and the characteristic variation due to being left at high temperature has been taken into consideration. The design was made by, and it could not be said that the optimized configuration was realized in the ferroelectric memory.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a ferroelectric memory device in which the read margin can be maximized including the temperature change during operation and the characteristic change due to high temperature storage. It is in.

[0017]

In order to achieve the above object, the present invention provides a combination 2 of one switching transistor connected to a bit line and one ferroelectric capacitor connected in series to the switching transistor.
One bit is formed by a set, each ferroelectric capacitor is polarized in different directions, and binary data is stored depending on the polarization direction. In the data read operation, the capacitance ratio of the ferroelectric capacitor and the bit line is 2 decided
A ferroelectric memory device for detecting a polarization state corresponding to binary data based on a difference between bit line potentials of a book, wherein a polarization of a ferroelectric capacitor in different applied voltage-polarization amount characteristics obtained under different evaluation situations is described. The bit line capacitance is set so that the difference in remanent polarization when a non-voltage is applied and the difference in polarization amount when a voltage is applied during a polarization inversion data read operation may match or substantially match the difference in the amount. There is.

Further, the present invention provides a combination of one switching transistor and one ferroelectric capacitor connected to the switching transistor.
Bits are configured to store binary data depending on the polarization direction of the ferroelectric capacitor, and in the data read operation, the bit line potential determined by the capacitance ratio between the ferroelectric capacitor and the bit line and the reference potential provided elsewhere are stored. 2 due to the difference
A ferroelectric memory device for detecting a polarization state corresponding to value data, wherein when a non-voltage is applied in a difference in polarization amount between different applied voltage-polarization amount characteristics obtained by different evaluation situations of a ferroelectric capacitor. Difference in remnant polarization of
The bit line capacitance is set so that the difference in the amount of polarization due to voltage application during the operation of reading the polarization inversion data may match or substantially match.

In each of the above ferroelectric memory devices,
The bit line capacitance is the difference between the remanent polarization when a non-voltage is applied and the difference between the polarization amounts at the voltage application point during the polarization inversion data read operation in the difference in polarization amount between the ferroelectric capacitors at different memory operating temperatures. Are set to match or substantially match.

Further, the bit line capacitance is set so that the difference in remanent polarization when a non-voltage is applied is smaller than the difference in polarization amount at a voltage application point during a polarization inversion data read operation.

In each of the above ferroelectric memory devices,
The bit line capacitance is the difference between the remanent polarization when a non-voltage is applied and the voltage when the polarization inversion data is read in the difference in the polarization amount of the ferroelectric capacitor between the normal operation of the memory and the operation after being left for a certain period. It is set so that the difference in the amount of polarization at the applied point is the same or substantially the same.

The bit line capacitance is set so that the difference in remanent polarization when a non-voltage is applied is smaller than the difference in polarization amount at the voltage application point during a polarization inversion data read operation.

According to the ferroelectric memory device of the present invention, 2T
In the r-2Cap method and the 1Tr-1Cap method, the bit line capacitance is different in the difference in polarization amount between different applied voltage-polarization amount characteristics obtained by different evaluation conditions of the ferroelectric capacitor, specifically, different memory operation. The difference between the residual polarization when a non-voltage is applied and the polarization quantity when a voltage is applied during the polarization inversion data read operation is calculated between the difference in the polarization amount at temperature or the difference in the polarization amount between the normal operation of the memory and the operation after leaving for a certain period of time. Since the difference and the difference are set so that they coincide with each other or substantially coincide with each other, even when the residual polarization is deteriorated after being left at a high temperature or when the operating temperature rises,
Read margin does not deteriorate.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a ferroelectric non-volatile memory according to the present invention will be described below. In the ferroelectric non-volatile memory according to the present embodiment, as a circuit, for example, the ferroelectric non-volatile memory adopting the 2Tr-2Cap method shown in FIG. 9 or the ferroelectric non-volatile memory adopting the 1Tr-1Cap method shown in FIG. It is equivalent to a non-volatile memory. The ferroelectric non-volatile memory according to the present embodiment is different from the conventional ferroelectric non-volatile memory in that the difference in polarization charge after the high temperature storage or at the low temperature / high temperature read operation is different from the difference in the residual polarization. The bit line capacitance is set to be large. Hereinafter, the principle of setting the bit line capacitance will be described step by step with reference to the drawings.

A method for estimating the difference in bit line potential change at the time of reading will be described below with reference to FIGS. 1 and 2.

FIG. 1 is an equivalent circuit diagram of a switching transistor and a ferroelectric capacitor connected to each bit line. When the switching transistor is on, the ferroelectric capacitor FC is connected in series with the parasitic capacitance (bit line capacitance) Cb of the bit line between the plate line PL and the ground GND. In the read operation, Vpl is applied to the plate line.
The fact that the bit line potential Vbl differs depending on the polarization state of the ferroelectric capacitor FC when the potential is applied is used. This bit line potential Vbl is the ferroelectric capacitor F
Although it is determined by potential division by C and the bit line capacitance Cb, since the capacitance Cs of the ferroelectric capacitor FC is a non-linear capacitance for which a concrete formula of the function is not clear, it is not possible to analytically solve the bit line potential Vbl. It is impossible. Therefore,
In order to obtain the bit line potential Vbl, the following drawing method is used.

The electric charge Q accumulated in the ferroelectric capacitor FC when a potential difference V is applied across the electrodes of the ferroelectric capacitor FC is represented by a function Q (V).
Here, the functional form of Q (V) corresponds to the curve D-C at the time of non-polarization inversion and the curve B-C at the time of polarization inversion in FIG. on the other hand,
When the bit line capacitance Cb is a linear capacitor, the relationship between the accumulated charge and the potential difference V across the electrodes is represented by Q = Cb · V. When the voltage Vpl is applied to the plate line PL, since the bit line is open, the charges accumulated in the ferroelectric capacitors FC and Cb are equal, and if the charges are Qo, the following simultaneous equations hold.

[0028]

## EQU1 ## Qo = Q (Vpl-Vbl) (1)

[Equation 2] Qo = Cb · Vbl (2)

As shown in FIG. 2, Vbl that satisfies this simultaneous equation is a straight line having a slope Cb drawn on the hysteresis and respective curves B-C and D-C on the polarization inversion and non-polarization inversion sides.
It can be obtained by the intersection with and.

When the bit line potentials Vbl1 and Vbl0 on the polarization inversion and non-polarization inversion sides are obtained as described above, for example, the bit line potential difference ΔV in the 2Tr-2Cap system.
bl (Vbl1-Vbl0) can be represented by the portion shown in FIG. Further, the bit line potential difference ΔVbl in the case of 1Tr-2Cap is half this. It is desirable for the memory cell to have a larger bit line potential difference ΔVbl in order to make the read margin as large as possible, but as can be seen from FIG. 2, the bit line potential difference ΔVbl varies with the size of the bit line capacitance Cb and the hysteresis curve. It can be seen that

With the above calculation example of the bit line potential difference ΔVbl
Then, the ferroelectric thin film SrBi_TwoTa _TwoO₉, 130n
m, 3 μm^TwoHysteresis Obtained by the Capacitor of
Curve is shown in FIG. In FIG. 3, Cb = 600 fF, power supply
The voltage Vcc is set to 2.0V. In this case, ΔV
As bl, 0.8 V is obtained.

Next, using the above-described estimation method of the bit line potential difference ΔVbl, ΔVb when the device operating temperature changes
The behavior of the change in l and the memory design method in which the read margin does not decrease even if the device operating temperature changes will be described with reference to FIG. 4 (the same sample as FIG. 3).

The temperature change of the remanent polarization Pr (intersection point of the hysteresis curve and the charge axis) and the coercive voltage Vc (intersection point of the hysteresis curve and the voltage axis), which is an index showing the shape of the hysteresis curve, is theoretically expressed by the following equation. expressed.

[0034]

[Formula 3] Pr∝ (Tc-T) ^1/2 Vc∝ (Tc-T) ^3/2 (Tc: Curie temperature) (3)

It can be seen from this that both the remanent polarization and the coercive voltage decrease as the temperature rises.

FIG. 4 shows hysteresis curves at 0 ° C. and 70 ° C., which correspond to a general device operation guarantee temperature range. In FIG. 4, the value of the bit line capacitance Cb is 300
It is set for three types of fF, 560fF, and 900fF.

FIG. 5 is a graph showing the change in the bit line potential difference ΔVbl before and after high temperature standing based on this. FIG.
According to the data, when the bit line capacitance Cb is 900 fF, the bit line potential difference ΔVbl decreases due to the increase in operating temperature.
There is no change at 0 fF, and on the contrary, it increases at 300 fF. As shown in FIG. 4, there is no change at Cb = 560 fF because the amount of decrease in remanent polarization (the amount of polarization charge when the applied voltage is 0 V) and the amount of change in polarization charge at the intersection of the bit line capacitance Cb and hysteresis are as shown in FIG. Because they are equal. With this value as the boundary, when Cb> 560 fF, it becomes>, so Δ
Vbl decreases, and when Cb <560fF, <becomes <, so ΔVbl increases. As a result, if the bit line capacitance Cb is set at a place where ≧, ΔVbl can be set to be unchanged or large even if the operating temperature changes.

From the above consideration, the following can be said as the design method of the ferroelectric memory. In the hysteresis curve of the ferroelectric capacitor at the lowest temperature of the device operation guaranteed temperature range and the hysteresis curve at the highest temperature,
By setting the bit line capacitance Cb at a point where the difference in the amount of polarization at the intersection with the bit line capacitance Cb is equal to or larger than the amount of decrease in remanent polarization, in the operation guaranteed temperature range, The bit line potential difference ΔVbl can be set to be unchanged or to increase even when the operating temperature rises. That is, it is possible to prevent the read margin from deteriorating even when the remanent polarization Pr deteriorates due to the increase in operating temperature.

In DRAM design, the bit line capacitance is generally set to about 10 times the capacitance value of the memory capacitor. However, according to the above setting method, since the bit line capacitance Cb where = is almost equal to the capacitance value of the ferroelectric capacitor, the DRA is changed as before.
It can be seen that the value is completely different from that in the case of following the design of M.

By the same consideration, the behavior of the change in the bit line potential difference ΔVbl due to the high temperature standing process and the memory design method will be described. In the ferroelectric capacitor in which the data is written, the amount of polarization decreases as it is left at high temperature, so the hysteresis curve changes as shown in FIG.
Here, since the film quality itself of the ferroelectric does not change, it coincides with the original curve in the saturation region of the hysteresis curve. Therefore, in the reading of "1" data and "0" data, a shift occurs at the intersection position of the bit line capacitance Cb and the hysteresis, and the bit line potential fluctuates.

In the difference between the hysteresis curves before and after the high temperature treatment, the fluctuation of the bit line potential difference ΔVbl with respect to the three kinds of bit line capacitances is 320 fF which is ≦ unlike the above case when the device operating temperature changes. As a boundary, as shown in FIG. 7, the bit line potential difference ΔVbl does not increase after being left at a high temperature. This is "1"
This is because the slope of the hysteresis curve on the "0" data read side also changes at the same time as on the data side. However, even in this case, since the bit line potential difference Vbl on the "1" data read side changes from the minus side shift to the plus side shift when left at high temperature, the decrease amount of ΔVbl due to high temperature exposure is suppressed to a small level. be able to. Therefore, as in the case of high temperature storage, by setting the bit line potential to be ≧, it is possible to design a device that suppresses deterioration of the read margin in the high temperature storage processing.

The method of setting the bit line capacitance which allows a large read margin after the device is left at a high temperature when the device operating temperature is changed has been described above. However, the similar method is not limited to these cases and the device reliability is improved. It can also be generally applied to the case where the hysteresis curve changes due to changes in the environment that must be taken into consideration. That is, the above method may be applied to the two hysteresis curves that fluctuate the maximum in the environment where reliability is to be guaranteed.

The consideration of ΔVbl when left at a high temperature and when the device temperature changes has been described for the 2Tr-2Cap type, but the same discussion can be applied to the 1Tr-1Cap type device. Further, the operation method of the memory shown in the conventional example is only one example to which the present invention can be applied, and the capacitance of the ferroelectric capacitor and the bit line such as the method of setting the precharge voltage of the bit line to V _CC. The present invention can be applied to any memory of the type that detects the bit line potential determined by the ratio. Further, in the above description, the read operating point is set by adjusting the bit line capacitance, but if the relationship of the set values is satisfied, means for adjusting other parameters such as the capacitor area and the ferroelectric film thickness. May be used.

[0044]

As described above, according to the ferroelectric memory device of the present invention, it is possible to realize the ferroelectric memory device in which the read margin does not deteriorate even when the device is operated at high temperature. Further, it is possible to realize a ferroelectric memory device capable of holding data for a long time without deteriorating the read margin even when left at high temperature.

[Brief description of drawings]

FIG. 1 is a diagram showing an equivalent circuit seen from a plate line of a ferroelectric nonvolatile memory cell.

FIG. 2 is a diagram for explaining how to obtain a bit line potential by drawing.

FIG. 3 is a diagram showing a hysteresis curve obtained by a capacitor of a dielectric thin film SrBi ₂ Ta ₂ O ₉ , 130 nm, 3 μm ² as a calculation example of a bit line potential difference ΔVbl.

FIG. 4 is a diagram showing hysteresis curves at 0 ° C. and 70 ° C. corresponding to a general device operation guarantee temperature range.

FIG. 5 is a bit line potential difference ΔV before and after being left at a high temperature based on FIG.
It is the figure which made the change of bl into a graph.

FIG. 6 is a diagram for explaining the behavior of changes in the bit line potential difference ΔVbl due to the high temperature storage process and a memory design method.

FIG. 7 is a graph showing changes in the bit line potential difference ΔVbl due to the high temperature storage process.

FIG. 8 is a diagram showing a hysteresis characteristic of a ferroelectric capacitor.

FIG. 9 is a diagram showing a basic 1-bit configuration of a ferroelectric non-volatile memory adopting a 2Tr-2Cap system.

FIG. 10 is a timing chart of potentials applied to each terminal during writing in the ferroelectric nonvolatile memory adopting the 2Tr-2Cap method.

11 is a diagram showing a polarization state of the ferroelectric capacitor at the time of writing corresponding to FIG.

FIG. 12 is a timing chart of a potential applied to each terminal when reading a ferroelectric non-volatile memory adopting a 2Tr-2Cap method.

13 is a diagram showing a polarization state of the ferroelectric capacitor at the time of reading corresponding to FIG.

FIG. 14 is a diagram showing a basic 1-bit configuration of a nonvolatile memory adopting a 1Tr-1Cap system.

FIG. 15 is a timing chart of potentials applied to each terminal during writing in the ferroelectric nonvolatile memory adopting the 1Tr-1Cap method.

16 is a diagram showing a polarization state of the ferroelectric capacitor at the time of writing corresponding to FIG.

FIG. 17 is a timing chart of a potential applied to each terminal when reading a ferroelectric non-volatile memory adopting the 1Tr-1Cap method.

18 is a diagram showing a polarization state of the ferroelectric capacitor at the time of reading corresponding to FIG.

[Explanation of symbols]

Tr1, Tr2 ... Switching transistor, RTr
1, RTr2 ... Switching transistor for reference, FC1, FC2 ... Ferroelectric capacitor, RFC1,
RFC2 ... Reference ferroelectric capacitor, BL
1, BL2 ... Bit line, WL, WL1, WL2 ... Word line, RWL ... Reference word line, PL ... Plate line, RPL ... Reference plate line, MC ... Memory cell, RMC ... Reference memory cell.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H01L 21/8247 29/788 29/792

Claims (10)

[Claims] 1. A combination 2 of one switching transistor connected to a bit line and one ferroelectric capacitor connected in series to the switching transistor.
One bit is formed by a set, each ferroelectric capacitor is polarized in different directions, and binary data is stored depending on the polarization direction. In the data read operation, the capacitance ratio of the ferroelectric capacitor and the bit line is 2 decided
A ferroelectric memory device for detecting a polarization state corresponding to binary data by a difference between bit line potentials of a book, the polarization of a ferroelectric capacitor at different applied voltage-polarization amount characteristics obtained under different evaluation conditions. The bit line capacitance is set so that the difference in remanent polarization when a non-voltage is applied and the difference in polarization amount when a voltage is applied during a polarization inversion data read operation are matched or substantially matched. Ferroelectric memory device. 2. The bit line capacitance is the difference between the remanent polarization when a non-voltage is applied and the voltage application point when a polarization inversion data is read in the difference in the polarization amount of the ferroelectric capacitor at different memory operating temperatures. 2. The ferroelectric memory device according to claim 1, wherein the difference in polarization amount is set to match or substantially match. 3. The bit line capacitance is set so that a difference in remanent polarization when a non-voltage is applied is smaller than a difference in polarization amount at a voltage application point during a polarization inversion data read operation. The ferroelectric memory device described. 4. The bit line capacitance is the difference between the residual polarization when a voltage is not applied and the polarization inversion data in the difference in the polarization amount between the normal operation of the memory and the operation of the ferroelectric capacitor after being left for a certain period of time. 2. The ferroelectric memory device according to claim 1, wherein the difference in the polarization amount at the voltage application point during the read operation is set to match or substantially match. 5. The bit line capacitance is set such that the difference in remanent polarization when a non-voltage is applied is smaller than the difference in polarization amount at a voltage application point during a polarization inversion data read operation. The ferroelectric memory device described. 6. One bit is configured by a combination of one switching transistor and one ferroelectric capacitor connected to the switching transistor, and binary data is stored depending on a polarization direction of the ferroelectric capacitor. In a data read operation, a ferroelectric memory device that detects a polarization state corresponding to binary data by a difference between a bit line potential determined by a capacitance ratio between a ferroelectric capacitor and a bit line and a reference potential provided elsewhere. As for the difference in the amount of polarization between different applied voltage-polarization amount characteristics obtained by different evaluation conditions of the ferroelectric capacitor, the difference in remanent polarization when no voltage is applied and the polarization when voltage is applied during polarization inversion data read operation. The bit line capacitance is set so that the amount of difference and the amount of difference match. Storage device. 7. The bit line capacitance is the difference between the remanent polarization when a non-voltage is applied and the voltage application point when a polarization inversion data is read in the difference in the polarization amount of the ferroelectric capacitor at different memory operating temperatures. 7. The ferroelectric memory device according to claim 6, wherein the difference in polarization amount is set to match or substantially match. 8. The bit line capacitance is set so that a difference in remanent polarization when a non-voltage is applied is smaller than a difference in polarization amount at a voltage application point during a polarization inversion data read operation. The ferroelectric memory device described. 9. The bit line capacitance is the difference between the residual polarization when a voltage is not applied and the polarization inversion data in the difference in the polarization amount between the normal operation of the memory and the operation of the ferroelectric capacitor after being left for a certain period of time. 7. The ferroelectric memory device according to claim 6, wherein the difference in the polarization amount at the voltage application point during the read operation is set to match or substantially match. 10. The bit line capacitance is set such that the difference in remanent polarization when a non-voltage is applied is smaller than the difference in polarization amount at a voltage application point during a polarization inversion data read operation. The ferroelectric memory device described.