JPH0922985A - Method and apparatus for designing layout, semiconductor chip designing apparatus using the same and the semiconductor chip - Google Patents
Method and apparatus for designing layout, semiconductor chip designing apparatus using the same and the semiconductor chipInfo
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- JPH0922985A JPH0922985A JP7169958A JP16995895A JPH0922985A JP H0922985 A JPH0922985 A JP H0922985A JP 7169958 A JP7169958 A JP 7169958A JP 16995895 A JP16995895 A JP 16995895A JP H0922985 A JPH0922985 A JP H0922985A
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- impurity diffusion
- region
- diffusion region
- data
- semiconductor chip
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、レイアウト設計方
法及び装置並びにこれらを用いた半導体チップ設計装置
並びに半導体チップに関し、より詳細には、一の半導体
チップ内に電源を分離する必要のある回路が混在する、
いわゆる、マクロ埋め込み型半導体チップのレイアウト
設計方法及び装置並びにこれらを用いた半導体チップ設
計装置並びに半導体チップに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout designing method and apparatus, a semiconductor chip designing apparatus and a semiconductor chip using the same, and more particularly to a circuit in which a power supply needs to be separated in one semiconductor chip. Mixed,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called macro-embedded semiconductor chip layout design method and apparatus, a semiconductor chip design apparatus and semiconductor chip using the same.
【０００２】近年、ＬＳＩ（Large Scale Integration
）回路等を含む半導体チップにおいては、一の半導体
チップに搭載すべき回路の大規模化に伴い、高集積化の
傾向が著しい。このような半導体チップにおいて、複数
の同じ基本素子（ゲート素子）を規則的に敷き詰めたチ
ップを用いて、当該基本素子間の配線のみで所望の機能
を実現しようとする、いわゆるゲートアレイを搭載した
半導体チップがあるが、最近、上述の高集積化の必要か
ら、ゲートアレイの一部に当該ゲートアレイにより実現
される機能と異なる機能を備えるマクロセル（複数の基
本セルを組合わせることにより所定の機能を実現した回
路ブロック）を一または複数個埋め込む手法により、い
わゆるマクロ埋め込み型セルアレイ（ゲートアレイ）半
導体チップを形成することが行われている。In recent years, LSI (Large Scale Integration)
In a semiconductor chip including a circuit and the like, there is a remarkable tendency of high integration with the increase in the scale of the circuit to be mounted on one semiconductor chip. In such a semiconductor chip, a chip in which a plurality of the same basic elements (gate elements) are regularly spread is used to mount a so-called gate array, which is intended to realize a desired function only by wiring between the basic elements. Although there are semiconductor chips, recently, due to the need for higher integration, a macro cell having a function different from the function realized by the gate array is provided in a part of the gate array (a predetermined function by combining a plurality of basic cells. A so-called macro-embedded cell array (gate array) semiconductor chip is formed by a method of embedding one or a plurality of circuit blocks that realize the above.
【０００３】[0003]
【従来の技術】ここで、従来技術のマクロ埋め込み型セ
ルアレイ半導体チップの一例について図５及び図６を用
いて説明する。2. Description of the Related Art An example of a conventional macro-embedded cell array semiconductor chip will be described with reference to FIGS.
【０００４】図５にその外観図を示すように、従来技術
のマクロ埋め込み型セルアレイ半導体チップ１００は、
ゲートアレイにより構成されるロジック部１０２の中に
マクロセルにより構成されるマクロ部１０３が埋め込ま
れている。また、半導体チップ１００の最外周部には半
導体チップ１００と他の半導体チップまたは外部回路と
を接続するためのＩ／Ｏ（Input/Output）領域１０１が
構成されている。As shown in the external view of FIG. 5, the conventional macro-embedded cell array semiconductor chip 100 is
A macro unit 103 composed of macro cells is embedded in a logic unit 102 composed of a gate array. Further, an I / O (Input / Output) area 101 for connecting the semiconductor chip 100 to another semiconductor chip or an external circuit is formed in the outermost peripheral portion of the semiconductor chip 100.
【０００５】次に、図５に示す半導体チップ１００の細
部構成の一例について、図５における符号Ｐで示す領域
の拡大図である図６を用いて説明する。図６にその拡大
図を示すように、半導体チップ１００においては、その
ロジック部１０２には、ゲートアレイを構成する複数の
Ｐ型不純物拡散領域としてのＰウェル１０４と複数のＮ
型不純物拡散領域としてのＮウェル１０５が規則的に形
成されている。これらのＰウェル１０４及びＮウェル１
０５に対して所望の金属配線及びヴァイアホール等を形
成することにより、ロジック部１０２において所望の機
能を有する回路が構成される。また、このロジック部１
０２に対しては、金属配線とは別個の電源ＶSS及びＶDD
により必要な電源が供給されることとなる。Next, an example of a detailed configuration of the semiconductor chip 100 shown in FIG. 5 will be described with reference to FIG. 6 which is an enlarged view of a region indicated by a symbol P in FIG. As shown in the enlarged view of FIG. 6, in the semiconductor chip 100, in the logic portion 102, the P wells 104 as the plurality of P type impurity diffusion regions forming the gate array and the plurality of N wells.
N wells 105 are regularly formed as the type impurity diffusion regions. These P-well 104 and N-well 1
A circuit having a desired function is formed in the logic portion 102 by forming a desired metal wiring, via holes, and the like for 05. In addition, this logic unit 1
02, power supplies V SS and V DD separate from metal wiring
Will supply the required power.
【０００６】一方、マクロ部１０３においては、当該マ
クロ部１０３に掲載されるマクロセルの機能に対応して
ＰウェルまたはＮウェルが形成されることとなる。この
とき、マクロ部１０３におけるＰウェルまたはＮウェル
は、ロジック部１０２におけるＰウェル１０４またはＮ
ウェル１０５のように規則的に形成される必要はなく、
当該マクロ部１０３に含まれるマクロセルの機能に対応
して形成される。On the other hand, in the macro unit 103, P wells or N wells are formed corresponding to the functions of the macro cells included in the macro unit 103. At this time, the P well or N well in the macro unit 103 is the P well 104 or N well in the logic unit 102.
The well 105 does not need to be regularly formed,
It is formed corresponding to the function of the macro cell included in the macro unit 103.
【０００７】ここで、最近のマクロ埋め込み型セルアレ
イ半導体チップ１００では、上述の高集積化に伴い、デ
ィジタル回路のみが構成されるロジック部１０２に対し
て、マクロ部１０３にアナログ回路を組込む必要も生じ
て生きている。すなわち、一の半導体チップにアナログ
回路とディジタル回路を混在させて形成する必要が出て
きているのである。Here, in the recent macro-embedded cell array semiconductor chip 100, it is necessary to incorporate an analog circuit in the macro unit 103 with respect to the logic unit 102 which is constituted only by a digital circuit, due to the above-mentioned high integration. Alive That is, it has become necessary to form an analog circuit and a digital circuit in a mixed manner on one semiconductor chip.
【０００８】[0008]
【発明が解決しようとする課題】ここで、ロジック部１
０２とマクロ部１０３の電源に着目すると、ロジック部
１０２とマクロ部１０３が共にディジタル回路である場
合等においては、それぞれの電源を互いに分離する必要
はなく、従って、ロジック部１０２とマクロ部１０３の
間隔ｔ（図６参照）も、ロジック部１０２とマクロ部１
０３が短絡しない距離であればよく、通常は半導体チッ
プ１００を設計する際の設計ルールを満たすような間隔
を取れば十分である。Here, the logic unit 1
02 and the macro unit 103, when the logic unit 102 and the macro unit 103 are both digital circuits, it is not necessary to separate the respective power supplies from each other, and therefore, the logic unit 102 and the macro unit 103 are not separated from each other. The interval t (see FIG. 6) is also defined by the logic unit 102 and the macro unit 1.
It is sufficient if 03 is a distance that does not cause a short circuit, and it is usually sufficient to provide an interval satisfying the design rule when designing the semiconductor chip 100.
【０００９】しかしながら、マクロ部１０３内にアナロ
グ回路を構成する必要がある場合等においては、ロジッ
ク部１０２の電源とマクロ部１０３の電源とを確実に分
離する必要がある。この場合には、マクロ部１０３とロ
ジック部１０２との間隔を、図７に符号ｔ1 ’及び
ｔ2 ’で示すように、電源を分離する必要がない場合
（図６参照）に比してより広くする必要がある。However, when it is necessary to form an analog circuit in the macro unit 103, the power supply of the logic unit 102 and the power supply of the macro unit 103 must be reliably separated. In this case, as compared with the case where the power supply does not need to be separated (see FIG. 6), the interval between the macro unit 103 and the logic unit 102 is, as shown by reference numerals t 1 'and t 2 ' in FIG. Need to be wider.
【００１０】これは、ロジック部１０２の電源とマクロ
部１０３の電源とを分離する場合、例えば、ロジック部
１０２のＰウェル１０４とマクロ部のＰウェルとの間で
電位差が生じる場合があるが、このとき、ロジック部１
０２のＰウェル１０４とマクロ部のＰウェルとの間隔が
図６に示すような設計ルールで規定される間隔しかない
と、ロジック部１０２のＰウェル１０４とマクロ部のＰ
ウェル間で電流が流れてしまい、ロジック部１０２とマ
クロ部１０３の電源分離が完全にできなくなることによ
るものである。このことは、ロジック部１０２のＮウェ
ル１０４とマクロ部のＮウェル間でも生じ得ることであ
る。この場合、図７に示す間隔ｔ1 ’及びｔ2 ’は、ロ
ジック部１０２におけるＰウェル１０４とＮウェル１０
５の間隔の数倍以上も必要となる。This is because when the power source of the logic unit 102 and the power source of the macro unit 103 are separated, for example, a potential difference may occur between the P well 104 of the logic unit 102 and the P well of the macro unit. At this time, the logic unit 1
If the distance between the P well 104 of No. 02 and the P well of the macro portion is only the distance defined by the design rule as shown in FIG.
This is because a current flows between the wells and the power supply for the logic unit 102 and the macro unit 103 cannot be completely separated. This can occur between the N well 104 of the logic unit 102 and the N well of the macro unit. In this case, the intervals t 1 ′ and t 2 ′ shown in FIG.
Several times more than the interval of 5 is required.
【００１１】従って、電源分離のためにロジック部１０
２とマクロ部１０３との間隔を設計ルールで規定される
間隔以上に広げた場合には、所望の機能を実現するため
の半導体チップ１００の面積自体も広がることとなり、
半導体チップ１００の小型化が図れず、また、ロジック
部１０２のゲート素子の利用率も低下して設計自体の自
由度が下がり、非効率となるという問題点があった。Therefore, the logic unit 10 is used for power supply separation.
If the distance between 2 and the macro unit 103 is increased beyond the distance specified by the design rule, the area itself of the semiconductor chip 100 for realizing a desired function also increases.
There is a problem that the semiconductor chip 100 cannot be downsized, the utilization factor of the gate element of the logic unit 102 is reduced, the degree of freedom of design itself is reduced, and the efficiency is reduced.
【００１２】また、電源分離を行うための他の方法とし
て、マクロ部１０３自体の大きさをロジック部１０２と
の間隔を考慮して大きく設計する方法もあるが、この場
合でもマクロ部１０３がその機能として必要な大きさ以
上に大きくなることとなり、上記と同様の問題点が存在
することとなる。As another method for performing power supply separation, there is also a method of designing the size of the macro unit 103 itself in consideration of the space between the macro unit 103 and the logic unit 102. The size becomes larger than the size required for the function, and the same problem as described above exists.
【００１３】そこで、本発明は上記問題点に鑑みてなさ
れたもので、その目的は、一の半導体チップ内に電源分
離が必要な複数の回路を形成する場合に、当該回路間の
間隔を必要以上に広げることなく電源分離を完全に行う
ことにより、半導体チップの小型化及び設計効率の向上
が可能な半導体チップ及びこれを設計するためのレイア
ウト設計方法及び装置並びにこれらを用いた半導体チッ
プ設計装置を提供することにある。Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide an interval between the circuits when forming a plurality of circuits which require power supply separation in one semiconductor chip. A semiconductor chip that can be miniaturized and improved in design efficiency by completely separating power supplies without expanding the above, a layout designing method and apparatus for designing the same, and a semiconductor chip designing apparatus using the same To provide.
【００１４】[0014]
【課題を解決するための手段】上記の問題点を解決する
ために、請求項１に記載の発明は、一の半導体チップ上
に、第１電源に接続された第１不純物拡散領域と、前記
第１電源から分離された第２電源に接続されるととも
に、前記第１不純物拡散領域と同種の第２不純物拡散領
域とを配置するためのレイアウト設計方法において、前
記第１不純物拡散領域に対応する第１不純物拡散領域デ
ータと、前記第２不純物拡散領域に対応する第２不純物
拡散領域データとを生成する第１不純物拡散領域データ
生成工程と、前記第１不純物拡散領域と前記第２不純物
拡散領域との間の領域に、前記第１不純物拡散領域又は
前記第２不純物拡散領域とは異種の第３不純物拡散領域
を配置するための第３不純物拡散領域データを生成する
第２不純物拡散領域データ生成工程と、を備えて構成さ
れる。In order to solve the above-mentioned problems, the invention according to claim 1 provides a first impurity diffusion region connected to a first power source on one semiconductor chip, and In the layout design method for connecting the second power supply separated from the first power supply and arranging the first impurity diffusion region and the second impurity diffusion region of the same kind, the layout design method corresponds to the first impurity diffusion region. A first impurity diffusion region data generating step of generating first impurity diffusion region data and second impurity diffusion region data corresponding to the second impurity diffusion region; the first impurity diffusion region and the second impurity diffusion region; And a second impurity diffusion region for generating third impurity diffusion region data for disposing a third impurity diffusion region different from the first impurity diffusion region or the second impurity diffusion region in a region between and. Configured to include an over data generating step.
【００１５】請求項１に記載の発明の作用によれば、第
１不純物拡散領域データ生成工程において、第１不純物
拡散領域データと第２不純物拡散領域データとを生成す
る。そして、第２不純物拡散領域データ生成工程におい
て、第１不純物拡散領域と第２不純物拡散領域との間の
領域にＮ型の第３不純物拡散領域を配置するための第３
不純物拡散領域データを生成する。According to the operation of the invention described in claim 1, in the first impurity diffusion region data generating step, the first impurity diffusion region data and the second impurity diffusion region data are generated. Then, in the second impurity diffusion region data generating step, a third impurity diffusion region for arranging the N-type third impurity diffusion region is formed in a region between the first impurity diffusion region and the second impurity diffusion region.
Impurity diffusion region data is generated.
【００１６】よって、第１不純物拡散領域データ、第２
不純物拡散領域データ及び第３不純物拡散領域データを
用いて設計製作された半導体チップにおいては、第１不
純物拡散領域と第２不純物拡散領域の間の領域にＮ型の
第３不純物拡散領域が配置されるので、第１不純物拡散
領域と第２不純物拡散領域が共にＰ型であり、更に、そ
れぞれが個別に、相互に分離された電源に接続される場
合に、第１不純物拡散領域と第２不純物拡散領域間の間
隙を狭くしても、第１不純物拡散領域と第２不純物拡散
領域間に電流が流れることがない。Therefore, the first impurity diffusion region data and the second impurity diffusion region data
In a semiconductor chip designed and manufactured using the impurity diffusion region data and the third impurity diffusion region data, an N-type third impurity diffusion region is arranged in a region between the first impurity diffusion region and the second impurity diffusion region. Therefore, when the first impurity diffusion region and the second impurity diffusion region are both P-type, and each is individually connected to a power source separated from each other, the first impurity diffusion region and the second impurity diffusion region Even if the gap between the diffusion regions is narrowed, no current flows between the first impurity diffusion region and the second impurity diffusion region.
【００１７】上記の問題点を解決するために、請求項２
に記載の発明は、請求項１に記載のレイアウト設計方法
において、前記第３不純物拡散領域は、前記第２不純物
拡散領域を含むマクロセル領域の周囲に略リング状に配
置されるように構成される。In order to solve the above problems, a second aspect of the present invention is provided.
In the layout designing method according to claim 1, the invention according to claim 3 is configured such that the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region. .
【００１８】請求項２に記載の発明の作用によれば、請
求項１に記載の発明の作用に加えて、第３不純物拡散領
域は、第２不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置される。According to the operation of the invention described in claim 2, in addition to the operation of the invention described in claim 1, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the second impurity diffusion region. Arranged.
【００１９】よって、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、当該第１不純物拡散領
域と第２不純物拡散領域間に電流が流れることがないの
で、マクロセル領域の電源と他の領域の電源とを分離す
ることができる。Therefore, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, current does not flow between the first impurity diffusion region and the second impurity diffusion region, so that the macrocell region is not affected. The power source and the power source in other areas can be separated.
【００２０】上記の問題点を解決するために、請求項３
に記載の発明は、請求項１に記載のレイアウト設計方法
において、前記第３不純物拡散領域は、前記第１不純物
拡散領域を含むマクロセル領域の周囲に略リング状に配
置されるように構成される。In order to solve the above problems, a third aspect of the present invention is provided.
In the layout designing method according to claim 1, the invention according to claim 1 is configured such that the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region. .
【００２１】請求項３に記載の発明の作用によれば、請
求項１に記載の発明の作用に加えて、第３不純物拡散領
域は、第１不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置される。According to the action of the invention described in claim 3, in addition to the action of the invention described in claim 1, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the first impurity diffusion region. Arranged.
【００２２】よって、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、当該第１不純物拡散領
域と第２不純物拡散領域間に電流が流れることがないの
で、マクロセル領域の電源と他の領域の電源とを分離す
ることができる。Therefore, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, a current does not flow between the first impurity diffusion region and the second impurity diffusion region, so that the macrocell region The power source and the power source in other areas can be separated.
【００２３】上記の問題点を解決するために、請求項４
に記載の発明は、一の半導体チップ上に、第１電源に接
続されたＰ型ウェル等のＰ型の第１不純物拡散領域及び
Ｎ型ウェル等のＮ型の第２不純物拡散領域とを含むロジ
ック部等の第１領域と、前記第１電源から分離された第
２電源に接続されたＰ型ウェル等のＰ型の第３不純物拡
散領域及びＮ型ウェル等のＮ型の第４不純物拡散領域と
を含むマクロ部等の第２領域とを配置するためのレイア
ウト設計方法において、前記第１領域に対応する第１領
域データと、前記第２領域に対応する第２領域データと
を生成する領域データ生成工程と、前記第１領域と前記
第２領域との間の領域に一又は複数のＰ型ウェル等のＰ
型の第５不純物拡散領域及び一又は複数のＮ型ウェル等
のＮ型の第６不純物拡散領域を、前記第１領域と前記第
２領域のうち、一方から他方へ向かう方向に交互に複数
配置するための不純物拡散領域データを生成する不純物
拡散領域データ生成工程と、を備えて構成される。In order to solve the above problems, a fourth aspect of the present invention is provided.
The invention described in (1) includes a P-type first impurity diffusion region such as a P-type well and an N-type second impurity diffusion region such as an N-type well, which are connected to a first power source, on one semiconductor chip. A first region such as a logic portion and a P-type third impurity diffusion region such as a P-type well connected to a second power source separated from the first power source and an N-type fourth impurity diffusion region such as an N-type well. In a layout design method for arranging a second area such as a macro part including an area, first area data corresponding to the first area and second area data corresponding to the second area are generated. A region data generating step, and one or more P-type wells or the like P in the region between the first region and the second region.
Type fifth impurity diffusion regions and one or more N-type sixth impurity diffusion regions such as N-type wells are alternately arranged in a direction from one of the first region and the second region toward the other. And a step of generating impurity diffusion region data for generating the impurity diffusion region data.
【００２４】請求項４に記載の発明の作用によれば、領
域データ生成工程において、第１領域データと第２領域
データとを生成する。そして、不純物拡散領域データ生
成工程において、第１領域と第２領域との間の領域に一
又は複数のＰ型の第５不純物拡散領域及び一又は複数の
Ｎ型の第６不純物拡散領域を、第１領域と第２領域のう
ち、一方から他方へ向かう方向に交互に配置するための
不純物拡散領域データを生成する。According to the operation of the invention described in claim 4, in the area data generating step, the first area data and the second area data are generated. Then, in the impurity diffusion region data generation step, one or more P-type fifth impurity diffusion regions and one or more N-type sixth impurity diffusion regions are provided in a region between the first region and the second region. Impurity diffusion region data for alternately arranging the first region and the second region in the direction from one to the other is generated.
【００２５】よって、第１領域データ、第２領域データ
及び不純物拡散領域データに基づいて設計製作された半
導体チップにおいては、第１領域と第２領域の間の領域
に第５不純物拡散領域及び第６不純物拡散領域が第１領
域と第２領域を結ぶ方向に交互に配置されるので、第１
領域と第２領域のそれぞれが個別に、相互に分離された
電源に接続される場合に、第１領域と第２領域間の間隙
を狭くしても、第１領域と第２領域間に電流が流れるこ
とがない。Therefore, in the semiconductor chip designed and manufactured based on the first region data, the second region data and the impurity diffusion region data, the fifth impurity diffusion region and the fifth impurity diffusion region are formed in the region between the first region and the second region. Since the six impurity diffusion regions are alternately arranged in the direction connecting the first region and the second region,
When each of the region and the second region is individually connected to a power source separated from each other, even if the gap between the first region and the second region is narrowed, the current between the first region and the second region is reduced. Does not flow.
【００２６】上記の問題点を解決するために、請求項５
に記載の発明は、請求項４に記載のレイアウト設計方法
において、前記第５不純物拡散領域及び前記第６不純物
拡散領域は、互いに略並行して配置されると共に、前記
第２領域の周囲に略リング状に配置されるように構成さ
れる。In order to solve the above problems, a fifth aspect of the present invention is provided.
In the layout design method according to claim 4, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and substantially the same as the periphery of the second region. It is configured to be arranged in a ring shape.
【００２７】請求項５に記載の発明の作用によれば、請
求項４に記載の発明の作用に加えて、第５不純物拡散領
域及び第６不純物拡散領域は、互いに略並行して配置さ
れると共に、第２領域の周囲に略リング状に配置され
る。According to the action of the invention described in claim 5, in addition to the action of the invention described in claim 4, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other. Together, they are arranged in a substantially ring shape around the second region.
【００２８】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００２９】上記の問題点を解決するために、請求項６
に記載の発明は、請求項４に記載のレイアウト設計方法
において、前記第５不純物拡散領域及び前記第６不純物
拡散領域は、互いに略並行して配置されると共に、前記
第１領域の周囲に略リング状に配置されるように構成さ
れる。In order to solve the above problems, a sixth aspect of the present invention is provided.
In the layout designing method according to claim 4, the invention according to claim 4 is characterized in that the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially in parallel with each other and substantially in the periphery of the first region. It is configured to be arranged in a ring shape.
【００３０】請求項６に記載の発明の作用によれば、請
求項４に記載の発明の作用に加えて、第５不純物拡散領
域及び第６不純物拡散領域は、互いに略並行して配置さ
れると共に、第１領域の周囲に略リング状に配置され
る。According to the operation of the invention described in claim 6, in addition to the operation of the invention described in claim 4, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other. Together, they are arranged in a substantially ring shape around the first region.
【００３１】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００３２】上記の問題点を解決するために、請求項７
に記載の発明は、一の半導体チップ上に第１電源に接続
された第１不純物拡散領域と、前記第１電源から分離さ
れた第２電源に接続されるとともに、前記第１不純物拡
散領域と同種の第２不純物拡散領域とを配置するための
レイアウト設計装置において、前記第１不純物拡散領域
に対応する第１不純物拡散領域データと、前記第２不純
物拡散領域に対応する第２不純物拡散領域データとを生
成するＣＰＵ等の第１不純物拡散領域データ生成手段
と、前記第１不純物拡散領域と前記第２不純物拡散領域
との間の領域に、前記第１不純物拡散領域又は前記第２
不純物拡散領域とは異種の第３不純物拡散領域を配置す
るための第３不純物拡散領域データを生成するＣＰＵ等
の第２不純物拡散領域データ生成手段と、を備えて構成
される。In order to solve the above-mentioned problems, claim 7
According to the invention described in 1), a first impurity diffusion region connected to a first power supply on one semiconductor chip, a second power supply separated from the first power supply, and a first impurity diffusion region In a layout design device for arranging second impurity diffusion regions of the same type, first impurity diffusion region data corresponding to the first impurity diffusion region and second impurity diffusion region data corresponding to the second impurity diffusion region. And a first impurity diffusion region data generating unit such as a CPU for generating the first impurity diffusion region or the second impurity diffusion region in a region between the first impurity diffusion region and the second impurity diffusion region.
The impurity diffusion region includes a second impurity diffusion region data generation unit such as a CPU that generates third impurity diffusion region data for arranging a different third impurity diffusion region.
【００３３】請求項７に記載の発明の作用によれば、第
１不純物拡散領域データ生成手段は、第１不純物拡散領
域データと第２不純物拡散領域データとを生成する。そ
して、第２不純物拡散領域データ生成手段は、第１不純
物拡散領域と第２不純物拡散領域との間の領域に、第１
不純物拡散領域又は第２不純物拡散領域とは異種の第３
不純物拡散領域を配置するための第３不純物拡散領域デ
ータを生成する。According to the operation of the invention described in claim 7, the first impurity diffusion region data generating means generates the first impurity diffusion region data and the second impurity diffusion region data. Then, the second impurity diffusion region data generation means sets the first impurity diffusion region data in the region between the first impurity diffusion region and the second impurity diffusion region.
A third type of impurity different from the impurity diffusion region or the second impurity diffusion region
Third impurity diffusion region data for arranging the impurity diffusion regions is generated.
【００３４】よって、第１不純物拡散領域データ、第２
不純物拡散領域データ及び第３不純物拡散領域データに
基づいて設計製作された半導体チップにおいては、第１
不純物拡散領域と第２不純物拡散領域の間の領域にＮ型
の第３不純物拡散領域が配置されるので、第１不純物拡
散領域と第２不純物拡散領域が共にＰ型であり、更に、
それぞれが個別に、相互に分離された電源に接続される
場合に、第１不純物拡散領域と第２不純物拡散領域間の
間隙を狭くしても、第１不純物拡散領域と第２不純物拡
散領域間に電流が流れることがない。Therefore, the first impurity diffusion region data and the second impurity diffusion region data
In the semiconductor chip designed and manufactured based on the impurity diffusion region data and the third impurity diffusion region data,
Since the N-type third impurity diffusion region is arranged in the region between the impurity diffusion region and the second impurity diffusion region, both the first impurity diffusion region and the second impurity diffusion region are P-type, and further,
In the case where each is individually connected to a power supply separated from each other, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, the gap between the first impurity diffusion region and the second impurity diffusion region is No current flows through.
【００３５】上記の問題点を解決するために、請求項８
に記載の発明は、請求項７に記載のレイアウト設計装置
において、前記第３不純物拡散領域は、前記第２不純物
拡散領域を含むマクロセル領域の周囲に略リング状に配
置されるように構成される。In order to solve the above-mentioned problems, claim 8
In the layout design apparatus according to claim 7, the invention according to claim 7 is configured such that the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region. .
【００３６】請求項８に記載の発明の作用によれば、請
求項７に記載の発明の作用に加えて、第３不純物拡散領
域は、第２不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置される。According to the action of the invention described in claim 8, in addition to the action of the invention described in claim 7, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the second impurity diffusion region. Arranged.
【００３７】よって、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、当該第１不純物拡散領
域と第２不純物拡散領域間に電流が流れることがないの
で、マクロセル領域の電源と他の領域の電源とを分離す
ることができる。Therefore, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, a current does not flow between the first impurity diffusion region and the second impurity diffusion region, so that the macrocell region The power source and the power source in other areas can be separated.
【００３８】上記の問題点を解決するために、請求項９
に記載の発明は、請求項７に記載のレイアウト設計装置
において、前記第３不純物拡散領域は、前記第１不純物
拡散領域を含むマクロセル領域の周囲に略リング状に配
置されるように構成される。In order to solve the above problems, a ninth aspect is provided.
In the layout design apparatus according to claim 7, the invention according to claim 7 is configured such that the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region. .
【００３９】請求項９に記載の発明の作用によれば、請
求項７に記載の発明の作用に加えて、第３不純物拡散領
域は、第１不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置される。According to the action of the invention described in claim 9, in addition to the action of the invention described in claim 7, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the first impurity diffusion region. Arranged.
【００４０】よって、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、当該第１不純物拡散領
域と第２不純物拡散領域間に電流が流れることがないの
で、マクロセル領域の電源と他の領域の電源とを分離す
ることができる。Therefore, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, a current does not flow between the first impurity diffusion region and the second impurity diffusion region. The power source and the power source in other areas can be separated.
【００４１】上記の問題点を解決するために、請求項１
０に記載の発明は、一の半導体チップ上に、第１電源に
接続されたＰ型ウェル等のＰ型の第１不純物拡散領域及
びＮ型ウェル等のＮ型の第２不純物拡散領域とを含むロ
ジック部等の第１領域と、前記第１電源から分離された
第２電源に接続されたＰ型ウェル等のＰ型の第３不純物
拡散領域及びＮ型ウェル等のＮ型の第４不純物拡散領域
とを含むマクロ部等の第２領域とを配置するためのレイ
アウト設計装置において、前記第１領域に対応する第１
領域データと、前記第２領域に対応する第２領域データ
とを生成するＣＰＵ等の領域データ生成手段と、前記第
１領域と前記第２領域との間の領域に一又は複数のＰ型
ウェル等のＰ型の第５不純物拡散領域及び一又は複数の
Ｎ型ウェル等のＮ型の第６不純物拡散領域を、前記第１
領域と前記第２領域にうち、一方から他方に向かう方向
に交互に複数配置するための不純物拡散領域データを生
成するＣＰＵ等の不純物拡散領域データ生成手段と、を
備えて構成される。In order to solve the above-mentioned problems, the method according to claim 1
In the invention described in 0, a P-type first impurity diffusion region such as a P-type well and an N-type second impurity diffusion region such as an N-type well connected to a first power source are provided on one semiconductor chip. A first region such as a logic part including a P-type third impurity diffusion region such as a P-type well connected to a second power source separated from the first power source; and an N-type fourth impurity such as an N-type well. In a layout design device for arranging a second area such as a macro part including a diffusion area, a first area corresponding to the first area is provided.
Area data generating means such as a CPU for generating area data and second area data corresponding to the second area, and one or a plurality of P-type wells in the area between the first area and the second area. A P-type fifth impurity diffusion region and one or more N-type sixth impurity diffusion regions such as N-type wells.
Of the region and the second region, impurity diffusion region data generating means such as a CPU that generates impurity diffusion region data for alternately arranging a plurality of regions in the direction from one to the other is configured.
【００４２】請求項１０に記載の発明の作用によれば、
領域データ生成手段は、第１領域データと第２領域デー
タとを生成する。そして、不純物拡散領域データ生成手
段は、第１領域と第２領域との間の領域に一又は複数の
Ｐ型の第５不純物拡散領域及び一又は複数のＮ型の第６
不純物拡散領域を、第１領域と第２領域のうち、一方か
ら他方へ向かう方向に交互に配置するための不純物拡散
領域データを生成する。According to the operation of the tenth aspect of the present invention,
The area data generation means generates the first area data and the second area data. Then, the impurity diffusion region data generation means includes one or more P-type fifth impurity diffusion regions and one or more N-type sixth regions in the region between the first region and the second region.
Impurity diffusion region data for alternately arranging the impurity diffusion regions in the direction from one of the first region and the second region to the other is generated.
【００４３】よって、第１領域データ、第２領域データ
及び不純物拡散領域データに基づいて設計製作された半
導体チップにおいては、第１領域と第２領域の間の領域
に第５不純物拡散領域及び第６不純物拡散領域が第１領
域と第２領域を結ぶ方向に交互に複数配置されるので、
第１領域と第２領域のそれぞれが個別に、相互に分離さ
れた電源に接続される場合に、第１領域と第２領域間の
間隙を狭くしても、第１領域と第２領域間に電流が流れ
ることがない。Therefore, in the semiconductor chip designed and manufactured based on the first region data, the second region data and the impurity diffusion region data, the fifth impurity diffusion region and the fifth impurity diffusion region are formed in the region between the first region and the second region. Since a plurality of 6 impurity diffusion regions are alternately arranged in the direction connecting the first region and the second region,
When each of the first region and the second region is individually connected to a power supply separated from each other, even if the gap between the first region and the second region is narrowed, the gap between the first region and the second region is reduced. No current flows through.
【００４４】上記の問題点を解決するために、請求項１
１に記載の発明は、請求項１０に記載のレイアウト設計
装置において、前記第５不純物拡散領域及び前記第６不
純物拡散領域は、互いに略並行して配置されると共に、
前記第２領域の周囲に略リング状に配置されるように構
成される。In order to solve the above-mentioned problems, the first aspect of the present invention is provided.
The invention according to claim 1 is the layout design apparatus according to claim 10, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and
It is configured to be arranged in a substantially ring shape around the second region.
【００４５】請求項１１に記載の発明の作用によれば、
請求項１０に記載の発明の作用に加えて、第５不純物拡
散領域及び第６不純物拡散領域は、互いに略並行して配
置されると共に、第２領域の周囲に略リング状に配置さ
れる。According to the operation of the invention described in claim 11,
In addition to the action of the invention described in claim 10, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and are arranged in a substantially ring shape around the second region.
【００４６】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion regions, even if the gap between the first and second regions is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００４７】上記の問題点を解決するために、請求項１
２に記載の発明は、請求項１０に記載のレイアウト設計
装置において、前記第５不純物拡散領域及び前記第６不
純物拡散領域は、互いに略並行して配置されると共に、
前記第１領域の周囲に略リング状に配置されるように構
成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a second aspect of the present invention, in the layout design apparatus according to the tenth aspect, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and
It is configured to be arranged in a substantially ring shape around the first region.
【００４８】請求項１２に記載の発明の作用によれば、
請求項１０に記載の作用に加えて、第５不純物拡散領域
及び第６不純物拡散領域は、互いに略並行して配置され
ると共に、前記第１領域の周囲に略リング状に配置され
る。According to the action of the invention described in claim 12,
In addition to the function of the tenth aspect, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and are arranged in a substantially ring shape around the first region.
【００４９】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００５０】上記の問題点を解決するために、請求項１
３に記載の発明は、請求項７乃至１２のいずれかに記載
のレイアウト装置と、前記レイアウト装置の動作に必要
な所定のデータを入力するためのキーボード等の入力手
段と、前記第１不純物拡散領域データ、前記第２不純物
拡散領域データ、前記第３不純物拡散領域データ、前記
第１領域データ、前記第２領域データ、前記不純物拡散
領域データのうち、いずれかのデータに基づく半導体チ
ップレイアウトを表示するディスプレイ等の表示手段
と、すくなくとも前記第１不純物拡散領域データ、前記
第２不純物拡散領域データ、前記第３不純物拡散領域デ
ータ、前記第１領域データ、前記第２領域データ及び前
記不純物拡散領域データを記憶するＨＤＤ（Hard Disk
Drive ）等の記憶手段と、を備えて構成される。In order to solve the above-mentioned problems, the method according to claim 1
The invention according to claim 3 is the layout apparatus according to any one of claims 7 to 12, input means such as a keyboard for inputting predetermined data necessary for the operation of the layout apparatus, and the first impurity diffusion. Display a semiconductor chip layout based on any one of region data, the second impurity diffusion region data, the third impurity diffusion region data, the first region data, the second region data, and the impurity diffusion region data Display means such as a display, and at least the first impurity diffusion region data, the second impurity diffusion region data, the third impurity diffusion region data, the first region data, the second region data, and the impurity diffusion region data. HDD (Hard Disk
Drive) and other storage means.
【００５１】請求項１３に記載の発明の作用によれば、
請求項７乃至１２のいずれかに記載の発明の作用に加え
て、入力手段によりレイアウト装置の動作に必要な所定
のデータを入力する。According to the operation of the invention described in claim 13,
In addition to the operation of the invention described in any one of claims 7 to 12, predetermined data necessary for the operation of the layout device is input by the input means.
【００５２】そして、表示手段は、第１不純物拡散領域
データ、第２不純物拡散領域データ、第３不純物拡散領
域データ、第１領域データ、第２領域データ、不純物拡
散領域データのうち、いずれかのデータに基づく半導体
チップレイアウトを表示する。Then, the display means is any one of the first impurity diffusion region data, the second impurity diffusion region data, the third impurity diffusion region data, the first region data, the second region data, and the impurity diffusion region data. Display the semiconductor chip layout based on the data.
【００５３】一方、記憶手段は、少なくとも第１不純物
拡散領域データ、第２不純物拡散領域データ、第３不純
物拡散領域データ、第１領域データ、第２領域データ及
び不純物拡散領域データを記憶する。On the other hand, the storage means stores at least the first impurity diffusion region data, the second impurity diffusion region data, the third impurity diffusion region data, the first region data, the second region data and the impurity diffusion region data.
【００５４】よって、一の半導体チップ内に同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域が隣接して存在
し、且つ、それぞれの不純物拡散領域を互いに分離され
た電源に接続する必要がある場合に、当該不純物拡散領
域間の間隙を狭くしても、当該不純物拡散領域間に電流
が流れることがない半導体設計が可能となる。Therefore, it is necessary to have impurity diffusion regions of the same type (P-type or N-type) adjacent to each other in one semiconductor chip, and to connect the respective impurity diffusion regions to power sources separated from each other. In some cases, even if the gap between the impurity diffusion regions is narrowed, it is possible to design a semiconductor in which a current does not flow between the impurity diffusion regions.
【００５５】上記の問題点を解決するために、請求項１
４に記載の発明は、第１電源に接続された第１不純物拡
散領域と、前記第１電源から分離された第２電源に接続
されるとともに、前記第１不純物拡散領域と同種の第２
不純物拡散領域とが配置された半導体チップであって、
前記第１不純物拡散領域と前記第２不純物拡散領域との
間の領域に、前記第１不純物拡散領域又は前記第２不純
物拡散領域とは異種の第３不純物拡散領域が配置されて
構成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a fourth aspect of the present invention, there is provided a first impurity diffusion region connected to a first power source and a second power source separated from the first power source, and a second impurity of the same type as the first impurity diffusion region.
A semiconductor chip in which an impurity diffusion region is arranged,
A third impurity diffusion region different from the first impurity diffusion region or the second impurity diffusion region is arranged in a region between the first impurity diffusion region and the second impurity diffusion region.
【００５６】請求項１４に記載の発明の半導体チップの
作用によれば、第１不純物拡散領域と第２不純物拡散領
域との間の領域に、第１不純物拡散領域又は第２不純物
拡散領域とは異種の第３不純物拡散領域が配置されてい
る。According to the operation of the semiconductor chip of the fourteenth aspect, the first impurity diffusion region or the second impurity diffusion region is provided in the region between the first impurity diffusion region and the second impurity diffusion region. Dissimilar third impurity diffusion regions are arranged.
【００５７】よって、第１不純物拡散領域と第２不純物
拡散領域とを、それぞれが個別に、相互に分離された電
源に接続する場合に、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、第１不純物拡散領域と
第２不純物拡散領域間に電流が流れることがない。Therefore, when the first impurity diffusion region and the second impurity diffusion region are individually connected to the power sources separated from each other, the gap between the first impurity diffusion region and the second impurity diffusion region is formed. Even if is narrowed, no current flows between the first impurity diffusion region and the second impurity diffusion region.
【００５８】上記の問題点を解決するために、請求項１
５に記載の発明は、請求項１４に記載の半導体チップに
おいて、前記第３不純物拡散領域は、前記第２不純物拡
散領域を含むマクロセル領域の周囲に略リング状に配置
されて構成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a fifth aspect of the present invention, in the semiconductor chip according to the fourteenth aspect, the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region.
【００５９】請求項１５に記載の発明の半導体チップの
作用によれば、請求項１４に記載の発明の作用に加え
て、第３不純物拡散領域は、第２不純物拡散領域を含む
マクロセル領域の周囲に略リング状に配置される。According to the operation of the semiconductor chip of the fifteenth aspect of the invention, in addition to the function of the invention of the fourteenth aspect, the third impurity diffusion region is surrounded by the macro cell region including the second impurity diffusion region. Are arranged in a substantially ring shape.
【００６０】よって、マクロセル領域と他の領域間の間
隙が狭い場合でも、第１不純物拡散領域と第２不純物拡
散領域間に電流が流れることがないので、マクロセル領
域の電源と他の領域の電源とを分離することができる。Therefore, even if the gap between the macro cell region and the other region is narrow, no current flows between the first impurity diffusion region and the second impurity diffusion region. Therefore, the power source of the macro cell region and the power source of the other regions are not supplied. And can be separated.
【００６１】上記の問題点を解決するために、請求項１
６に記載の発明は、請求項１４に記載の半導体チップに
おいて、前記第３不純物拡散領域は、前記第１不純物拡
散領域を含むマクロセル領域の周囲に略リング状に配置
されて構成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a sixth aspect of the present invention, in the semiconductor chip according to the fourteenth aspect, the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region.
【００６２】請求項１６に記載の発明の半導体チップの
作用によれば、請求項１４に記載の発明の作用に加え
て、第３不純物拡散領域は、第１不純物拡散領域を含む
マクロセル領域の周囲に略リング状に配置される。According to the operation of the semiconductor chip of the sixteenth aspect of the invention, in addition to the operation of the invention of the fourteenth aspect, the third impurity diffusion region is formed around the macro cell region including the first impurity diffusion region. Are arranged in a substantially ring shape.
【００６３】よって、マクロセル領域と他の領域間の間
隙が狭い場合でも、第１不純物拡散領域と第２不純物拡
散領域間に電流が流れることがないので、マクロセル領
域の電源と他の領域の電源とを分離することができる。Therefore, even if the gap between the macro cell region and the other regions is narrow, no current flows between the first impurity diffusion region and the second impurity diffusion region, so that the power source of the macro cell region and the power source of the other regions are not supplied. And can be separated.
【００６４】上記の問題点を解決するために、請求項１
７に記載の発明は、第１電源に接続されたＰ型ウェル等
のＰ型の第１不純物拡散領域及びＮ型ウェル等のＮ型の
第２不純物拡散領域とを含むロジック部等の第１領域
と、前記第１電源から分離された第２電源に接続された
Ｐ型ウェル等のＰ型の第３不純物拡散領域及びＮ型ウェ
ル等のＮ型の第４不純物拡散領域とを含むマクロ部等の
第２領域とが配置された半導体チップであって、前記第
１領域と前記第２領域との間の領域に一又は複数のＰ型
ウェル等のＰ型の第５不純物拡散領域及び一又は複数の
Ｎ型ウェル等のＮ型の第６不純物拡散領域が、前記第１
領域と前記第２領域のうち、一方から他方へ向かう方向
に交互に複数配置されて構成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a seventh aspect of the present invention, there is provided a first logic part or the like including a P-type first impurity diffusion region such as a P-type well connected to a first power source and an N-type second impurity diffusion region such as an N-type well. A macro part including a region and a P-type third impurity diffusion region such as a P-type well connected to a second power supply separated from the first power supply and an N-type fourth impurity diffusion region such as an N-type well. A second region such as a P-type fifth impurity diffusion region such as one or a plurality of P-type wells and a first region in the region between the first region and the second region. Alternatively, the N-type sixth impurity diffusion region such as a plurality of N-type wells is formed into the first
A plurality of regions and the second region are alternately arranged in a direction from one to the other.
【００６５】請求項１７に記載の発明の半導体チップの
作用によれば、Ｐ型の第１不純物拡散領域及びＮ型の第
２不純物拡散領域とを含む第１領域とＰ型の第３不純物
拡散領域及びＮ型の第４不純物拡散領域とを含む第２領
域との間の領域に一又は複数のＰ型の第５不純物拡散領
域及び一又は複数のＮ型の第６不純物拡散領域が、第１
領域と第２領域のうち、一方から他方へ向かう方向に交
互に配置されている。According to the operation of the semiconductor chip of the seventeenth aspect, the first region including the P-type first impurity diffusion region and the N-type second impurity diffusion region and the P-type third impurity diffusion region. One or more P-type fifth impurity diffusion regions and one or more N-type sixth impurity diffusion regions are provided in a region between the region and the second region including the N-type fourth impurity diffusion region, 1
The regions and the second regions are alternately arranged in the direction from one to the other.
【００６６】よって、第１領域と第２領域のそれぞれが
個別に、相互に分離された電源に接続される場合に、第
１領域と第２領域間の間隙を狭くしても、第１領域と第
２領域間に電流が流れることがない。Therefore, when each of the first region and the second region is individually connected to the power supply separated from each other, even if the gap between the first region and the second region is narrowed, the first region No current flows between the second area and the second area.
【００６７】上記の問題点を解決するために、請求項１
８に記載の発明は、請求項１７に記載の半導体チップに
おいて、前記第５不純物拡散領域及び前記第６不純物拡
散領域は、互いに略並行に配置されていると共に、前記
第２領域の周囲に略リング状に配置されて構成される。In order to solve the above-mentioned problems, claim 1
According to an eighth aspect of the present invention, in the semiconductor chip according to the seventeenth aspect, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and are substantially arranged around the second region. It is arranged in a ring shape.
【００６８】請求項１８に記載の発明の半導体チップの
作用によれば、請求項１７に記載の発明の作用に加え
て、第５不純物拡散領域及び第６不純物拡散領域は、互
いに略並行に配置されていると共に、第２領域の周囲に
略リング状に配置されている。According to the operation of the semiconductor chip of the eighteenth aspect, in addition to the operation of the seventeenth aspect, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other. In addition, it is arranged in a substantially ring shape around the second region.
【００６９】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００７０】上記の問題点を解決するために、請求項１
９に記載の発明は、請求項１７に記載の半導体チップに
おいて、前記第５不純物拡散領域及び前記第６不純物拡
散領域は、互いに略並行に配置されていると共に、前記
第１領域の周囲に略リング状に配置されて構成される。In order to solve the above-mentioned problems, the method according to claim 1
According to a ninth aspect of the present invention, in the semiconductor chip according to the seventeenth aspect, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and are substantially arranged around the first region. It is arranged in a ring shape.
【００７１】請求項１９に記載の発明の半導体チップの
作用によれば、請求項１７に記載の発明の作用に加え
て、第５不純物拡散領域及び第６不純物拡散領域は、互
いに略並行に配置されていると共に、第１領域の周囲に
略リング状に配置されている。According to the operation of the semiconductor chip of the invention described in Item 19, in addition to the effect of the invention described in Item 17, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other. In addition, it is arranged in a substantially ring shape around the first region.
【００７２】よって、第１領域と第２領域が同種（Ｐ型
同士又はＮ型同士）の不純物拡散領域を含む場合に、第
１領域と第２領域間の間隙を狭くしても、当該第１領域
と第２領域間に電流が流れることがないので、第１領域
の電源と第２領域の電源とを分離することができる。Therefore, when the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, Since no current flows between the first region and the second region, the power source in the first region and the power source in the second region can be separated.
【００７３】[0073]
【発明の実施の形態】次に、本発明の好適な実施形態に
ついて図１乃至図３を用いて説明する。 （Ｉ）装置構成 始めに、実施形態に係る半導体チップ設計装置の構成に
ついて図１を用いて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Next, a preferred embodiment of the present invention will be described with reference to FIGS. (I) Device Configuration First, the configuration of the semiconductor chip designing device according to the embodiment will be described with reference to FIG.
【００７４】図１に示すように、実施形態に係る半導体
チップ設計装置ＣＤは、ロジック部を構成するゲートア
レイにおけるゲート素子の予め設計された配置データを
記憶するライブラリ記憶装置１７と、必要な設計データ
等を入力するための入力手段としてのキーボード１０
と、上記設計データを他の設計装置で設計した場合の当
該設計データが記録されたフレキシブルディスク等の記
録媒体からキーボード１０の指示に基づき当該設計デー
タを読み出す入力手段としてのフレキシブルディスクド
ライブ等の読出装置１１と、後述のフローチャートに基
づいて、ロジック部及びマクロ部並びに当該ロジック部
とマクロ部の間の領域に後述のＰウェルリングＰＲ及び
ＮウェルリングＮＲを形成するためのウェル配置データ
等を生成するためのＣＰＵ等の処理装置１２と、処理装
置１２におけるウェル配置データ等生成処理のための後
述のフローチャートに対応するプログラム等を記憶し、
必要に応じて出力するＲＯＭ（Read Only Memory）１３
と、ウェル配置データ等生成処理の結果又は後述の実施
例の処理を実行中におけるレイアウト等を表示するため
の表示手段としてのディスプレイ１４と、ウェル配置デ
ータ等生成処理の結果を記憶するための記憶手段として
のフレキシブルディスクドライブ、ＨＤ（HardDisk ）
ドライブ等の記憶装置１５と、ウェル配置データ等生成
処理の結果をデータとして出力するためのプリンタ１６
とにより構成されている。As shown in FIG. 1, the semiconductor chip designing apparatus CD according to the embodiment includes a library storage unit 17 for storing prearranged layout data of gate elements in a gate array forming a logic section, and a required design. Keyboard 10 as input means for inputting data and the like
And a flexible disk drive or the like as input means for reading the design data from a recording medium, such as a flexible disk, in which the design data is recorded when the design data is designed by another design device, based on an instruction from the keyboard 10. Based on the device 11 and a flow chart described later, well placement data for forming a P well ring PR and an N well ring NR, which will be described later, in a logic portion and a macro portion and a region between the logic portion and the macro portion are generated. A processing device 12 such as a CPU for performing the processing, and a program or the like corresponding to a later-described flowchart for well placement data generation processing in the processing device 12,
ROM (Read Only Memory) 13 that outputs as needed
And a display 14 as a display unit for displaying the result of the well placement data etc. generation process or the layout etc. during execution of the process of the embodiment described later, and a memory for storing the result of the well placement data etc. generation process. Flexible disk drive as a means, HD (HardDisk)
A storage device 15 such as a drive, and a printer 16 for outputting the result of the generation processing such as well placement data as data.
It is composed of
【００７５】ここで、上述の構成における処理装置１２
が、本発明における第１不純物拡散領域データ生成手
段、第２不純物拡散領域データ生成手段、領域データ生
成手段及び不純物拡散領域データ生成手段として機能す
る。 （II）動作説明 次に、処理装置１２におけるウェル配置データ等生成処
理を中心として、実施形態に係る半導体チップ設計装置
ＣＤの動作について、ロジック部とマクロ部を電源分離
する必要がある場合を例として、図２及び図３に基づき
説明する。Here, the processing device 12 in the above-mentioned configuration
Function as the first impurity diffusion region data generation unit, the second impurity diffusion region data generation unit, the region data generation unit, and the impurity diffusion region data generation unit in the present invention. (II) Description of Operation Next, with respect to the operation of the semiconductor chip designing apparatus CD according to the embodiment, focusing on the well placement data generation processing in the processing apparatus 12, an example of the case where it is necessary to separate the power supply from the logic unit and the macro unit Will be described with reference to FIGS. 2 and 3.
【００７６】実施形態のウェル配置データ等生成処理に
おいては、始めに、ライブラリ記憶装置１７に記憶され
たゲートアレイ配置データ及びキーボード１０又は読出
装置１１を介して入力された設計データに基づき、処理
装置１２において、第１領域としてのロジック部１にお
けるＰウェル３及びＮウェル４の配置データが生成され
る（ステップＳ１）。ステップＳ１の処理において、ロ
ジック部１に配置すべき回路に対応して各ウェルの配置
が決定される。In the well layout data generation processing of the embodiment, first, based on the gate array layout data stored in the library storage device 17 and the design data input via the keyboard 10 or the reading device 11, the processing device is processed. At 12, the placement data of the P well 3 and the N well 4 in the logic unit 1 as the first region is generated (step S1). In the process of step S1, the placement of each well is determined corresponding to the circuit to be placed in the logic section 1.
【００７７】ロジック部１における各ウェルの配置デー
タが生成されると（ステップＳ１）、次に、キーボード
１０又は読出装置１１を介して入力された設計データに
基づき、第２領域としてのマクロ部２におけるＰウェル
及びＮウェルの配置データが生成される（ステップＳ
２）。ステップＳ２の処理において、マクロ部２に配置
すべき回路に対応して各ウェルの配置が決定される。こ
のマクロ部２に配置すべき回路は、アナログ回路等を含
むものであり、ロジック部１に形成される回路とは電源
を分離すべきものである。マクロ部２の各ウェルの配置
データが生成されると（ステップＳ２）、次に、ロジッ
ク部１とマクロ部２の間の領域に、一のＰウェルリング
ＰＲと一のＮウェルリングＮＲとを形成するためのウェ
ルリング配置データが生成される（ステップＳ３）。こ
のとき、ＰウェルリングＰＲ及びＮウェルリングＮＲ
は、図３に示すように、マクロ部２を囲むように略リン
グ状に配置される。更に、図３に示すように、Ｐウェル
リングＰＲの幅ｔPR及びＮウェルリングＮＲの幅ｔNR、
ＰウェルリングＰＲとＮウェルリングＮＲの間隔ｔ11並
びにＰウェルリングＰＲ又はＮウェルリングＮＲとロジ
ック部１又はマクロ部２との間隔ｔ21又はｔ22は、それ
ぞれ、半導体チップＣの設計ルールにより規定される最
小長さとされる。When the layout data of each well in the logic section 1 is generated (step S1), the macro section 2 as the second area is then generated based on the design data input via the keyboard 10 or the reading device 11. P-well and N-well placement data in step S is generated (step S
2). In the process of step S2, the placement of each well is determined corresponding to the circuit to be placed in the macro unit 2. The circuit to be arranged in the macro unit 2 includes an analog circuit and the like, and the power supply should be separated from the circuit formed in the logic unit 1. When the placement data of each well of the macro unit 2 is generated (step S2), next, one P well ring PR and one N well ring NR are set in the region between the logic unit 1 and the macro unit 2. Welling arrangement data for forming is generated (step S3). At this time, P well ring PR and N well ring NR
Are arranged in a substantially ring shape so as to surround the macro portion 2, as shown in FIG. Further, as shown in FIG. 3, the width t PR of the P well ring PR and the width t NR of the N well ring NR ,
The distance t 11 between the P-well ring PR and the N-well ring NR and the distance t 21 or t 22 between the P-well ring PR or the N-well ring NR and the logic unit 1 or the macro unit 2 depend on the design rule of the semiconductor chip C, respectively. The minimum length is specified.
【００７８】ウェルリング配置データが生成されると
（ステップＳ３）、次に、キーボード１０又は読出装置
１１を介して入力された設計データに基づき、ロジック
部１及びマクロ部２内の配線レイアウトデータが生成さ
れる（ステップＳ４）。When the welling layout data is generated (step S3), the wiring layout data in the logic section 1 and the macro section 2 is next calculated based on the design data input via the keyboard 10 or the reading device 11. It is generated (step S4).
【００７９】ステップＳ４においてロジック部１及びマ
クロ部２内の配線レイアウトデータが生成された後は、
当該配線レイアウトデータ及びステップＳ１乃至Ｓ３の
処理で生成されたウェル配置データに基づいて所定の自
動配線が実行され、ロジック部１とマクロ部２の電源が
分離されたマクロ埋め込み型セルアレイ半導体チップＣ
を構成するためのレイアウトが完成することとなる。After the wiring layout data in the logic section 1 and the macro section 2 is generated in step S4,
A macro-embedded cell array semiconductor chip C in which a predetermined automatic wiring is executed based on the wiring layout data and the well layout data generated in the processes of steps S1 to S3, and the logic unit 1 and the macro unit 2 are separated from each other in power supply.
The layout for constructing is completed.
【００８０】ここで、ＰウェルリングＰＲ及びＮウェル
リングＮＲの作用について図３を用いて具体的に説明す
ると、マクロ部２の外周部にＰウェルが形成される場合
には、当該Ｐウェルとロジック部１のＰウェル３との間
にＮウェルリングＮＲが存在することにより、マクロ部
２外周のＰウェルとロジック部１のＰウェル３との間に
電流が発生することはない。これは、当該マクロ部２外
周のＰウェル又はＰウェル３との間に異種の不純物拡散
領域であるＮウェルリングＮＲが存在し、更にマクロ部
２外周のＰウェル又はＰウェル３とＮウェルリングＮＲ
との電位が相互に異なることによるものである。同様
に、マクロ部２の外周部にＮウェルが形成される場合に
は、当該Ｎウェルとロジック部１のＮウェル４との間に
ＰウェルリングＰＲが存在することにより、当該Ｎウェ
ル間の電流が遮断される。Here, the operation of the P well ring PR and the N well ring NR will be specifically described with reference to FIG. 3. When a P well is formed in the outer peripheral portion of the macro portion 2, the P well ring PR Since the N well ring NR exists between the P well 3 of the logic section 1 and the P well 3 of the macro section 2, no current is generated between the P well 3 of the macro section 2 and the P well 3 of the logic section 1. This is because an N well ring NR, which is a different type of impurity diffusion region, exists between the P well or P well 3 on the outer periphery of the macro portion 2, and the P well or P well 3 and the N well ring on the outer periphery of the macro portion 2 are present. NR
This is because the potentials of and are different from each other. Similarly, when an N well is formed in the outer peripheral portion of the macro portion 2, the P well ring PR exists between the N well and the N well 4 of the logic portion 1, so that the N well The current is cut off.
【００８１】この各ウェルリングの作用によりロジック
部１とマクロ部２間で電流が生じることがなく、当該ロ
ジック部１とマクロ部２の間で電源が分離されるが、こ
のとき、ロジック部１とマクロ部２の間隔ｔ1 又はｔ2
は半導体チップＣの設計ルールにより規定され、図７に
示すような広い間隔を取る必要がない。Due to the action of each well ring, no current is generated between the logic section 1 and the macro section 2, and the power supply is separated between the logic section 1 and the macro section 2. At this time, however, the logic section 1 And the interval t 1 or t 2 between the macro part 2
Is defined by the design rule of the semiconductor chip C, and it is not necessary to set a wide interval as shown in FIG.
【００８２】以上説明したように、実施形態によれば、
ロジック部１とマクロ部２との間隔を広くすることなく
ロジック部１とマクロ部２との電源を分離することがで
きるので、半導体チップＣ自体を小型化することができ
ると共に、半導体チップＣの設計における自由度を向上
させることができる。また、実施形態の半導体チップ設
計装置ＣＤにより設計製作された半導体チップＣにおい
ても、ロジック部１とマクロ部２との間隔を広くするこ
となくロジック部１とマクロ部２との電源を分離するこ
とができるので、半導体チップＣ自体を小型化すること
ができる。 （III ）変形形態 以上説明した実施形態においては、ＰウェルリングＰＲ
及びＮウェルリングＮＲを連続した略リング状とした
が、本発明はこれに限られるものではなく、同種（Ｐ型
同士又はＮ型同士）のウェルが対向する部分のみにＰウ
ェルリングＰＲ又はＮウェルリングＮＲを形成するよう
にしてもよい。より具体的には、図４にその外観図を示
すように、マクロ部２の外周部がＰウェルのみである場
合には、ロジック部１との関係で、Ｐウェル同士が対向
する部分にのみＮウェルリングＮＲを不連続に配置して
もよい。この場合は、ロジック部１とマクロ部２の間隔
ｔ1Hは、図３の符号ｔ1 又はｔ2 で示される間隔よりさ
らに狭くすることができる。As described above, according to the embodiment,
Since the power supply for the logic unit 1 and the macro unit 2 can be separated without increasing the distance between the logic unit 1 and the macro unit 2, the semiconductor chip C itself can be downsized and the semiconductor chip C The degree of freedom in design can be improved. Also in the semiconductor chip C designed and manufactured by the semiconductor chip designing apparatus CD of the embodiment, the power supply for the logic unit 1 and the macro unit 2 should be separated without widening the interval between the logic unit 1 and the macro unit 2. Therefore, the semiconductor chip C itself can be miniaturized. (III) Modification In the embodiment described above, the P well ring PR is used.
The N-well ring NR and the N-well ring NR are continuous and substantially ring-shaped. However, the present invention is not limited to this, and the P well ring PR or N The well ring NR may be formed. More specifically, as shown in the external view of FIG. 4, when the outer peripheral portion of the macro portion 2 is only the P well, only the portion where the P wells face each other is related to the logic portion 1. The N well ring NR may be discontinuously arranged. In this case, the interval t 1H between the logic unit 1 and the macro unit 2 can be made narrower than the interval indicated by reference numeral t 1 or t 2 in FIG.
【００８３】また、上記の実施形態では、マクロ部２の
周囲にロジック部１を略リング状に配置したが、ロジッ
ク部１を囲むようにマクロ部２を形成する場合には、ロ
ジック部１の周囲にＰウェルリングＰＲ及びＮウェルリ
ングＮＲを配置してもよい。In the above embodiment, the logic part 1 is arranged in a ring shape around the macro part 2. However, when the macro part 2 is formed so as to surround the logic part 1, the logic part 1 is You may arrange P well ring PR and N well ring NR in the circumference.
【００８４】更に、ＰウェルリングＰＲ及びＮウェルリ
ングＮＲの数は、それぞれ一に限られるものではなく、
複数配置することもできる。Furthermore, the numbers of P well ring PR and N well ring NR are not limited to one, respectively.
It is also possible to arrange a plurality.
【００８５】[0085]
【発明の効果】以上説明したように、請求項１又は７に
記載の発明によれば、第１不純物拡散領域データ、第２
不純物拡散領域データ及び第３不純物拡散領域データを
用いて設計製作された半導体チップにおいては、第１不
純物拡散領域と第２不純物拡散領域の間の領域に、第１
不純物拡散領域と第２不純物拡散領域とは異種の第３不
純物拡散領域が配置されるので、第１不純物拡散領域と
第２不純物拡散領域が同種（Ｐ型同士又はＮ型同士）の
不純物拡散領域であり、更に、それぞれが個別に、相互
に分離された電源に接続される場合に、第１不純物拡散
領域と第２不純物拡散領域間の間隙を狭くしても、第１
不純物拡散領域と第２不純物拡散領域間に電流が流れる
ことがない。As described above, according to the invention of claim 1 or 7, the first impurity diffusion region data and the second impurity diffusion region data are used.
In the semiconductor chip designed and manufactured using the impurity diffusion region data and the third impurity diffusion region data, the first chip is formed in the region between the first impurity diffusion region and the second impurity diffusion region.
Since the impurity diffusion region and the second impurity diffusion region are different from each other in the third impurity diffusion region, the first impurity diffusion region and the second impurity diffusion region are of the same type (P-type or N-type). In addition, when each of them is individually connected to the power supplies separated from each other, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed,
No current flows between the impurity diffusion region and the second impurity diffusion region.
【００８６】従って、異なる電源に接続された同種の不
純物拡散領域である第１不純物拡散領域及び第２不純物
拡散領域が必要となる場合に、当該第１不純物拡散領域
及び第２不純物拡散領域の回路設計に変更を加えること
なく、第１不純物拡散領域が接続されている第１電源
と、第２不純物拡散領域が接続されている第２電源とを
完全に分離することができる。Therefore, when the first impurity diffusion region and the second impurity diffusion region which are the same type of impurity diffusion regions connected to different power supplies are required, the circuits of the first impurity diffusion region and the second impurity diffusion region are required. It is possible to completely separate the first power supply connected to the first impurity diffusion region and the second power supply connected to the second impurity diffusion region without changing the design.
【００８７】更に、第１不純物拡散領域と第２不純物拡
散領域間の間隙を狭くしても、それぞれの電源を完全に
分離することができるので、半導体チップとしての集積
度を向上させ、当該半導体チップの小型化を図ることが
でき、その設計における自由度も向上する。Further, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, the respective power supplies can be completely separated, so that the degree of integration as a semiconductor chip is improved and the semiconductor is concerned. The size of the chip can be reduced, and the degree of freedom in designing the chip can be improved.
【００８８】請求項２又は３に記載の発明によれば、請
求項１に記載の発明の効果に加えて、第３不純物拡散領
域は、第２不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置されるので、第１不純物拡散領域と
第２不純物拡散領域間の間隙を狭くしても、当該第１不
純物拡散領域と第２不純物拡散領域間に電流が流れるこ
とがないので、マクロセル領域の電源と他の領域の電源
とを分離することができる。According to the invention described in claim 2 or 3, in addition to the effect of the invention described in claim 1, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the second impurity diffusion region. Since they are arranged in a matrix, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, current does not flow between the first impurity diffusion region and the second impurity diffusion region. It is possible to separate the power supply for the area and the power supply for the other area.
【００８９】請求項４又は１０に記載の発明によれば、
第１領域データ、第２領域データ及び不純物拡散領域デ
ータに基づいて設計製作された半導体チップにおいて
は、第１領域と第２領域の間の領域に第５不純物拡散領
域及び第６不純物拡散領域が、第１領域と第２領域のう
ち、一方から他方に向かう方向に交互に複数配置される
ので、第１領域と第２領域のそれぞれが個別に、相互に
分離された電源に接続される場合に、第１領域と第２領
域間の間隙を狭くしても、第１領域と第２領域間に電流
が流れることがない。According to the invention described in claim 4 or 10,
In the semiconductor chip designed and manufactured based on the first region data, the second region data, and the impurity diffusion region data, the fifth impurity diffusion region and the sixth impurity diffusion region are formed in the region between the first region and the second region. In the case where a plurality of first regions and second regions are alternately arranged in the direction from one to the other, each of the first regions and the second regions is individually connected to a mutually separated power source. Moreover, even if the gap between the first region and the second region is narrowed, the current does not flow between the first region and the second region.
【００９０】従って、当該第１領域及び第２領域の回路
設計に変更を加えることなく、第１領域が接続されてい
る第１電源と、第２領域が接続されている第２電源とを
完全に分離することができる。Therefore, the first power source to which the first region is connected and the second power source to which the second region is connected can be completely replaced without changing the circuit design of the first and second regions. Can be separated into
【００９１】更に、第１領域と第２領域間の間隙を狭く
しても、それぞれの電源を完全に分離することができる
ので、半導体チップとしての集積度を向上させ、当該半
導体チップの小型化を図ることができ、その設計におけ
る自由度も向上する。Further, even if the gap between the first region and the second region is narrowed, the respective power supplies can be completely separated, so that the degree of integration as a semiconductor chip is improved and the semiconductor chip is miniaturized. Therefore, the degree of freedom in the design can be improved.
【００９２】請求項５に記載の発明によれば、請求項４
に記載の発明の効果に加えて、第５不純物拡散領域及び
第６不純物拡散領域は、互いに略並行して配置されると
共に、第２領域の周囲に略リング状に配置されるので、
第１領域と第２領域が同種（Ｐ型同士又はＮ型同士）の
不純物拡散領域を含む場合に、第１領域と第２領域間の
間隙を狭くしても、当該第１領域と第２領域間に電流が
流れることがないので、第１領域の電源と第２領域の電
源とを分離することができる。According to the invention of claim 5, claim 4
In addition to the effects of the invention described in (1), since the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and are arranged in a substantially ring shape around the second region,
In the case where the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, the first region and the second region Since no current flows between the regions, the power source in the first region and the power source in the second region can be separated.
【００９３】請求項６に記載の発明によれば、請求項４
に記載の発明の効果に加えて、第５不純物拡散領域及び
第６不純物拡散領域は、互いに略並行して配置されると
共に、第１領域の周囲に略リング状に配置されるので、
第１領域と第２領域が同種（Ｐ型同士又はＮ型同士）の
不純物拡散領域を含む場合に、第１領域と第２領域間の
間隙を狭くしても、当該第１領域と第２領域間に電流が
流れることがないので、第１領域の電源と第２領域の電
源とを分離することができる。According to the invention of claim 6, claim 4
In addition to the effects of the invention described in (1), since the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and arranged in a substantially ring shape around the first region,
In the case where the first region and the second region include the same type (P-type or N-type) impurity diffusion region, even if the gap between the first region and the second region is narrowed, the first region and the second region Since no current flows between the regions, the power source in the first region and the power source in the second region can be separated.
【００９４】請求項８又は９に記載の発明によれば、請
求項７に記載の発明の効果に加えて、第３不純物拡散領
域は、第２不純物拡散領域を含むマクロセル領域の周囲
に略リング状に配置されるので、第１不純物拡散領域と
第２不純物拡散領域間の間隙を狭くしても、当該第１不
純物拡散領域と第２不純物拡散領域間に電流が流れるこ
とがないので、マクロセル領域の電源と他の領域の電源
とを分離することができる。According to the invention of claim 8 or 9, in addition to the effect of the invention of claim 7, the third impurity diffusion region is substantially ring-shaped around the macro cell region including the second impurity diffusion region. Since they are arranged in a matrix, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, current does not flow between the first impurity diffusion region and the second impurity diffusion region. It is possible to separate the power supply for the area and the power supply for the other area.
【００９５】請求項１１に記載の発明によれば、請求項
１０に記載の発明の効果に加えて、第５不純物拡散領域
及び第６不純物拡散領域は、互いに略並行して配置され
ると共に、第２領域の周囲に略リング状に配置されるの
で、第１領域と第２領域が同種（Ｐ型同士又はＮ型同
士）の不純物拡散領域を含む場合に、第１領域と第２領
域間の間隙を狭くしても、当該第１領域と第２領域間に
電流が流れることがないので、第１領域の電源と第２領
域の電源とを分離することができる。According to the eleventh aspect of the invention, in addition to the effect of the tenth aspect of the invention, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and Since the first region and the second region include impurity diffusion regions of the same type (P-type or N-type), since the first and second regions are arranged around the second region in a substantially ring shape, the first region and the second region are separated from each other. Even if the gap is narrowed, the current does not flow between the first region and the second region, so that the power source in the first region and the power source in the second region can be separated.
【００９６】請求項１２に記載の発明によれば、請求項
１０に記載の発明の効果に加えて、第５不純物拡散領域
及び第６不純物拡散領域は、互いに略平行に配置される
と共に、第１領域の周囲に略リング状に配置されるの
で、第１領域と第２領域が同種（Ｐ型同士又はＮ型同
士）の不純物拡散領域を含む場合に、第１領域と第２領
域間の間隙を狭くしても、当該第１領域と第２領域間に
電流が流れることがないので、第１領域の電源と第２領
域の電源とを分離することができる。According to the twelfth aspect of the invention, in addition to the effect of the tenth aspect of the invention, the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and Since the first region and the second region include the impurity diffusion regions of the same type (P-type or N-type), since the first region and the second region are arranged around the one region in a substantially ring shape, the gap between the first region and the second region is large. Even if the gap is narrowed, current does not flow between the first region and the second region, so that the power source in the first region and the power source in the second region can be separated.
【００９７】請求項１３に記載の発明によれば、請求項
７乃至１２のいずれかに記載の発明の効果に加えて、一
の半導体チップ内に同種（Ｐ型同士又はＮ型同士）の不
純物拡散領域が隣接して存在し、且つ、それぞれの不純
物拡散領域を互いに分離された電源に接続する必要があ
る場合に、当該不純物拡散領域間の間隙を狭くしても、
当該不純物拡散領域間に電流が流れることがない半導体
設計が可能となる。According to the invention described in claim 13, in addition to the effect of the invention described in any one of claims 7 to 12, impurities of the same kind (P-type or N-type) are contained in one semiconductor chip. When the diffusion regions are adjacent to each other and it is necessary to connect the respective impurity diffusion regions to power sources separated from each other, even if the gap between the impurity diffusion regions is narrowed,
It is possible to design a semiconductor in which a current does not flow between the impurity diffusion regions.
【００９８】従って、当該不純物拡散領域の回路設計に
変更を加えることなく、当該不純物拡散領域の電源分離
を行うことができるので、半導体設計を簡略化すること
ができる。Therefore, since the power supply of the impurity diffusion region can be separated without changing the circuit design of the impurity diffusion region, the semiconductor design can be simplified.
【００９９】更に、当該不純物拡散領域の間隔を狭くし
ても確実に電源分離をすることができるので、半導体チ
ップとしての集積度を向上させ、当該半導体チップの小
型化を図ることができ、その設計における自由度も向上
する。Further, the power supply can be surely separated even if the interval between the impurity diffusion regions is narrowed, so that the integration degree as a semiconductor chip can be improved and the semiconductor chip can be miniaturized. The degree of freedom in design is also improved.
【０１００】請求項１４に記載の発明の半導体チップに
よれば、同種（Ｐ型同士又はＮ型同士）の第１不純物拡
散領域と第２不純物拡散領域とが個別に相互に分離され
た電源に接続する場合に、第１不純物拡散領域と第２不
純物拡散領域間の間隙を狭くしても、第１不純物拡散領
域と第２不純物拡散領域間に電流が流れることがない。According to the semiconductor chip of the fourteenth aspect of the present invention, in the power supply in which the first impurity diffusion regions and the second impurity diffusion regions of the same type (P-type or N-type) are individually separated from each other. In the case of connection, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, current does not flow between the first impurity diffusion region and the second impurity diffusion region.
【０１０１】従って、第１不純物拡散領域と第２不純物
拡散領域間の間隙を狭くしても、それぞれの電源を完全
に分離することができるので、半導体チップとしての集
積度を向上させ、当該半導体チップの小型化を図ること
ができる。Therefore, even if the gap between the first impurity diffusion region and the second impurity diffusion region is narrowed, the respective power supplies can be completely separated from each other, so that the integration degree as a semiconductor chip is improved, and the semiconductor chip concerned is improved. The size of the chip can be reduced.
【０１０２】請求項１５又は１６に記載の発明の半導体
チップによれば、請求項１４に記載の発明の効果に加え
て、マクロセル領域と他の領域間の間隙が狭い場合で
も、第１不純物拡散領域と第２不純物拡散領域間に電流
が流れることがないので、マクロセル領域の電源と他の
領域の電源とを分離することができる。According to the semiconductor chip of the invention of claim 15 or 16, in addition to the effect of the invention of claim 14, even when the gap between the macro cell region and the other region is narrow, the first impurity diffusion is performed. Since no current flows between the region and the second impurity diffusion region, the power source in the macro cell region and the power source in other regions can be separated.
【０１０３】請求項１７に記載の発明の半導体チップに
よれば、第１領域と第２領域との間の領域にＰ型の第５
不純物拡散領域及びＮ型の第６不純物拡散領域が、第１
領域と第２領域のうち、一方から他方へ向かう方向に交
互に配置されているので、第１領域と第２領域のそれぞ
れが個別に、相互に分離された電源に接続される場合
に、第１領域と第２領域間の間隙を狭くしても、第１領
域と第２領域間に電流が流れることがない。According to the semiconductor chip of the seventeenth aspect of the present invention, the P-type fifth element is provided in the region between the first region and the second region.
The impurity diffusion region and the N-type sixth impurity diffusion region are the first
Since the regions and the second regions are alternately arranged in the direction from one to the other, when the first region and the second region are individually connected to the power sources separated from each other, Even if the gap between the first region and the second region is narrowed, current does not flow between the first region and the second region.
【０１０４】従って、第１領域と第２領域間の間隙を狭
くしても、それぞれの電源を完全に分離することができ
るので、半導体チップとしての集積度を向上させ、当該
半導体チップの小型化を図ることができる。Therefore, even if the gap between the first region and the second region is narrowed, the respective power supplies can be completely separated, so that the degree of integration as a semiconductor chip can be improved and the semiconductor chip can be miniaturized. Can be achieved.
【０１０５】請求項１８に記載の発明の半導体チップに
よれば、請求項１７に記載の発明の効果に加えて、第５
不純物拡散領域及び第６不純物拡散領域は、互いに略並
行に配置されていると共に、第２領域の周囲に略リング
状に配置されているので、第１領域と第２領域が同種
（Ｐ型同士又はＮ型同士）の不純物拡散領域を含む場合
に、第１領域と第２領域間の間隙を狭くしても、当該第
１領域と第２領域間に電流が流れることがなく、第１領
域の電源と第２領域の電源とを分離することができる。According to the semiconductor chip of the invention described in claim 18, in addition to the effect of the invention described in claim 17,
The impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and are arranged in a substantially ring shape around the second region, so that the first region and the second region are of the same type (P-type Or an N-type impurity diffusion region is included, even if the gap between the first region and the second region is narrowed, no current flows between the first region and the second region. It is possible to separate the power source in the second region and the power source in the second region.
【０１０６】請求項１９に記載の発明の半導体チップに
よれば、請求項１７に記載の発明の効果に加えて、第５
不純物拡散領域及び第６不純物拡散領域は、互いに略並
行に配置されていると共に、第１領域の周囲に略リング
状に配置されているので、第１領域と第２領域が同種
（Ｐ型同士又はＮ型同士）の不純物拡散領域を含む場合
に、第１領域と第２領域間の間隙を狭くしても、当該第
１領域と第２領域間に電流が流れることがなく、第１領
域の電源と第２領域の電源とを分離することができる。According to the semiconductor chip of the invention described in Item 19, in addition to the effect of the invention described in Item 17,
The impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and are arranged in a substantially ring shape around the first region, so that the first region and the second region are of the same type (P-type Or an N-type impurity diffusion region is included, even if the gap between the first region and the second region is narrowed, no current flows between the first region and the second region. It is possible to separate the power source in the second region and the power source in the second region.
【図１】実施例の半導体チップ設計装置の概要構成ブロ
ック図である。FIG. 1 is a schematic block diagram of a semiconductor chip designing apparatus according to an embodiment.
【図２】実施例の半導体チップ設計装置の動作を示すフ
ローチャートである。FIG. 2 is a flowchart showing the operation of the semiconductor chip designing apparatus of the embodiment.
【図３】実施例のマクロ埋め込み型セルアレイ半導体チ
ップの外観図（平面図）である。FIG. 3 is an external view (plan view) of a macro-embedded cell array semiconductor chip of an example.
【図４】変形例のマクロ埋め込み型セルアレイ半導体チ
ップの外観図（平面図）である。FIG. 4 is an external view (plan view) of a macro embedded cell array semiconductor chip of a modified example.
【図５】従来技術のマクロ埋め込み型セルアレイ半導体
チップの外観図（平面図）である。FIG. 5 is an external view (plan view) of a conventional macro-embedded cell array semiconductor chip.
【図６】従来技術のマクロ埋め込み型セルアレイ半導体
チップの部分拡大図である。FIG. 6 is a partially enlarged view of a conventional macro-embedded cell array semiconductor chip.
【図７】従来技術の問題点を説明する図である。FIG. 7 is a diagram illustrating a problem of the conventional technique.
１、１０２…ロジック部 ２、１０３…マクロ部 ３、１０４…Ｐウェル ４、１０５…Ｎウェル １０…キーボード １１…読出装置 １２…処理装置 １３…ＲＯＭ １４…ディスプレイ １５…記憶装置 １６…プリンタ １７…ライブラリ記憶装置 １００…半導体チップ １０１…Ｉ／Ｏ領域 Ｃ、Ｃ’…半導体チップ ＰＲ…Ｐウェルリング ＮＲ…Ｎウェルリング ＶSS、ＶDD…電源1, 102 ... Logic part 2, 103 ... Macro part 3, 104 ... P well 4, 105 ... N well 10 ... Keyboard 11 ... Reading device 12 ... Processing device 13 ... ROM 14 ... Display 15 ... Storage device 16 ... Printer 17 ... Library storage device 100 ... Semiconductor chip 101 ... I / O area C, C '... Semiconductor chip PR ... P well ring NR ... N well ring V SS , V DD ... Power supply
Claims (19)
された第１不純物拡散領域と、前記第１電源から分離さ
れた第２電源に接続されるとともに、前記第１不純物拡
散領域と同種の第２不純物拡散領域とを配置するための
レイアウト設計方法において、 前記第１不純物拡散領域に対応する第１不純物拡散領域
データと、前記第２不純物拡散領域に対応する第２不純
物拡散領域データとを生成する第１不純物拡散領域デー
タ生成工程と、 前記第１不純物拡散領域と前記第２不純物拡散領域との
間の領域に、前記第１不純物拡散領域又は前記第２不純
物拡散領域とは異種の第３不純物拡散領域を配置するた
めの第３不純物拡散領域データを生成する第２不純物拡
散領域データ生成工程と、 を備えることを特徴とするレイアウト設計方法。1. A first impurity diffusion region connected to a first power source, a second power source separated from the first power source, and the first impurity diffusion region on one semiconductor chip. A layout designing method for arranging second impurity diffusion regions of the same kind, comprising: first impurity diffusion region data corresponding to the first impurity diffusion region and second impurity diffusion region data corresponding to the second impurity diffusion region. And a first impurity diffusion region data generation step of generating a first impurity diffusion region and a second impurity diffusion region different from the first impurity diffusion region or the second impurity diffusion region in a region between the first impurity diffusion region and the second impurity diffusion region. A second impurity diffusion region data generating step of generating third impurity diffusion region data for arranging the third impurity diffusion region of, and a layout designing method.
おいて、 前記第３不純物拡散領域は、前記第２不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とするレイアウト設計方法。2. The layout design method according to claim 1, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region. Design method.
おいて、 前記第３不純物拡散領域は、前記第１不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とするレイアウト設計方法。3. The layout design method according to claim 1, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region. Design method.
されたＰ型の第１不純物拡散領域及びＮ型の第２不純物
拡散領域とを含む第１領域と、前記第１電源から分離さ
れた第２電源に接続されたＰ型の第３不純物拡散領域及
びＮ型の第４不純物拡散領域とを含む第２領域とを配置
するためのレイアウト設計方法において、 前記第１領域に対応する第１領域データと、前記第２領
域に対応する第２領域データとを生成する領域データ生
成工程と、 前記第１領域と前記第２領域との間の領域に一又は複数
のＰ型の第５不純物拡散領域及び一又は複数のＮ型の第
６不純物拡散領域を、前記第１領域及び前記第２領域の
うち、一方から他方へ向かう方向に交互に配置するため
の不純物拡散領域データを生成する不純物拡散領域デー
タ生成工程と、 を備えることを特徴とするレイアウト設計方法。4. A first region including a P-type first impurity diffusion region and an N-type second impurity diffusion region connected to a first power supply on one semiconductor chip, and separated from the first power supply. A layout designing method for arranging a second region including a P-type third impurity diffusion region and an N-type fourth impurity diffusion region connected to the generated second power source, the layout designing method corresponding to the first region. A region data generating step of generating first region data and second region data corresponding to the second region, and one or more P-type first regions in a region between the first region and the second region. Generating impurity diffusion region data for alternately arranging an impurity diffusion region and one or more N-type sixth impurity diffusion regions in a direction from one of the first region and the second region toward the other The impurity diffusion region data generation process A layout design method that is characterized by
おいて、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されると共に、前記第２領域
の周囲に略リング状に配置されることを特徴とするレイ
アウト設計方法。5. The layout design method according to claim 4, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and a ring is formed around the second region. A layout design method characterized by being arranged in a line.
おいて、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されると共に、前記第１領域
の周囲に略リング状に配置されることを特徴とするレイ
アウト設計方法。6. The layout design method according to claim 4, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and a ring is formed around the first region. A layout design method characterized by being arranged in a line.
された第１不純物拡散領域と、前記第１電源から分離さ
れた第２電源に接続されるとともに、前記第１不純物拡
散領域と同種の第２不純物拡散領域とを配置するための
レイアウト設計装置において、 前記第１不純物拡散領域に対応する第１不純物拡散領域
データと、前記第２不純物拡散領域に対応する第２不純
物拡散領域データとを生成する第１不純物拡散領域デー
タ生成手段と、 前記第１不純物拡散領域と前記第２不純物拡散領域との
間の領域に、前記第１不純物拡散領域又は前記第２不純
物拡散領域とは異種の第３不純物拡散領域を配置するた
めの第３不純物拡散領域データを生成する第２不純物拡
散領域データ生成手段と、 を備えることを特徴とするレイアウト設計装置。7. A first impurity diffusion region connected to a first power supply, a second power supply separated from the first power supply, and a first impurity diffusion region on one semiconductor chip. In a layout design device for arranging second impurity diffusion regions of the same type, first impurity diffusion region data corresponding to the first impurity diffusion region and second impurity diffusion region data corresponding to the second impurity diffusion region. And a first impurity diffusion region data generating means for generating a first impurity diffusion region and a region between the first impurity diffusion region and the second impurity diffusion region, the first impurity diffusion region and the second impurity diffusion region being different from each other. A second impurity diffusion region data generating means for generating third impurity diffusion region data for arranging the third impurity diffusion region of, and a layout designing device.
おいて、 前記第３不純物拡散領域は、前記第２不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とするレイアウト設計装置。8. The layout design apparatus according to claim 7, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region. Design equipment.
おいて、 前記第３不純物拡散領域は、前記第１不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とするレイアウト設計装置。9. The layout design apparatus according to claim 7, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region. Design equipment.
続されたＰ型の第１不純物拡散領域及びＮ型の第２不純
物拡散領域とを含む第１領域と、前記第１電源から分離
された第２電源に接続されたＰ型の第３不純物拡散領域
及びＮ型の第４不純物拡散領域とを含む第２領域とを配
置するためのレイアウト設計装置において、 前記第１領域に対応する第１領域データと、前記第２領
域に対応する第２領域データとを生成する領域データ生
成手段と、 前記第１領域と前記第２領域との間の領域に一又は複数
のＰ型の第５不純物拡散領域及び一又は複数のＮ型の第
６不純物拡散領域を、前記第１領域と前記第２領域のう
ち、一方から他方へ向かう方向に交互に配置するための
不純物拡散領域データを生成する不純物拡散領域データ
生成手段と、 を備えることを特徴とするレイアウト設計装置。10. A first region on a semiconductor chip, the first region including a P-type first impurity diffusion region and an N-type second impurity diffusion region connected to a first power supply, and separated from the first power supply. A layout designing device for arranging a second region including a P-type third impurity diffusion region and an N-type fourth impurity diffusion region connected to the second power source, which corresponds to the first region. Area data generating means for generating first area data and second area data corresponding to the second area; and one or more P-type first areas in an area between the first area and the second area. Generating impurity diffusion region data for alternately arranging 5 impurity diffusion regions and one or more N-type sixth impurity diffusion regions in a direction from one of the first region and the second region toward the other Means for generating impurity diffusion region data, A layout design device that is characterized by
置において、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されると共に、前記第２領域
の周囲に略リング状に配置されることを特徴とするレイ
アウト設計装置。11. The layout design apparatus according to claim 10, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and a ring is formed around the second region. A layout designing device characterized by being arranged in a pattern.
置において、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されると共に、前記第１領域
の周囲に略リング状に配置されることを特徴とするレイ
アウト設計装置。12. The layout design apparatus according to claim 10, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other and a ring is formed around the first region. A layout designing device characterized by being arranged in a pattern.
レイアウト装置と、 前記レイアウト装置の動作に必要な所定のデータを入力
するための入力手段と、 前記第１不純物拡散領域データ、前記第２不純物拡散領
域データ、前記第３不純物拡散領域データ、前記第１領
域データ、前記第２領域データ、前記不純物拡散領域デ
ータのうち、いずれかのデータに基づく半導体チップレ
イアウトを表示する表示手段と、 少なくとも前記第１不純物拡散領域データ、前記第２不
純物拡散領域データ、前記第３不純物拡散領域データ、
前記第１領域データ、前記第２領域データ及び前記不純
物拡散領域データを記憶する記憶手段と、 を備えることを特徴とする半導体チップ設計装置。13. The layout apparatus according to claim 7, input means for inputting predetermined data necessary for the operation of the layout apparatus, the first impurity diffusion region data, and the first impurity diffusion area data. Display means for displaying a semiconductor chip layout based on any one of the two impurity diffusion region data, the third impurity diffusion region data, the first region data, the second region data, and the impurity diffusion region data; At least the first impurity diffusion region data, the second impurity diffusion region data, the third impurity diffusion region data,
A semiconductor chip designing device comprising: a storage unit that stores the first region data, the second region data, and the impurity diffusion region data.
領域と、前記第１電源から分離された第２電源に接続さ
れるとともに、前記第１不純物拡散領域と同種の第２不
純物拡散領域とが配置された半導体チップであって、 前記第１不純物拡散領域と前記第２不純物拡散領域との
間の領域に、前記第１不純物拡散領域又は前記第２不純
物拡散領域とは異種の第３不純物拡散領域が配置された
ことを特徴とする半導体チップ。14. A first impurity diffusion region connected to a first power source and a second power source separated from the first power source, and a second impurity diffusion region of the same kind as the first impurity diffusion region. And a third chip different from the first impurity diffusion region or the second impurity diffusion region in a region between the first impurity diffusion region and the second impurity diffusion region. A semiconductor chip having an impurity diffusion region arranged therein.
いて、 前記第３不純物拡散領域は、前記第２不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とする半導体チップ。15. The semiconductor chip according to claim 14, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the second impurity diffusion region. .
いて、 前記第３不純物拡散領域は、前記第１不純物拡散領域を
含むマクロセル領域の周囲に略リング状に配置されるこ
とを特徴とする半導体チップ。16. The semiconductor chip according to claim 14, wherein the third impurity diffusion region is arranged in a substantially ring shape around a macro cell region including the first impurity diffusion region. .
物拡散領域及びＮ型の第２不純物拡散領域とを含む第１
領域と、前記第１電源から分離された第２電源に接続さ
れたＰ型の第３不純物拡散領域及びＮ型の第４不純物拡
散領域とを含む第２領域とが配置された半導体チップで
あって、 前記第１領域と前記第２領域との間の領域に一又は複数
のＰ型の第５不純物拡散領域及び一又は複数のＮ型の第
６不純物拡散領域が、前記第１領域と前記第２領域のう
ち、一方から他方に向かう方向に交互に配置されたこと
を特徴とする半導体チップ。17. A first device including a P-type first impurity diffusion region and an N-type second impurity diffusion region connected to a first power supply.
A semiconductor chip in which a region and a second region including a P-type third impurity diffusion region and an N-type fourth impurity diffusion region connected to a second power supply separated from the first power supply are arranged. Then, one or more P-type fifth impurity diffusion regions and one or more N-type sixth impurity diffusion regions are provided in the region between the first region and the second region. A semiconductor chip characterized by being arranged alternately in a direction from one to the other of the second regions.
いて、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されていると共に、前記第２
領域の周囲に略リング状に配置されていることを特徴と
する半導体チップ。18. The semiconductor chip according to claim 17, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and the second impurity diffusion region is formed.
A semiconductor chip, which is arranged in a substantially ring shape around a region.
いて、 前記第５不純物拡散領域及び前記第６不純物拡散領域
は、互いに略並行して配置されていると共に、前記第１
領域の周囲に略リング状に配置されていることを特徴と
する半導体チップ。19. The semiconductor chip according to claim 17, wherein the fifth impurity diffusion region and the sixth impurity diffusion region are arranged substantially parallel to each other, and the first impurity diffusion region is disposed.
A semiconductor chip, which is arranged in a substantially ring shape around a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7169958A JPH0922985A (en) | 1995-07-05 | 1995-07-05 | Method and apparatus for designing layout, semiconductor chip designing apparatus using the same and the semiconductor chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7169958A JPH0922985A (en) | 1995-07-05 | 1995-07-05 | Method and apparatus for designing layout, semiconductor chip designing apparatus using the same and the semiconductor chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0922985A true JPH0922985A (en) | 1997-01-21 |
Family
ID=15895995
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7169958A Withdrawn JPH0922985A (en) | 1995-07-05 | 1995-07-05 | Method and apparatus for designing layout, semiconductor chip designing apparatus using the same and the semiconductor chip |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0922985A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212671B1 (en) | 1997-10-20 | 2001-04-03 | Mitsubishi Electric System Lsi Design Corporation | Mask pattern data producing apparatus, mask pattern data producing method and semiconductor integrated circuit device |
| JP2006100863A (en) * | 2002-10-30 | 2006-04-13 | Nec Electronics Corp | Power source separating structure of semiconductor device and semiconductor manufacturing method |
| JP2009111119A (en) * | 2007-10-30 | 2009-05-21 | Nec Electronics Corp | Layout designing method of semiconductor integrated circuit, layout design program, and layout design assisting apparatus |
-
1995
- 1995-07-05 JP JP7169958A patent/JPH0922985A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6212671B1 (en) | 1997-10-20 | 2001-04-03 | Mitsubishi Electric System Lsi Design Corporation | Mask pattern data producing apparatus, mask pattern data producing method and semiconductor integrated circuit device |
| JP2006100863A (en) * | 2002-10-30 | 2006-04-13 | Nec Electronics Corp | Power source separating structure of semiconductor device and semiconductor manufacturing method |
| JP2009111119A (en) * | 2007-10-30 | 2009-05-21 | Nec Electronics Corp | Layout designing method of semiconductor integrated circuit, layout design program, and layout design assisting apparatus |
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|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20021001 |