JPH09229784A - Signal processing circuit for sensor making use of change in capacitance - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal processing circuit in which change in capacitance is converted, with high sensitivity, into voltage. SOLUTION: Capacitance elements C1, C2 are constituted of a pair of electrodes which are arranged in such a way that their mutual distance is changed by the action of an external force, and the external force is detected by the difference between a capacitance value C1 and a capacitance value C2. A square-wave signal CLK at a prescribed cycle is input to an input terminal T1, it is inverted by an inverter element 51, and it is then branched into a route reaching a node N1 through a delay circuit R1, C1 and into a route reaching a node N2 through a delay circuit R2, C2. Both branched signals are given to an exclusive-OR element 52, a signal based on a phase difference is output at a node N3, it is smoothed by a smoothing circuit RS CS, and a voltage signal is output at an output terminal T2. Open collector-type inverter elements 53, 54 are connected across the terminal T1 and the node N1 as well as across the terminal T1 and the node N2, and the capacitance elements C1, C2 are discharged forcibly when the square-wave signal CLK is in a high-level state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a sensor that utilizes a change in capacitance, and more particularly to a signal for a sensor that detects force, acceleration, magnetism, etc. based on a change in the distance between a pair of electrodes. The present invention relates to a circuit that performs processing.

[0002]

2. Description of the Related Art In the automobile industry, machine industry and the like, there is an increasing demand for sensors capable of accurately detecting physical quantities such as force, acceleration and magnetism. In particular, there is a demand for a small device that can detect these physical quantities for each of two-dimensional or three-dimensional components. In order to meet such a demand, a sensor that detects a physical quantity by utilizing a change in capacitance has been proposed. For example, JP-A-4-148833, JP-A-5-118942, JP-A-5-215627, and International Publication No. WO91 / 10 based on the Patent Cooperation Treaty
Japanese Patent Laid-Open No. 118 proposes a sensor that utilizes a change in capacitance. In these sensors, a capacitive element is composed of a fixed electrode formed on a fixed substrate and a displacement electrode that is displaced by the action of force, and the force applied is based on the change in the capacitance of the capacitive element. Each of the multidimensional components of can be detected.

Control devices for automobiles and industrial robots perform various controls based on output signals from sensors. At this time, the output signal is not in the form of the electrostatic capacitance C but in the voltage value V
It is easier to handle if given in the form of. For this reason,
A signal processing circuit is required to convert the output of the sensor taken out as a change in capacitance into a voltage value. However, in order to obtain an accurate sensor output, it is necessary to use a signal processing circuit that is less likely to cause an error due to temperature. Especially when the sensor is used for automobiles and industrial robots,
Severe temperature conditions of 40 to + 100 ° C. are required, and the temperature characteristics will seriously affect the detection accuracy.

In view of this, Japanese Patent Laid-Open No. 5-346357 proposes a signal processing circuit for a sensor that utilizes a change in capacitance, which can output an accurate detection value without being affected by temperature. There is. In this signal processing circuit,
A CR delay circuit is configured by combining a resistive element with a capacitive element that constitutes the sensor, and a voltage value V corresponding to the capacitive value C is obtained based on the delay time of the periodic signal that has passed through this delay circuit.

[0005]

The above-described conventional signal processing circuit is an excellent circuit in that an error due to temperature is unlikely to occur, but there is a limit in performing more accurate detection. Sensors that detect force, acceleration, magnetism, etc.
In the future, there is a tendency for ever-smaller size to be demanded, and the capacitance value of the built-in capacitive element must be reduced. Therefore, it becomes necessary to detect a finer capacitance change with high sensitivity. As a method of increasing the detection sensitivity of the signal processing circuit described above, there are a method of increasing the resistance value of the resistance element and a method of increasing the frequency of the periodic signal. Because of the blunting, if a certain limit is exceeded, correct operation cannot be ensured.

Therefore, an object of the present invention is to provide a signal processing circuit for a sensor that utilizes a change in electrostatic capacitance to obtain a highly sensitive output without being affected by temperature.

[0007]

[Means for Solving the Problems]

(1) According to a first aspect of the present invention, an external force acts in a predetermined direction to form a first capacitive element by an electrode pair arranged so that a mutual distance increases, and conversely, The second pair of electrodes is arranged so that the distance between them decreases.
Used for the sensor which is capable of detecting the applied external force based on the difference between the capacitance change value of the first capacitance element and the capacitance change value of the second capacitance element. A signal supply source that supplies a periodic signal that periodically repeats a low level state and a high level state in the processing circuit;
A first resistance element to which a periodic signal is supplied to the end points of the
A second resistance element to which a periodic signal is supplied to the end points of the
The input end of is connected to the second end of the first resistive element,
The second input end is connected to the second end point of the second resistance element, and a logical signal indicating the phase difference between the signal applied to the first input end and the signal applied to the second input end. And a logic element for generating the first capacitance element and fixing one end of the electrode pair forming the first capacitance element and one end of the electrode pair forming the second capacitance element to a low level state. Connecting the other end of the electrode pair forming the to the second end point of the first resistance element,
The other end of the electrode pair forming the second capacitance element is connected to the second end point of the second resistance element so that the difference in the capacitance change value can be output as a logic signal, and the periodic signal has a high level. State, it does not affect the state of both input terminals of the logic element, and when the periodic signal is in the low level state,
A control element having a function of discharging each capacitance element so that both input terminals of the logic element are in a low level state is further provided.

(2) A second aspect of the present invention is the above-mentioned first aspect.
In the signal processing circuit according to this aspect, an offset capacitance element connected in parallel with the second capacitance element is further provided so that the phase difference indicated by the logic signal increases or decreases with respect to a predetermined reference level, and the external force applied is applied. The direction of is recognized based on this increase or decrease.

(3) According to a third aspect of the present invention, a capacitance element is constituted by an electrode pair arranged so that the mutual distance is changed by the action of an external force, and based on the change in the capacitance of the capacitance element. In a signal processing circuit used for a sensor capable of detecting an applied external force, a signal supply source that supplies a periodic signal that periodically repeats a low level state and a high level state, and this periodic signal is supplied to a first end point. A periodic signal is applied to the resistance element and the first input terminal, the second input terminal is connected to the second end point of the resistance element, and the signal applied to the first input terminal and the second input terminal And a logic element that generates a logic signal indicating a phase difference from the signal applied to the input terminal of
While fixing one end of the electrode pair forming the capacitive element to the low level state, the other end is connected to the second end point of the resistive element,
When the periodic signal is in the high level state, the change in the capacitance of the capacitive element can be output, and the state of the second input terminal of the logical element is not affected, and the periodic signal is in the low level state. In the case of 1), a control element having a function of discharging the capacitance element is further provided so that the second input terminal of the logic element is in a low level state.

(4) A fourth aspect of the present invention relates to the above-mentioned first aspect.
-In the signal processing circuit according to the third aspect, as the periodic signal supplied by the signal supply source, a rectangular wave signal having a duty ratio such that the period for discharging the capacitive element is shorter than the period for charging Is used.

(5) A fifth aspect of the present invention is the above-mentioned first aspect.
In the signal processing circuit according to the third aspect, the signal supply source is provided with means for adjusting the frequency or duty ratio of the periodic signal generated.

(6) The sixth aspect of the present invention is the above-mentioned first aspect.
In the signal processing circuit according to the fifth aspect, an open collector type inverter element is used as a control element, a signal inverted from the periodic signal is applied to the input terminal of this inverter element, and the output terminal of this inverter element is applied. It is connected to the input terminal of the logic element.

(7) A seventh aspect of the present invention relates to the above-mentioned first aspect.
In the signal processing circuit according to the fifth aspect, an analog switch having one end fixed to a low level state and the other end connected to the input end of the logic element is used as the control element, and the periodic signal supplied from the signal supply source is used. Is a high level state, an OFF state is performed when it is in a high level state, and a ON state is performed when it is in a low level state, and the capacitive element is discharged in an ON state.

(8) An eighth aspect of the present invention relates to the above-mentioned first aspect.
In the signal processing circuit according to the seventh aspect, a smoothing circuit that smoothes the logic signal generated by the logic element to generate a voltage signal of a predetermined level is further provided so that the phase difference can be detected as a voltage value. is there.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION §1 Basic Principle of Sensor First, the basic principle of a sensor to which the present invention is applied will be briefly described. For details of the specific structure and manufacturing method of the sensor, refer to the above-mentioned publications.

FIG. 1 is a side sectional view of a so-called "single-stick beam" one-dimensional acceleration sensor which has been conventionally used. The main components of this sensor are the upper fixed substrate 1,
Lower fixed substrate 2, intermediate body 3, elastic support body 4, acting body 5,
The upper electrode 6 and the lower electrode 7. Here, the upper fixed substrate 1 and the lower fixed substrate 2 are made of an insulator, and the intermediate body 3, the elastic support body 4, and the working body 5 are made of integrally molded metal.
The upper electrode 6 is formed on the lower surface of the upper fixed substrate 1,
A predetermined distance d is secured between the upper surface of the working body 5 and the upper surface. Here, the upper surface layer of the acting body 5 functions as an electrode facing the upper electrode 6, and a pair of electrodes (the upper surface layer of the acting body 5 and the upper electrode 6) arranged at intervals d has a capacitance value C1. One capacitive element C1 is formed. On the other hand, the lower electrode 7 is formed on the upper surface of the lower fixed substrate 2,
A predetermined distance d is ensured between the lower surface of and. Here, the lower surface layer of the acting body 5 functions as an electrode facing the lower electrode 7, and has a capacitance value C2 by a pair of electrodes (the lower surface layer of the acting body 5 and the lower electrode 7) arranged at intervals d. Thus, the second capacitive element C2 is formed.

The elastic support 4 is made of a thin metal plate and has elasticity. Therefore, when an external force acts on the action body 5, the elastic support body 4 elastically deforms and the action body 5 is displaced, and the displacement amount depends on the magnitude of the applied external force. In FIG. 2, a downward force F (for example, a force based on acceleration) acts on the action body 5,
FIG. 5 is a side sectional view showing a state in which an action body 5 is displaced downward in the drawing due to the elastic support body 4 bending. For example, acting body 5
Is moved downward by Δd in the figure, the electrode spacing of the first capacitive element C1 becomes wide as d + Δd, and the electrode spacing of the second capacitive element C2 becomes narrow as d−Δd.

Generally, the electrostatic capacitance C of a capacitive element is determined by C = εS / d, where S is the electrode area, d is the electrode spacing, and ε is the dielectric constant. Therefore, the capacitance C increases as the distance between the opposing electrodes decreases, and decreases as the distance increases. Therefore, in the state shown in FIG. 2, the capacitance value C1 of the first capacitance element C1 decreases and the capacitance value C2 of the second capacitance element C2 increases in comparison with the state shown in FIG. Therefore, based on these changes in capacitance value,
The external force acting on the acting body 5 (in this example, the force F based on acceleration) can be obtained. Specifically, the absolute value of the difference (C2-C1) between the capacitance values indicates the magnitude of the applied force, and the sign of the difference indicates the direction of the applied force.
A metal mass having a certain mass is used as the acting body 5,
If the entire sensor is installed in, for example, an elevator, acceleration is applied to the working body 5 that functions as a weight based on the lifting motion of the elevator. Due to the external force based on this acceleration, the acting body 5 is displaced, and the applied acceleration is detected as a change in the capacitance value. Thus, this sensor functions as a one-dimensional acceleration sensor.

On the other hand, FIG. 3 is a side sectional view of a conventionally proposed three-dimensional acceleration sensor. The main components of this sensor are the fixed substrate 10, the flexible substrate 20, the acting body 30,
And it is the device housing 40. FIG. 4 shows a bottom view of the fixed substrate 10. FIG. 3 shows a cross section of the fixed substrate 10 of FIG. 4 cut along the X-axis. The fixed substrate 10 is a disk-shaped substrate as shown, and the periphery thereof is fixed to the device housing 40. On this lower surface, a disk-shaped fixed electrode 1 is also provided.
1 is formed. On the other hand, FIG. 5 shows a top view of the flexible substrate 20. FIG. 3 shows a cross section of the flexible substrate 20 of FIG. 5 cut along the X-axis. The flexible substrate 20 is also a disk-shaped substrate as shown, and the periphery thereof is fixed to the device housing 40. On the upper surface, fan-shaped displacement electrodes 21-24 having the same shape and a disc-shaped displacement electrode 25 are formed as shown in the figure. The action body 30 has a columnar shape as shown by a broken line in FIG. The device housing 40 is
It has a cylindrical shape and fixedly supports the periphery of the fixed substrate 10 and the flexible substrate 20.

The fixed substrate 10 and the flexible substrate 20 are arranged in parallel with each other at a predetermined interval. Both are disc-shaped substrates, whereas the fixed substrate 10 has high rigidity and is unlikely to be bent, whereas the flexible substrate 20 has flexibility and becomes a substrate that bends when a force is applied. I have. Now, as shown in FIG. 3, an action point P is defined at the center of gravity of the acting body 30, and an XYZ three-dimensional coordinate system having this action point P as an origin is defined as shown in the figure. That is, the X axis is defined in the right direction in FIG. 3, the Z axis is defined in the upward direction, and the Y axis is defined in the direction perpendicular to the paper surface toward the back side of the paper surface. Here, assuming that the entire sensor is mounted on, for example, an automobile, acceleration is applied to the action body 30 based on the traveling of the automobile. Due to this acceleration, an external force acts on the action point P.
In the state where no force is applied to the action point P, as shown in FIG. 3, the fixed electrode 11 and the displacement electrodes 21 to 25 are kept in parallel with each other with a predetermined gap. However, for example, when a force Fx in the X-axis direction acts on the action point P, this force Fx causes a moment force with respect to the flexible substrate 20,
As shown in FIG. 6, the flexible substrate 20 is bent. Due to this bending, the distance between the displacement electrode 21 and the fixed electrode 11 increases, but the distance between the displacement electrode 23 and the fixed electrode 11 decreases. Assuming that the force applied to the point of action P is -Fx in the opposite direction, the bending in the opposite relationship to this occurs.

When the force Fx or -Fx acts in this way, a change occurs in the electrostatic capacitances of the displacement electrodes 21 and 23. By detecting this, the force Fx is detected.
Alternatively, -Fx can be detected. At this time, the distance between each of the displacement electrodes 22, 24, 25 and the fixed electrode 11 partially increases or decreases, but
It can be considered that it does not change as a whole. On the other hand, when the force Fy or −Fy in the Y direction acts, similar changes occur only in the distance between the displacement electrode 22 and the fixed electrode 11 and the distance between the displacement electrode 24 and the fixed electrode 11. Further, when the force Fz in the Z-axis direction acts, as shown in FIG. 7, the gap between the displacement electrode 25 and the fixed electrode 11 becomes small, and when the force -Fz in the opposite direction acts, this gap becomes smaller. growing. At this time, the displacement electrodes 21 to 24 and the fixed electrode 1
The distance to 1 is also small or large, but the change relating to the displacement electrode 25 is most remarkable. Therefore, the force Fz or -Fz can be detected by detecting a change in the capacitance of the displacement electrode 25.

After all, the acceleration in the X-axis direction is caused by the displacement electrodes 21,
23, the acceleration in the Y-axis direction is based on the capacitance change between the fixed electrode 11 and the displacement electrode 22, and the acceleration in the Z-axis direction is the displacement electrode 25.
The detection is performed based on the capacitance change between the fixed electrode 11 and the fixed electrode 11. That is, the displacement electrode 21 and the fixed electrode 11
And a capacitive element C having a capacitance value C1
1 is configured, and the capacitive element C3 having the capacitance value C3 is configured by the combination of the displacement electrode 23 and the fixed electrode 11, the absolute value of the difference (C3-C1) of the capacitance values is in the X-axis direction. Indicates the magnitude of acceleration, and the sign of this difference indicates the direction of acceleration. In addition, the displacement electrode 22
If the capacitive element C2 having the capacitance value C2 is configured by the combination of the fixed electrode 11 and the fixed electrode 11, and the capacitive element C4 having the capacitance value C4 is configured by the combination of the displacement electrode 24 and the fixed electrode 11, Difference in capacitance value (C2
The absolute value of −C4) indicates the magnitude of acceleration in the Y-axis direction,
The sign of this difference indicates the direction of acceleration. Further, assuming that the capacitive element C5 having the capacitance value C5 is configured by the combination of the displacement electrode 25 and the fixed electrode 11, the absolute value of the variation of the capacitance value C5 is the magnitude of the acceleration in the Z-axis direction. And the sign of this variation indicates the direction of acceleration.

Although each of the above-mentioned sensors is an acceleration sensor, it can be used as a force sensor if an external force is directly applied to the working bodies 5 and 30. Further, if the acting bodies 5 and 30 are made of a magnetic body, they can be used as a magnetic sensor for detecting a magnetic force acting on the acting bodies.

§2 Conventional Signal Processing Circuit After all, in the above-mentioned various sensors, the physical quantity is detected based on the change of the electrostatic capacity, but the detection result is displayed or recorded, Alternatively, in order to perform some control based on this detection result, it is necessary to convert the electrostatic capacitance value into a voltage value. A signal processing circuit suitable for performing such capacitance value / voltage value conversion is disclosed in Japanese Patent Application Laid-Open No. 5-346357.
This signal processing circuit suppresses the influence of temperature as much as possible,
It has an advantage that an accurate detection value can be output.

FIG. 8 is a circuit diagram showing an example of this conventional signal processing circuit. If this signal processing circuit is used, for example, two capacitive elements C1 and C2 forming the one-dimensional acceleration sensor shown in FIG. 1 will be described. Difference in capacitance value (C2-C1)
Can be taken out as a voltage value V1. At the input terminal T1 of this circuit, a signal source (not shown)
A rectangular wave signal (so-called clock signal) CLK that periodically repeats a low level state and a high level state is applied.
The inverter element 51 is connected to the subsequent stage of the input terminal T1, and an inverted signal obtained by inverting the rectangular wave signal CLK is obtained at the node N0 corresponding to the output terminal of the inverter element 51. The latter stage of the node N0 is branched into two, and the resistance elements R1 and R2 are respectively connected to the nodes. The nodes N1 and N2 corresponding to the output terminals of the resistance elements R1 and R2 are connected to the exclusive OR element (Ex- OR gate) 52 is connected. One electrode of the capacitive element C1 is connected to the output terminal of the resistive element R1, and the other electrode of the capacitive element C1 is grounded.
One of the electrodes of the capacitive element C2 is connected to the output terminal of 2, and the other electrode of the capacitive element C2 is grounded.
Here, the capacitive elements C1 and C2 are the capacitive elements C1 and C2 forming the one-dimensional acceleration sensor shown in FIG. Further, the output terminal of the exclusive OR element 52 is connected to the resistance element Rs and the capacitance element Cs via the node N3, and finally, the output terminal T2 is provided. The resistance element Rs and the capacitance element Cs are a smoothing circuit for smoothing the output signal of the exclusive OR element 52.

Next, the operation of this signal processing circuit will be described with reference to the simulated waveform chart of FIG. In this simulated waveform diagram, the input terminal T1, node N0,
Waveforms of each part of N1, N2, N3 and the output terminal T2 are shown using the same time axis. However, each waveform shown in this simulated waveform diagram is a simulated waveform for convenience of explanation of the logical operation, and is slightly different from the waveform of each part obtained in an actual circuit. For example, nodes N1 and N2
Since the waveform obtained in step 1 is a waveform that has passed through a CR delay circuit that is a combination of C1 and R1 or a combination of C2 and R2, it does not become an accurate rectangular wave as shown in the figure, and the rising and falling parts are The waveform becomes slow (so-called “blunted waveform”). In the first place, even if a rectangular wave signal is given to the input terminal T1, it does not become a perfect rectangular wave because an actual circuit has parasitic resistance and parasitic capacitance in each part. However, for convenience of explanation, it is assumed here that each of the simulated waveforms obtained in each section is a rectangular wave.

Now, assume that a rectangular wave signal having a period P1 as shown in the first stage of FIG. 9 is applied to the input terminal T1. In this case, an inverted signal as shown in the second stage of FIG. 9 is obtained at the node N0 (here,
The delay and waveform rounding due to the inverter element 51 are ignored). Then, the inverted signal of the node N0 passes through the CR delay circuit including the resistance element R1 and the capacitance element C1 and appears at the node N1. However, a time delay Δt1 peculiar to the CR delay circuit is caused. The third stage of FIG. 9 shows a signal which appears at the node N1 with a time delay of Δt1 in this way. Similarly, a signal having a time delay appears at the node N2, but here, it is assumed that the signal appearing at the node N2 has a time delay of Δt2 larger than Δt1. Fourth of FIG.
A signal appearing at the node N2 with a time delay of Δt2 is shown in the stage. Since the exclusive OR element 52 has a function of taking the exclusive OR of the signal of the node N1 and the signal of the node N2, the signal appearing at the node N3 is as shown in the fifth row of FIG. It becomes something.
This signal is a signal indicating the phase difference between the signal of the node N1 and the signal of the node N2, and has a width W1 for each cycle P1 / 2.
It becomes a rectangular wave signal in which a pulse of (W1 = Δt2−Δt1) (hatched portion in the figure) appears. The signal at the node N3 is further smoothed by a smoothing circuit including a resistance element Rs and a capacitance element Cs, and finally a signal as shown in the sixth stage of FIG. 9 is obtained at the output terminal T2. . This signal is a signal showing a constant voltage value V1, and the area of the hatched portion in the signal of this output terminal T2 is the node N
This corresponds to the area of the hatched portion in the signal of No. 3.

Now, in such a circuit, assuming that the resistance values of the resistance elements R1 and R2 are set equal, and the capacitance values of the capacitance elements C1 and C2 are also set equal, the node N1 is set. , N2 have exactly the same waveform,
The output of the exclusive OR element 52 is always in the low level state. Therefore, the output terminal T2 is always in a low level state (state of V1 = 0 in the figure). Therefore, when this circuit is applied to the acceleration sensor shown in FIG. 1, no acceleration is applied to this sensor (state shown in FIG. 1).
Then, the output voltage V1 = 0. However, for example, when a downward acceleration in the figure is applied to the action body 5 of the acceleration sensor (state shown in FIG. 2), the capacitance value C1 of the capacitance element C1 decreases and the capacitance value C2 of the capacitance element C2. Therefore, even if the resistance elements R1 and R2 have the same resistance value in the circuit shown in FIG.
The delay time of the delay circuit composed of the combination of C1 (Δt
Compared with 1), the delay time (Δt2) of the delay circuit composed of the combination of R2 and C2 becomes larger. The waveforms of the nodes N1 and N2 shown in FIG. 9 show the state when there is a difference in the delay times in this way. This delay time difference (Δt2−Δt1) is a factor that determines the pulse width W1 of the signal that appears at the node N3, and finally determines the output voltage V1 that appears at the output terminal T2. After all, if this signal processing circuit is used, the displacement amount of the working body 5 in the acceleration sensor shown in FIG. 1 can be obtained as the output voltage V1 of the output terminal T2.

The example in which the signal processing circuit is applied to the one-dimensional acceleration sensor shown in FIG. 1 has been described above, but the circuit can be similarly applied to the three-dimensional acceleration sensor shown in FIG. For example, the displacement electrode 21 and the fixed electrode 11
The capacitive element formed by the combination of
8 is used as the capacitive element C2 in FIG. 8, the output voltage V1 indicates acceleration in the X-axis direction, and the displacement electrode 24 and the fixed electrode 11 are connected to each other. 8 is used as the capacitance element C1 of FIG. 8, and the capacitance element of the combination of the displacement electrode 22 and the fixed electrode 11 is used as the capacitance element C2 of FIG. 8, the output voltage V1 becomes Y.
It shows the acceleration in the axial direction.

§3 Limitation of conventional signal processing circuit Here, a method for improving the detection sensitivity of the above-described sensor will be examined. For example, as a method for improving the detection sensitivity of the one-dimensional acceleration sensor shown in FIG. 1, the elastic support body 4 is made thin so that it can be easily bent, and the displacement d of the working body 5 becomes large even with a slight external force. There are methods such as increasing the area of the upper electrode 6 and the lower electrode 7, and increasing the capacitance value of each capacitive element as a whole. However, both of these methods structurally improve the sensor. The present invention aims to improve the detection sensitivity by improving the signal processing circuit. In other words, as shown in FIG. 2, it provides a method of efficiently converting the displacement amount ± Δd into a voltage when the working body 5 is displaced by ± Δd.

The first method for improving the sensitivity of the signal processing circuit shown in FIG. 8 is to increase the resistance values of the resistance elements R1 and R2. The delay time Δ of the waveform of the node N1 shown in FIG.
t1 is determined by the time constant of the CR delay circuit including the resistance element R1 and the capacitance element C1, and when the resistance value of the resistance element R1 increases, the delay time Δt1 naturally increases. Similarly, if the resistance value of the resistance element R2 increases, the delay time Δt2 also increases. Therefore, for example, it is assumed that the resistance values of the resistance elements R1 and R2 can be doubled to double the delay times Δt1 and Δt2. The simulated waveform diagram of FIG. 10 shows the operation at this time. The third stage in FIG. 10 shows a signal that appears at the node N1 with a time delay of 2 · Δt1, and the fourth stage shows a signal with a time delay of 2 · Δt2 at the node N2. The signal is shown. In this case, the signal appearing at the node N3 is as shown in the fifth stage of FIG. 10, and the width W2 (W2 = 2 (Δt2−
It becomes a rectangular wave signal in which a pulse (Δt1)) (hatched portion in the figure) appears. Therefore, if this is smoothed, FIG.
As shown in the sixth row of, the voltage value V2 is applied to the output terminal T2.
Is obtained. As can be seen by comparing the voltage value V1 of FIG. 9 and the voltage value V2 of FIG. 10, the latter one obtains a larger voltage, which means that the sensitivity is improved.

A second method for improving the sensitivity of the signal processing circuit shown in FIG. 8 is a rectangular wave signal CL applied to the input terminal T1.
To increase the frequency of K. This will be explained with reference to the simulated waveform diagram of FIG. In the first row of FIG. 11,
Although the rectangular wave signal CLK given to the input terminal T1 is shown, its period P2 is shorter than the period P1 of the rectangular wave signal CLK shown in FIG. As described above, even if the rectangular wave signal CLK having a high frequency is used, the basic operation of this circuit does not change, so that the nodes N1 and N2 are connected to the nodes shown in the third and fourth stages of FIG. , A waveform as shown in the fifth row of FIG. 11 is obtained at the node N3. The signal of this node N3 is still the width W1 (W1
= [Delta] t2- [Delta] t1) pulse (hatched portion in the figure), but as can be seen by comparison with the signal in the fifth stage in FIG. 9, the period in which the pulse appears is P2 / 2.
Is shortened. Therefore, the signal smoothed and appearing at the output terminal T2 has the voltage value V3 as shown in the sixth stage of FIG. 11, and the sensitivity is also improved.

By applying these two methods, the detection sensitivity of the conventional signal processing circuit can be improved to some extent, but this method has its limits. The reason will be described with reference to the waveform diagrams of FIGS. 12 and 13.
The waveform diagrams of FIG. 9, FIG. 10, and FIG. 11 used in the above description of the operation are the simulated waveform diagrams shown for the convenience of description, as described above. You cannot get a perfect rectangular waveform. In particular, the waveforms obtained at the nodes N1 and N2 are considerably distorted by passing through the CR delay circuit. That is, the delay times Δt1 and Δt2 used in the above description are simulated representations of this waveform distortion. Therefore, the actual nodes N1, N
The waveform obtained in 2 is, for example, the waveform shown by the solid line in FIG. The waveform indicated by the alternate long and short dash line is a rectangular waveform before distortion is shown for comparison. Such distortion occurs because it takes time to charge or discharge the capacitive element C in the CR delay circuit.

Now, consider the operation when such a distorted signal is input to the exclusive OR element 52.
For example, if a CMOS logic element is used as the exclusive OR element 52, a CM operating at the power supply voltage VDD.
The logical operation threshold voltage of OS is near VDD / 2. However, the threshold voltage of the actual logic element has a hysteresis characteristic, and the threshold voltage when making a transition from the low level state to the high level state and the threshold voltage when making a transition from the high level state to the low level state are different. For example, in the waveform diagram of FIG. 12, the threshold voltage when the voltage of the node N1 or N2 transits from the low level state to the high level state is the voltage h.
The threshold voltage at the time of transition from the high level state to the low level state is the voltage h2. Therefore, at the moment when the rising portion of the signal waveform of the node N1 or N2 crosses the voltage level h1, or at the moment when the falling portion crosses the voltage level h2, the exclusive OR element 52 is connected.
The logic output of will transit. Thus, FIG.
In the case of the distorted waveform shown by the solid line, a "delay" occurs at the time when the logic transition occurs compared to the ideal waveform shown by the one-dot chain line, and this "delay" is the delay used in the explanation so far. This corresponds to the times Δt1 and Δt2.

Now, even when a distorted signal as shown by the solid line in FIG. 12 is inputted, as long as this signal waveform crosses the voltage levels h1 and h2 alternately, the exclusive OR element 52 is It is possible to perform logical operations as originally designed. However, if the frequency of this signal is increased, this logical operation will eventually be hindered. The waveform indicated by the solid line in FIG. 13 is a signal waveform obtained at the node N1 or N2 when the frequency of the rectangular wave signal CLK applied to the input terminal T1 is further increased. The waveform indicated by the alternate long and short dash line shows a rectangular wave signal before distortion occurs, and it can be seen that the frequency is higher than that of the rectangular wave signal in FIG. In this way, when the frequency of the original rectangular wave signal becomes higher, the period becomes shorter,
The distorted signal cannot sufficiently follow the original rectangular wave signal. In other words, the time required for charging or discharging the capacitive element of the CR delay circuit becomes longer than the period of the original rectangular wave signal. Therefore, as shown by the solid line in FIG. 13, the distorted signal waveform transits to the voltage decreasing process before reaching the high level state even in the voltage increasing process, and conversely, in the voltage decreasing process. Even if there is, a transition is made to the voltage rising process before reaching the low level state, and a periodic signal waveform oscillating with an amplitude A1 centering on the voltage level VDD / 2 is obtained. In the example shown in FIG. 13, since the amplitude A1 is still larger than the width of the voltage levels h1 to h2, the exclusive OR element 52 can perform the logical operation without any trouble. However, when the frequency of the original rectangular wave signal is further increased, the amplitude A1 is further decreased, and eventually the signal waveform does not cross the voltage levels h1 and h2. In this case, the exclusive OR element 52 cannot operate as originally designed, and a correct output voltage cannot be obtained from this signal processing circuit.

As described above, in the conventional signal processing circuit shown in FIG. 8, even if an attempt is made to increase the frequency of the rectangular wave signal CLK in order to increase the sensitivity, normal operation will not be performed when the frequency exceeds a certain level. I will end up. Such a situation is exactly the same as another method for increasing the sensitivity, that is, a method of increasing the resistance values of the resistance elements R1 and R2. If the resistance value of the CR delay circuit is set to a large value, the waveform distortion becomes more remarkable. That is,
Taking the signal waveform shown by the solid line in FIG. 13 as an example, when the resistance value is increased, the waveform becomes more sluggish. For this reason, the amplitude A1 also becomes small, and normal operation cannot be performed. Thus, in the conventional signal processing circuit shown in FIG.
There is a limit to the improvement of detection sensitivity, and it is not possible to improve the sensitivity beyond this limit.

§4 Signal Processing Circuit of the Present Invention A feature of the present invention is that the detection sensitivity is further improved by adding new components to the conventional signal processing circuit shown in FIG. . FIG. 14 is a circuit diagram of a signal processing circuit according to an example of the present invention. This circuit is shown in FIG.
The open-collector type inverter elements 53 and 54 are further added to the conventional signal processing circuit shown in FIG.
The input end of the inverter element 53 is connected to the input terminal T1 and the output end is connected to the node N1. Also,
The input end of the inverter element 54 is connected to the input terminal T1 and the output end is connected to the node N2. The open collector type inverter element is generally supplied in the form of a TTL element (for example, 7405-TTL chip), and basically has a function as a logic inverting element that inverts an input signal. When the circuit connection shown in 14 is made and used, a specific operation suitable for the present invention can be performed. That is, when the rectangular wave signal CLK of the input terminal T1 is in the low level state (when the signal supplied to the node N0 is in the high level state), the states of the nodes N1 and N2 are not affected at all ( In other words, when the rectangular wave signal CLK of the input terminal T1 is in the high level state (the signal supplied to the node N0 is in the low level, it functions as an element having an infinite resistance value (in a so-called high impedance state)). (In the state), the nodes N1 and N2 are connected to the ground potential, and the capacitance elements C1 and C2 are instantly discharged.

Now, the operation of the circuit to which the open collector type inverter elements 53 and 54 are added will be described with reference to the waveform chart of FIG. Now, if a rectangular wave signal CLK having a period P2 as shown in the first stage of FIG. 15 is applied to the input terminal T1 of the circuit shown in FIG. 14, the node N0 has the second stage of FIG. An inverted signal as shown in is obtained. At this time, the waveform appearing at the node N1 or N2 is as shown by the solid line in the third row of FIG. That is, the rectangular wave signal CLK of the input terminal T1
In the first half period P21 in which P is in the high level state, the nodes N1 and N2 are connected to the ground potential by the operation of the open collector type inverter elements 53 and 54, so that the capacitive elements C1 and C2 are instantly discharged and the node N1, N2
Potential becomes low level. On the other hand, the rectangular wave signal CLK of the input terminal T1 transits to the low level state and the latter half period P22
When entering, the open collector type inverter element 53,
54 has no effect on the potentials of the nodes N1 and N2, and the capacitive elements C1 and C2 are charged according to the time constant of the CR delay circuit.

The point to be noted here is that the latter half period P2
The charging operation in 2 is started from the state where the capacitive elements C1 and C2 are completely discharged (the state of the first half cycle P21), and therefore efficient charging is performed. That is, as shown in FIG. 13, rather than starting the charging operation from the half-charged state near the voltage level VDD / 2, the charging operation is started from the completely discharged state of the voltage level 0 as shown in FIG. This will enable efficient and quick charging. As a result, the waveform amplitude A2 of the nodes N1 and N2 shown in FIG. 15 becomes larger than the waveform amplitude A1 of the nodes N1 and N2 shown in FIG. After all, in the signal processing circuit of the present invention shown in FIG. 14, as compared with the conventional processing circuit shown in FIG. 8, even if the frequency of the rectangular wave signal CLK is set higher, there is no problem in operation, and the detection sensitivity is improved. It becomes possible to raise further.

§5 Relationship between Duty Ratio and Sensitivity As described above, in the signal processing circuit of the present invention shown in FIG. 14, by setting the frequency of the rectangular wave signal CLK to a higher value, detection is performed as compared with the conventional circuit. It is possible to further increase the sensitivity. However, the frequency of the rectangular wave signal CLK to be used is also limited in the signal processing circuit shown in FIG. 14, and if the frequency is raised above a certain level, it will not operate normally. FIG. 16 is a waveform diagram showing the operation of the signal processing circuit shown in FIG. 14 when the frequency of the rectangular wave signal CLK is further increased. The period P3 of the rectangular wave signal CLK shown in the first stage of FIG. 16 is the same as that of the rectangular wave signal CLK shown in the first stage of FIG.
Is shorter than the period P2. Therefore, FIG.
Waveform amplitude A3 of nodes N1 and N2 shown in the second stage of No. 6
Is smaller than the waveform amplitude A2 of the nodes N1 and N2 shown in the third stage of FIG. 15, and the threshold voltage level h1 is no longer reached.

The present inventor has found that even in such a state, normal operation can be performed by changing the duty ratio of the rectangular wave signal CLK. This will be explained with reference to the waveform chart of FIG. The rectangular wave signal CLK shown in the first stage of FIG. 17 has the same period P3 as the rectangular wave signal CLK shown in the first stage of FIG. 16, but the duty ratio is different. That is, in the waveform diagram of FIG. 16, the duty ratio is 50%, whereas in the waveform diagram of FIG. 17, the duty ratio is set to about 15% (first half period P31: second half period P32 = 15: 85). . Here, the first half period P31 is a period for discharging the capacitive elements C1 and C2. This discharge is instantaneously (time sufficiently shorter than the time constant of the CR delay circuit) by the open collector type inverter elements 53 and 54, so that the first half period P
It is not necessary to set 31 to be long. On the other hand, the latter half cycle P32
Is a period for charging the capacitive elements C1 and C2, and the charging speed is determined based on the time constant of the CR delay circuit. If the latter half period P32 is set to be long, it becomes possible to secure a sufficient time for the waveform to rise, as shown in the second stage waveform diagram of FIG. As described above, in both the operation shown in FIG. 16 and the operation shown in FIG. 17, the frequency of the rectangular wave signal CLK used is exactly the same, but the waveform amplitudes of the nodes N1 and N2 in the former are A3, which hinders normal operation. Whereas, in the latter case, the waveform amplitudes of the nodes N1 and N2 in the latter are A4, and the normal operation becomes possible.

As described above, in implementing the present invention, the duty ratio of the rectangular wave signal CLK used is set to 50% or less (so that the period for discharging the capacitive element is shorter than the period for charging. It is preferable to set)
Particularly, in practice, it is preferable to set the duty ratio of the discharge period to about 10%.

As described above, in the signal processing circuit according to the present invention, the detection sensitivity can be adjusted by adjusting the frequency of the rectangular wave signal CLK to be used or the duty ratio. Therefore, by adding a means for adjusting the frequency or duty ratio of the generated rectangular wave signal CLK to the signal generation source, a signal processing circuit having a sensitivity adjusting function can be realized. FIG. 18 is a circuit diagram showing an example of a signal processing circuit having such a function, and the clock generator 61 and the duty ratio adjuster 62 constitute a signal generation source. The clock generator 61 is a device for generating a rectangular wave signal CLK having an arbitrary frequency, and the duty ratio adjuster 62 is a clock generator 61.
Is a means for adjusting the duty ratio of the rectangular wave signal CLK generated by. The operator can adjust the clock generator 61 to set the frequency of the rectangular wave signal CLK to a desired value, and adjust the duty ratio adjuster 62 to set the duty ratio to a desired value. By such adjustment operation, the detection sensitivity of this signal processing circuit can be adjusted.

§6 Signal using offset capacitive element
Processing Circuit As described above, by using the signal processing circuit according to the present invention, the absolute value of the difference between the capacitance values of the pair of capacitive elements C1 and C2 can be extracted as the voltage value.
However, the circuit shown in FIG. 14 cannot recognize the sign of the difference. For example, consider the case where the signal processing circuit shown in FIG. 14 is applied to the one-dimensional acceleration sensor shown in FIG. When no acceleration acts on this acceleration sensor, the capacitance values of the capacitive elements C1 and C2 are equal, the signals of the nodes N1 and N2 in the circuit of FIG. 14 are exactly the same, and the output voltage of the output terminal T2 is It becomes 0.
On the other hand, as shown in FIG. 2, the downward force F due to acceleration is applied.
Is applied, the capacitance value C2 of the capacitive element C2 and the capacitive element C2
The relationship with the capacitance value C1 of 1 is C2> C1, and as shown in the simulated waveform diagram of FIG. 9, the signal waveform of the node N2 causes a larger delay than the signal waveform of the node N1. Then, the voltage V1 is obtained at the output terminal T2 based on the difference in the delay times. However,
Even if the direction of acceleration is reversed, exactly the same voltage is obtained at the output terminal T2. That is, contrary to FIG. 2, when an upward force −F in the figure acts on the basis of acceleration, the magnitude relationship of the capacitance values reverses to C2 <C1, and the signal waveform of the node N1 is higher than that of the signal waveform of the node N2. Although the signal waveform causes a larger delay, the same voltage V1 is obtained at the output terminal T2 because the difference in delay time remains unchanged.

Thus, if the circuit shown in FIG. 14 is applied to the one-dimensional acceleration sensor of FIG. 1 as it is, the absolute value of the acceleration acting in the vertical direction in the figure can be obtained as the voltage V1 at the output terminal T2. Information about the direction of acceleration (up or down) cannot be obtained.

In order to deal with such a problem, FIG.
The circuit shown in FIG. 19 may be used instead of the circuit shown in FIG. This circuit is obtained by adding an offset capacitance element C0 to the circuit shown in FIG. The offset capacitance element C0 is for biasing a predetermined offset value to the voltage value obtained at the output terminal T2,
By adding this, a voltage of a predetermined reference level is output to the output terminal T2 even when no acceleration is applied. For example, in the acceleration sensor shown in FIG. 1, the capacitance values of the capacitive elements C1 and C2 are equal to each other in the state where no acceleration is applied, but in the circuit shown in FIG. Since C0 is connected in parallel, the signal waveform at the node N2 causes a larger delay than the signal waveform at the node N1, and based on this phase difference, a predetermined reference level of the output terminal T2 is output. The voltage will be output.

Here, as shown in FIG. 2, if a downward force F acts, the magnitude relationship of the capacitance values becomes C2> C1.
Therefore, the delay time of the signal waveform of the node N2 is further increased, and as a result, the phase difference between the signal waveform of the node N1 and the signal waveform of the node N2 is increased, and the voltage output to the output terminal T2 is higher than the reference level. Also grows. On the contrary, when an upward force -F acts on the figure, the magnitude relationship of the capacitance values becomes C1.
> C2, the phase difference between the signal waveform of the node N1 and the signal waveform of the node N2 becomes small, and the voltage output to the output terminal T2 becomes smaller than the reference level.
Thus, by using the signal processing circuit shown in FIG. 19, it becomes possible to recognize the direction of the applied acceleration depending on whether the output voltage obtained at the output terminal T2 is higher or lower than the reference level. The distance from the reference level allows the absolute value of the applied acceleration to be recognized.

§7 Detect the capacitance value of a single capacitive element
Circuit The signal processing circuits described so far are circuits for extracting the difference between the capacitance values of the pair of capacitive elements forming the sensor as a voltage value. Such a circuit can be applied to the one-dimensional acceleration sensor shown in FIG. 1, and also for detecting the acceleration component in the X-axis direction and the acceleration component in the Y-axis direction in the three-dimensional acceleration sensor shown in FIG. It is possible to adapt. As described above, the method of obtaining the detection value as the difference between the capacitance values of the pair of capacitive elements has an advantage that the detection value with high accuracy can be obtained. For example, even if the constituent members of the sensor expand due to the temperature rise, and the electrode spacing of the capacitive element changes, as long as the same change occurs in a pair of capacitive elements, the difference detection value shows this temperature change. No effect will appear. However, some sensors have a type that directly detects the capacitance value of a single capacitive element. For example, in order to detect the acceleration component in the Z-axis direction in the three-dimensional acceleration sensor shown in FIG. 3, it is necessary to detect the capacitance value of a single capacitive element including the combination of the fixed electrode 11 and the displacement electrode 25. The one-dimensional acceleration sensor shown in FIG. 1 can also detect acceleration based on only the change in the capacitance value of one of the capacitive elements.

The present invention is thus applicable to a sensor of the type that detects the capacitance value of a single capacitive element.
FIG. 20 is a circuit diagram showing an example of a signal processing circuit applied to such a type of sensor. The difference from the circuit shown in FIG. 14 is that there is no CR delay circuit in the path from the inverter element 51 to the node N1, and the CR delay circuit is provided only in the path from the inverter element 51 to the node N2. is there. Therefore, the open collector type inverter element 54 is also connected to the input terminal T1 and the node N2.
It is provided only between and. In this circuit, the node N
The signal waveform appearing at 1 is the inverted signal itself of the node N0, and the pulse having the width corresponding to the phase difference between the delayed signal appearing at the node N2 and the inverted signal is the exclusive OR element 5
2 is output to the node N3, and an output voltage corresponding to this width is obtained at the output terminal T2. Eventually, the output voltage obtained at the output terminal T2 corresponds to the capacitance value of the capacitive element C.

§8 CMOS analog switch was used
Embodiments In the above-described signal processing circuit according to the present invention, the open collector type inverter elements 53 and 54 are used in order to instantaneously discharge the capacitive element, but analog switches can be used instead of these. is there. FIG.
It is a circuit diagram of a signal processing circuit configured using such analog switches 71 and 72. As the analog switch, for example, an element which is commercially available as “CMOS-4066” may be used. One end of the analog switch 71 is grounded and the other end is connected to the node N1, and one end of the analog switch 72 is grounded and the other end is connected to the node N2. All the switches perform a switching operation by the rectangular wave signal CLK given to the input terminal T1, and when the rectangular wave signal CLK is in the low level state (the signal supplied to the node N0 becomes the high level, each capacitance element is in the charging state). Is ON), and when it is in a high level state (when the signal supplied to the node N0 is at a low level and each capacitance element is in a discharging state), it is in an ON state. This analog switch is OF
In the F state, the states of the nodes N1 and N2 are not affected at all, but in the ON state, the nodes N1 and N2 are not affected.
2 is connected to the ground level, and has a function of forcibly and instantaneously discharging the capacitive elements C1 and C2.

After all, the point of the present invention is that when the signal supplied to the node N0 is at a high level and each capacitance element is in the charging state, it does not affect the states of the nodes N1 and N2 and is supplied to the node N0. When the signal to be set becomes low level and each capacitance element is in the discharge state, the nodes N1 and N2 are
Is added to the conventional signal processing circuit shown in FIG. 8 so that the capacitive element is forcibly discharged so as to be in a low level state. Any means such as an open collector type inverter element, an analog switch, etc. may be added.

§9 Other Embodiments Finally, some modifications of the present invention will be described below.

(1) In the above embodiments, the exclusive OR element (Ex) is used as the logic element for obtaining the phase difference.
Although the -OR gate) 52 is used, the phase difference can be obtained by another logic element. For example, in FIG.
The signal processing circuit shown in is a logical product element (AND gate) 8
23 is a circuit configured to obtain the phase difference between both input signals by means of 1. The signal processing circuit shown in FIG. 23 is a circuit configured to obtain the phase difference between both input signals by an OR element (OR gate) 82. is there.

FIG. 24 shows a simulated waveform diagram for explaining the basic operation of the signal processing circuit (FIG. 22) using the AND element 81. In this simulated waveform diagram, T1, N0, N
The waveforms appearing at the nodes 1 and N2 are exactly the same as those shown in FIG. 9, but the waveform appearing at the node N3 is the output waveform of the logical product element 81, and the voltage V4 appearing at the output terminal T2 is The output signal of the logical product element 81 becomes a smoothed voltage. As shown in the figure, the time width of the high level state in the waveform appearing at the node N3 is the original rectangular wave signal CL.
Since the phase difference W1 is subtracted from the half cycle (P1 / 2) of K, the difference between the voltage V4 obtained at the output terminal T2 and the reference voltage level (VDD / 2) corresponds to the phase difference W1. Therefore, the larger the phase difference W1 is, the smaller the voltage V4 obtained at the output terminal T2 is. However, in the point that a signal corresponding to the phase difference W1 is finally obtained, the exclusive OR described above is used. This is the same as the embodiment using the element 52.

On the other hand, FIG. 25 shows a simulated waveform diagram for explaining the basic operation of the signal processing circuit (FIG. 23) using the OR element 82. Also in this simulated waveform diagram, T1, N
The waveforms appearing at the nodes 0, N1, N2 are exactly the same as those shown in FIG. 9, but the waveform appearing at the node N3 is the output waveform of the logical sum element 82, and the voltage V5 appearing at the output terminal T2 is , The voltage obtained by smoothing the output signal of the logical sum element 82. As shown in the figure, the time width of the high-level state in the waveform appearing at the node N3 is equal to the half cycle (P1 / 2) of the original rectangular wave signal CLK plus the phase difference W1. The value obtained by subtracting the reference voltage level (VDD / 2) from the applied voltage V5 is the phase difference W1.
However, in the point that a signal corresponding to the phase difference W1 is finally obtained, there is no difference from the embodiment using the exclusive OR element 52 described above.

As described above, according to the present invention, as long as it is a logic element capable of obtaining a logic signal indicating the phase difference between both signals,
Although any logic element may be used, it is preferable to use an exclusive OR element for the most efficient phase difference detection.

(2) In the above embodiments, the rectangular wave signal CLK applied to the input terminal T1 is inverted by the inverter element 51, and the inverted signal supplied to the node N0 is supplied to each resistance element and the capacitive element. However, the inverter element 51 does not necessarily have to be used. For example, instead of the signal processing circuit shown in FIG. 14, a signal processing circuit as shown in FIG. 26 can be used. In the circuit of FIG. 26,
The rectangular wave signal CLK given to the input terminal T1 is directly supplied to each resistance element and capacitance element. However, in this case, since the nodes N1 and N2 need to be grounded when the rectangular wave signal CLK is in the low level state, the inverter elements 91 and 92 for logic inversion are replaced by open collector type inverter elements. It is inserted before 53 and 54.

In practice, it is preferable to use the circuit shown in FIG. 27 instead of the circuit shown in FIG. In the circuit of FIG. 27, the buffer circuit 93 is inserted in the preceding stage of the node N0. An analog circuit including a resistance element and a capacitance element is connected to the subsequent stage of the node N0. The buffer circuit 93 has a function of supplying sufficient electric power for driving the analog circuit.

In short, in the present invention, a predetermined periodic signal is supplied to the node N0, and when this periodic signal is in the high level state (in other words, when the capacitive element is in the charged state), It does not affect the states of the nodes N1 and N2, and when the periodic signal is in the low level state (in other words, when the capacitive element is in the discharging state), the node N
It suffices to perform control so as to forcibly discharge each capacitance element so that 1 and N2 are in a low level state.

(3) In the above embodiments, the node N
Logic signal obtained in 3 (signal with phase difference information)
Was smoothed through a smoothing circuit composed of a resistance element Rs and a capacitance element Cs to obtain a voltage signal of a predetermined level. In other words, the time width of the high level state of the logic signal obtained at the node N3 is taken out as the analog detection value by the smoothing circuit. However, in order to quantitatively detect the time width of the logic signal obtained at the node N3, it is not always necessary to use the smoothing circuit. The logic signal obtained at the node N3 is used for PWM of the phase difference information.
It is a signal modulated by the (Pulse Width Modulation) method, and the time width can be quantitatively detected by various other methods. For example, by using a pulse having a frequency sufficiently higher than the frequency of this logic signal and counting the time width of this logic signal, the final output of this signal processing circuit is obtained as a digital detection value. It is possible.

[0061]

As described above, according to the present invention, it is possible to further improve the sensitivity of the signal processing circuit for the sensor utilizing the change in the electrostatic capacitance.

[Brief description of drawings]

FIG. 1 is a side sectional view showing a structure of a one-dimensional acceleration sensor to which the present invention is applied.

FIG. 2 is a side sectional view showing a state when a force F based on acceleration acts on the acceleration sensor shown in FIG.

FIG. 3 is a side sectional view showing a structure of a three-dimensional acceleration sensor to which the present invention is applied.

4 is a bottom view of a fixed substrate 10 of the sensor shown in FIG. FIG. 3 shows a cross section of the fixed substrate 10 of FIG. 4 cut along the X-axis.

5 is a top view of a flexible substrate 20 of the sensor shown in FIG. FIG. 3 shows a cross section of the flexible substrate 20 of FIG. 5 cut along the X-axis.

6 is a force F in the X-axis direction applied to an action point P of the sensor shown in FIG.
It is a sectional side view which shows the bending state of a sensor when x acts.

FIG. 7 is a diagram showing a force F in the Z-axis direction applied to a point of action P of the sensor shown in FIG.
It is a sectional side view which shows the bending state of a sensor when z acts.

FIG. 8 is a circuit diagram showing a conventional signal processing circuit used in the sensor shown in FIGS.

9 is a simulated waveform diagram for explaining the basic operation of the signal processing circuit shown in FIG.

10 is a simulated waveform diagram for explaining the operation when the resistance values of the resistance elements R1 and R2 are increased in the signal processing circuit shown in FIG.

11 is a simulated waveform diagram for explaining the operation of the signal processing circuit shown in FIG. 8 when the frequency of the rectangular wave signal CLK supplied to the input terminal T1 is increased.

12 is a node N in the signal processing circuit shown in FIG.
It is a waveform diagram which shows the actual signal waveform which appears in 1 and N2.

13 is a waveform diagram showing actual signal waveforms appearing at nodes N1 and N2 when the frequency of the rectangular wave signal CLK supplied to the input terminal T1 is increased in the signal processing circuit shown in FIG.

FIG. 14 is a circuit diagram of a signal processing circuit according to an embodiment of the present invention.

15 is a node N in the signal processing circuit shown in FIG.
It is a waveform diagram which shows the actual signal waveform which appears in 1 and N2.

16 is a waveform diagram showing actual signal waveforms appearing at nodes N1 and N2 when the frequency of the rectangular wave signal CLK supplied to the input terminal T1 is increased in the signal processing circuit shown in FIG.

FIG. 17 is a waveform diagram showing actual signal waveforms appearing at nodes N1 and N2 when the duty ratio of the rectangular wave signal CLK given to the input terminal T1 is lowered in the signal processing circuit shown in FIG.

FIG. 18 is a circuit diagram showing a rectangular wave signal C in the signal processing circuit shown in FIG.
It is a circuit diagram which shows the circuit which added the function which adjusts the frequency and duty ratio of LK.

19 is a circuit diagram showing a circuit in which an offset capacitance element C0 is added to the signal processing circuit shown in FIG.

FIG. 20 is a circuit diagram of a signal processing circuit according to another embodiment of the present invention, which detects a capacitance value of a single capacitive element.

21. Instead of the open collector type inverter elements 53 and 54 in the signal processing circuit shown in FIG. 14, C
6 is a circuit diagram of a signal processing circuit according to an embodiment using MOS analog switches 71 and 72. FIG.

22 is a circuit diagram showing a circuit in which the logic element in the signal processing circuit shown in FIG. 14 is replaced with a logical product element (AND gate) 81. FIG.

23 is a circuit diagram showing a circuit in which the logical element in the signal processing circuit shown in FIG. 14 is replaced with an OR element (OR gate) 82. FIG.

FIG. 24 is a simulated waveform chart for explaining the basic operation of the signal processing circuit shown in FIG. 22.

FIG. 25 is a simulated waveform diagram for explaining the basic operation of the signal processing circuit shown in FIG. 23.

FIG. 26 is a circuit diagram showing a modification of the signal processing circuit shown in FIG.

27 is a circuit diagram of a circuit in which the signal processing circuit shown in FIG. 26 is further put into practical use.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Upper fixed substrate 2 ... Lower fixed substrate 3 ... Intermediate body 4 ... Elastic support body 5 ... Working body 6 ... Upper electrode 7 ... Lower electrode 10 ... Fixed substrate 11 ... Fixed electrode 20 ... Flexible substrate 21-25 ... Displacement electrode 30 ... Agent 40 ... Device housing 51 ... Inverter element 52 ... Exclusive OR element (Ex-OR gate) 53, 54 ... Open collector type inverter element 61 ... Clock generator 62 ... Duty ratio adjuster 71, 72 ... CMOS analog switch 81 ... AND element (AND gate) 82 ... OR element (OR gate) 91, 92 ... Inverter element 93 ... Buffer element A1 to A4 ... Amplitude C, C1 to C5 of signal waveform ... Capacitance element C0 ... Offset capacitance element Cs ... Smoothing circuit capacitance element CLK ... Rectangular wave signal (clock signal) F, Fx, Fz ... Based on acceleration Force acting on the basis h1, h2 ... Threshold voltage level N0-N3 ... Circuit node P ... Point of action P1-P3 ... Period of rectangular wave signal R, R1, R2 ... Resistance element Rs ... Smoothing circuit resistance element T1 ... Input Terminal T2 ... Output terminal Δt1, Δt2 ... Delay time V1 to V5 ... Output voltage VDD ... Power supply voltage W1, W2 ... Pulse width

Claims (8)

[Claims] 1. A first capacitance element is constituted by an electrode pair arranged so that the mutual distance increases by an external force acting in a predetermined direction, and conversely, the mutual distance decreases. A second capacitance element is configured by the arranged electrode pair, and an external force that acts on the basis of the difference between the change value of the capacitance of the first capacitance element and the change value of the capacitance of the second capacitance element. A signal processing circuit used for a sensor capable of detecting a signal, comprising: a signal supply source that supplies a periodic signal that periodically repeats a low-level state and a high-level state; and a first end point that receives the periodic signal. A first resistance element, a second resistance element to which the periodic signal is supplied to a first end point, and a first input end connected to a second end point of the first resistance element; An input end is connected to a second end point of the second resistance element, A logic element that generates a logic signal indicating a phase difference between a signal applied to an input terminal and a signal applied to the second input terminal, and one end of an electrode pair forming the first capacitive element. And one end of the electrode pair forming the second capacitance element are fixed to a low level state, and the other end of the electrode pair forming the first capacitance element is connected to the second end point of the first resistance element. And the other end of the electrode pair forming the second capacitance element is connected to the second end point of the second resistance element so that the difference can be output as the logic signal. When in the high level state, it does not affect the state of both input terminals of the logic element, and when the periodic signal is in the low level state, both input terminals of the logic element are in the low level state. Control element having a function of discharging each capacitive element Signal processing circuitry for the sensor which utilizes a change in capacitance, characterized in that further provided. 2. The signal processing circuit according to claim 1, further comprising an offset capacitance element connected in parallel with the second capacitance element, wherein the phase difference indicated by the logic signal increases or decreases with respect to a predetermined reference level. A signal processing circuit for a sensor utilizing a change in capacitance, characterized in that the direction of the applied external force can be recognized based on the increase or decrease. 3. A sensor comprising a pair of electrodes arranged such that the mutual distance is changed by the action of an external force, the capacitive element being constituted, and capable of detecting the applied external force based on the change in the capacitance of the capacitive element. A signal processing circuit for use in, a signal supply source for supplying a periodic signal which periodically repeats a low level state and a high level state, a resistance element to which the periodic signal is supplied to a first end point, The periodic signal is applied to an input end of the resistor element, and the second input terminal is connected to a second end point of the resistance element,
A logic element for generating a logic signal indicating a phase difference between a signal applied to the input terminal of the capacitor and a signal applied to the second input terminal, and one end of the electrode pair forming the capacitive element The low level state is fixed, and the other end is connected to the second end point of the resistance element so that a change in the capacitance of the capacitive element can be output as the logic signal, and the periodic signal is in the high level state. The second input end of the logic element is not affected, and the second input end of the logic element is in the low level state when the periodic signal is in the low level state. A signal processing circuit for a sensor utilizing a change in capacitance, further comprising a control element having a function of discharging the capacitance element. 4. The signal processing circuit according to claim 1, wherein, as the periodic signal supplied by the signal supply source, the period for discharging the capacitive element is shorter than the period for charging. A signal processing circuit for a sensor utilizing a change in capacitance, which is characterized by using a rectangular wave signal having a different duty ratio. 5. The signal processing circuit according to claim 1, wherein the signal supply source includes means for adjusting the frequency or duty ratio of the periodic signal generated. A signal processing circuit for sensors that utilizes changes in capacitance. 6. The signal processing circuit according to claim 1, wherein an open collector type inverter element is used as a control element, and a signal inverted with respect to the periodic signal is applied to an input terminal of the inverter element. A signal processing circuit for a sensor utilizing a change in capacitance, characterized in that the output terminal of this inverter element is connected to the input terminal of a logic element. 7. The signal processing circuit according to claim 1, wherein an analog switch whose one end is fixed to a low level state and whose other end is connected to an input end of a logic element is used as the control element. , When the periodic signal supplied from the signal supply source is in the high level state, it is in the OFF state, and in the low level state, it is O
A signal processing circuit for a sensor using a change in capacitance, wherein a switching operation to be in an N state is performed and a capacitive element is discharged when in an ON state. 8. The signal processing circuit according to claim 1, further comprising a smoothing circuit that smoothes a logic signal generated by the logic element to generate a voltage signal of a predetermined level, and the phase difference is a voltage. A signal processing circuit for a sensor that utilizes a change in capacitance, which is characterized in that it can be detected as a value.