JPH0922956A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0922956A
JPH0922956A JP16950695A JP16950695A JPH0922956A JP H0922956 A JPH0922956 A JP H0922956A JP 16950695 A JP16950695 A JP 16950695A JP 16950695 A JP16950695 A JP 16950695A JP H0922956 A JPH0922956 A JP H0922956A
Authority
JP
Japan
Prior art keywords
insulating tape
semiconductor chip
semiconductor device
electrodes
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16950695A
Other languages
Japanese (ja)
Inventor
Takeshi Terasaki
健 寺崎
Makoto Kitano
誠 北野
Akihiro Yaguchi
昭弘 矢口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16950695A priority Critical patent/JPH0922956A/en
Publication of JPH0922956A publication Critical patent/JPH0922956A/en
Pending legal-status Critical Current

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  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device in which a thermal stress generated at a semiconductor chip and at an electric connection part can be reduced and in which the reliability of the electric connection part is high. SOLUTION: In a semiconductor device, wiring patterns 6 and external terminals 5 which are formed on an insulating tape 4 as well as electrodes 2 at a semiconductor chip 1 are connected electrically via metal bumps 7, the insulating tape 4 is bent one or more times, and the external terminals 5 which are formed on the insulating tape 4 are installed in a range inside the face of the semiconductor chip 1.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体素子を収納す
る半導体パッケージに係り、特に、半導体パッケージと
実装基板の接続部の高信頼性を実現し得る半導体装置に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package which houses a semiconductor element, and more particularly to a semiconductor device which can realize high reliability of a connecting portion between a semiconductor package and a mounting board.

【0002】[0002]

【従来の技術】従来のフィルムキャリア,テープキャリ
ア,TAB(Tape Automated Bonding)と称されている半
導体装置は、ポリイミドフィルムなどの絶縁性材料より
なるテープ上に、半導体素子を実装するためのデバイス
ホールを設け、表面に銅箔などの導電性材料をエッチン
グして複数のリードを形成し、デバイスホールに突出し
たリードの先端部とチップを熱圧着でボンディングし、
次いで、ポッティング技術などにより、レジンでチップ
などを被覆して、樹脂封止される構造である。
2. Description of the Related Art Conventional semiconductor devices called film carriers, tape carriers, and TABs (Tape Automated Bonding) are device holes for mounting semiconductor elements on a tape made of an insulating material such as a polyimide film. , A conductive material such as copper foil is etched on the surface to form a plurality of leads, and the tip of the lead protruding into the device hole and the chip are bonded by thermocompression bonding,
Then, a chip or the like is covered with a resin by a potting technique or the like, and is resin-sealed.

【0003】尚、テープキャリアについて述べた文献の
例は、(株)日経マグロウヒル社刊「日経マイクロデバ
イス」1986年3月号P128〜135が挙げられ
る。
An example of a document describing a tape carrier is "Nikkei Microdevice", March 1986, P128-135, published by Nikkei McGraw-Hill Co., Ltd.

【0004】また、半導体チップのボンディングパッド
上に第1導体部を設け、第1導体部の上面のみが露出さ
れるように樹脂封止され、第1導体部と基板を塊状の第
2導体部で接続する小型化された樹脂封止型半導体パッ
ケージが特開平5−120687 号公報に開示されている。
Further, the first conductor portion is provided on the bonding pad of the semiconductor chip, and is resin-sealed so that only the upper surface of the first conductor portion is exposed. A miniaturized resin-encapsulated semiconductor package that is connected by means of the above is disclosed in Japanese Patent Application Laid-Open No. 5-120687.

【0005】[0005]

【発明が解決しようとする課題】上述した従来のテープ
キャリアを用いた場合には、リードがチップの周囲に配
置されるため実装面積が広くなること、リードがはんだ
付けされることからリードピッチが制限されることなど
から、高密度実装には限界がある。
When the above-mentioned conventional tape carrier is used, the leads are arranged around the chip, so that the mounting area is wide and the leads are soldered, so that the lead pitch is small. There is a limit to high-density mounting due to limitations.

【0006】一方、特開平5−120687 号公報に開示され
ている樹脂封止型半導体パッケージは、パッケージ下面
にボールグリッドアレイ状に配置されるため、多ピン化
が可能で、実装面積も小さくて済み、高密度実装に適し
ている。しかし、実装時あるいは使用時の温度環境の変
化で半導体パッケージと基板の熱膨張係数差により塊状
の第2導体部に熱応力が発生するため、塊状の第2導体
部が熱疲労破壊を起こす問題がある。
On the other hand, the resin-encapsulated semiconductor package disclosed in Japanese Patent Laid-Open No. 5-120687 is arranged in a ball grid array on the lower surface of the package, so that it is possible to increase the number of pins and the mounting area is small. It is suitable for high density mounting. However, thermal stress is generated in the lumped second conductor portion due to the difference in thermal expansion coefficient between the semiconductor package and the substrate due to changes in the temperature environment during mounting or use, and thus the lumped second conductor portion causes thermal fatigue damage. There is.

【0007】本発明の目的は、高密度実装が可能で、電
気的接続部の熱疲労破壊に対する信頼性に優れた半導体
装置を提供することにある。
An object of the present invention is to provide a semiconductor device which can be mounted at a high density and which is excellent in reliability against thermal fatigue damage of an electrical connection portion.

【0008】[0008]

【課題を解決するための手段】上記の目的を達成するた
めに、本発明は電極を有する半導体チップと、外部端子
と配線パターンを有する絶縁テープと、半導体チップの
電極と配線パターンとの電気的接続手段から構成された
半導体装置において、前記半導体チップの電極と前記配
線パターンとを金属バンプを介して電気的に接続し、前
記絶縁テープを1回以上折り曲げ、絶縁テープに設けた
外部端子を前記半導体チップの面内の範囲に設ける。
In order to achieve the above object, the present invention provides a semiconductor chip having electrodes, an insulating tape having an external terminal and a wiring pattern, and an electrical connection between the electrodes of the semiconductor chip and the wiring pattern. In a semiconductor device composed of connecting means, the electrodes of the semiconductor chip and the wiring patterns are electrically connected via metal bumps, the insulating tape is bent one or more times, and the external terminals provided on the insulating tape are It is provided within the range of the surface of the semiconductor chip.

【0009】また上記の目的を達成するために、前記半
導体チップの電極との電気的接続を行う金属バンプを含
む前記絶縁テープの面の裏面と前記外部端子を含む前記
絶縁テープの面の裏面の間を弾性率の低い接着剤で一部
あるいは全面で接着する。
In order to achieve the above-mentioned object, the back surface of the surface of the insulating tape including metal bumps for electrically connecting to the electrodes of the semiconductor chip and the back surface of the surface of the insulating tape including the external terminals are provided. The space is bonded partially or entirely with an adhesive having a low elastic modulus.

【0010】また上記の目的を達成するために、半導体
チップの回路形成面またはその裏面を樹脂封止する。
In order to achieve the above object, the circuit forming surface of the semiconductor chip or the back surface thereof is resin-sealed.

【0011】[0011]

【作用】本発明による半導体装置は、半導体チップの面
内に実装基板との電気的接続手段である外部端子を持
ち、かつ半導体装置と実装基板との線膨張係数差に起因
する熱変形量の差を吸収する手段を有しているため、電
気的接続部の信頼性を確保したまま高密度実装を図れ
る。
The semiconductor device according to the present invention has the external terminals, which are means for electrically connecting with the mounting substrate, in the plane of the semiconductor chip, and the amount of thermal deformation caused by the difference in the linear expansion coefficient between the semiconductor device and the mounting substrate. Since the means for absorbing the difference is provided, high density mounting can be achieved while ensuring the reliability of the electrical connection portion.

【0012】[0012]

【実施例】以下、本発明の実施例を図を用いて説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

【0013】本発明の第1実施例による半導体装置の斜
視図を図1に示す。また、第1実施例の断面図を図2に
示す。
FIG. 1 is a perspective view of a semiconductor device according to the first embodiment of the present invention. A sectional view of the first embodiment is shown in FIG.

【0014】半導体チップ1の回路形成面と同じ面に電
極2が形成され、電極2以外の主表面は絶縁保護膜3で
被われている。絶縁テープ4上に外部端子5と配線パタ
ーン6を形成して、半導体チップ1上の電極2と配線パ
ターン6を金属バンプ7を介して電気的に接続する。絶
縁テープ4を2箇所で折り曲げ、外部端子5を半導体チ
ップ1の面内の範囲に設けた。
An electrode 2 is formed on the same surface as the circuit forming surface of the semiconductor chip 1, and a main surface other than the electrode 2 is covered with an insulating protective film 3. The external terminals 5 and the wiring patterns 6 are formed on the insulating tape 4, and the electrodes 2 on the semiconductor chip 1 and the wiring patterns 6 are electrically connected via the metal bumps 7. The insulating tape 4 was bent at two places, and the external terminals 5 were provided within the area of the surface of the semiconductor chip 1.

【0015】絶縁保護膜3として、プラズマシリコン窒
化膜,プラズマシリコン酸化膜やポリイミドなどが用い
られる。
As the insulating protection film 3, a plasma silicon nitride film, a plasma silicon oxide film, polyimide or the like is used.

【0016】外部端子5と配線パターン6を有する絶縁
テープ4の断面を図3に示す。
A cross section of the insulating tape 4 having the external terminals 5 and the wiring patterns 6 is shown in FIG.

【0017】絶縁テープ4上の配線パターン6は絶縁テ
ープ4上に銅箔などの金属箔を接着し、金属箔をエッチ
ングして所望の形状に作成するのが一般的であるが、導
電性ワイヤの使用やスクリーン印刷などの他の方法を用
いても良い。
The wiring pattern 6 on the insulating tape 4 is generally formed by adhering a metal foil such as a copper foil on the insulating tape 4 and etching the metal foil into a desired shape. Other methods such as the use of a screen or screen printing may be used.

【0018】折り曲げ部分の曲率半径を小さくするた
め、絶縁テープ4の折り曲げ部を他の部分より薄くする
のが好ましい。絶縁テープ4の折り曲げ部の厚さを薄く
する方法は、例えば、選択的にエッチングを行う化学的
方法やエキシマレーザ光を利用した物理的な方法などが
挙げられる。外部端子5を含む面は実装時の形状保持性
の点から絶縁テープ4を他の部分より厚くするなどの方
法により剛性を確保するのが好ましい。本実施例では図
示していないが、短絡防止のため配線パターン6の上を
絶縁膜で覆っても良い。
In order to reduce the radius of curvature of the bent portion, it is preferable to make the bent portion of the insulating tape 4 thinner than other portions. Examples of the method of reducing the thickness of the bent portion of the insulating tape 4 include a chemical method of performing selective etching and a physical method using excimer laser light. From the viewpoint of shape retention during mounting, it is preferable to secure the rigidity of the surface including the external terminals 5 by making the insulating tape 4 thicker than other portions. Although not shown in this embodiment, the wiring pattern 6 may be covered with an insulating film to prevent a short circuit.

【0019】実装基板との電気的接続は配線パターン6
上に形成された外部端子5により行う。外部端子5は半
田バンプが一般的である。半田バンプの形成法は、メッ
キ法,半田ボール法,蒸着法,半田ディップ法が挙げら
れる。また、導電性樹脂でバンプを形成してもかまわな
い。この場合、導電性樹脂を転写供給することでバンプ
を形成する。
The wiring pattern 6 is used for electrical connection with the mounting board.
The external terminal 5 formed above is used. The external terminals 5 are generally solder bumps. Examples of the solder bump forming method include a plating method, a solder ball method, a vapor deposition method, and a solder dipping method. Also, the bumps may be formed of a conductive resin. In this case, bumps are formed by transferring and supplying a conductive resin.

【0020】電極2と配線パターン6との電気的接続は
電極2上または配線パターン6またはその両方に金属バ
ンプ7を設け、熱圧着法やリフロー法により行うのが一
般的である。金属バンプの代わりに導電性樹脂を用いて
も良い。金属バンプを形成する方法として、メッキ法,
半田ボール法,蒸着法,半田ディップ法,超音波半田付
け法等が挙げられる。
The electrical connection between the electrode 2 and the wiring pattern 6 is generally performed by providing a metal bump 7 on the electrode 2 or on the wiring pattern 6 or both, and by a thermocompression bonding method or a reflow method. A conductive resin may be used instead of the metal bump. As a method of forming a metal bump, a plating method,
The solder ball method, the vapor deposition method, the solder dipping method, the ultrasonic soldering method and the like can be mentioned.

【0021】本発明の半導体装置は、実装基板に配線パ
ターン6を有する絶縁テープ4を介して電気的に接続さ
れることから、実装基板に拘束されない。そのため、外
部端子5,金属バンプ7などの電気的接続部に温度環境
の変化による熱応力の発生が生じにくく、半導体装置の
信頼性向上に役立つ。
Since the semiconductor device of the present invention is electrically connected to the mounting board via the insulating tape 4 having the wiring pattern 6, it is not restricted by the mounting board. Therefore, thermal stress is less likely to occur in the electrical connection parts such as the external terminals 5 and the metal bumps 7 due to changes in the temperature environment, which is useful for improving the reliability of the semiconductor device.

【0022】本発明の第2実施例による半導体装置の断
面図を図4に示す。
FIG. 4 is a sectional view of a semiconductor device according to the second embodiment of the present invention.

【0023】第2実施例では、外部端子5と配線パター
ン6を有する絶縁テープ4の折り曲げ後の形状保持など
を目的に、折り曲げた絶縁テープの間の一部あるいは全
部を接着剤8を用いて接着する。接着剤8は、エポキシ
系,ポリイミド系などの樹脂系接着剤が主に用いられ
る。絶縁テープのせん断変形を容易にするため、接着剤
は弾性率の低いものが好ましい。また、本実施例では外
部端子5と配線パターン6を有する絶縁テープ4を二つ
用いて電気的接続を行っていることから、半導体チップ
1と実装基板の線膨張係数に起因する熱変形量の差を絶
縁テープ4の部分のせん断変形などにより吸収する。半
導体チップの主表面が長方形の場合、絶縁テープ4の折
り曲げ部を短辺に平行に配置するのが好ましい。
In the second embodiment, an adhesive 8 is used for a part or all of the bent insulating tapes for the purpose of retaining the shape of the insulating tapes 4 having the external terminals 5 and the wiring patterns 6 after the bending. To glue. As the adhesive 8, a resin-based adhesive such as an epoxy type or a polyimide type is mainly used. In order to facilitate the shear deformation of the insulating tape, it is preferable that the adhesive has a low elastic modulus. Further, in the present embodiment, since the two external tapes 5 and the insulating tape 4 having the wiring pattern 6 are used for the electrical connection, the amount of thermal deformation caused by the linear expansion coefficient of the semiconductor chip 1 and the mounting substrate is reduced. The difference is absorbed by shear deformation of the insulating tape 4 portion. When the main surface of the semiconductor chip is rectangular, it is preferable to arrange the bent portion of the insulating tape 4 parallel to the short side.

【0024】本発明の第3実施例による半導体装置の断
面図を図5に示す。
FIG. 5 is a sectional view of a semiconductor device according to the third embodiment of the present invention.

【0025】第3実施例では、中央部に外部端子5が、
その周囲に電極2との接続部が配置された絶縁テープ4
が折り曲げられ、電極2と金属バンプ7を介して電気的
に接続されている。これにより半導体チップ1と実装基
板の線膨張係数差に起因する両者の熱変形量の差は絶縁
テープ4の変形で吸収される。取り扱い性の向上等の理
由から半導体チップ全体あるいは一部を封止樹脂9で覆
うことも可能である。封止樹脂4を構成する樹脂には、
例えば、エポキシ樹脂を用いることができ、樹脂を含む
樹脂溶液をポッティングすることにより形成することが
できる。
In the third embodiment, the external terminal 5 is provided at the center,
Insulation tape 4 around which the connection with the electrode 2 is arranged
Are bent and electrically connected to the electrodes 2 through the metal bumps 7. As a result, the difference in thermal deformation amount between the semiconductor chip 1 and the mounting substrate due to the difference in linear expansion coefficient between them is absorbed by the deformation of the insulating tape 4. It is also possible to cover the whole or a part of the semiconductor chip with the sealing resin 9 for the reason of improving the handling property. The resin that constitutes the sealing resin 4 includes
For example, an epoxy resin can be used, and it can be formed by potting a resin solution containing a resin.

【0026】[0026]

【発明の効果】本発明によれば外部端子と配線パターン
を有する絶縁テープの変形により半導体チップや電気的
接続部に発生する熱応力を大きく減少させることができ
る。
According to the present invention, the thermal stress generated in the semiconductor chip or the electrical connection portion due to the deformation of the insulating tape having the external terminal and the wiring pattern can be greatly reduced.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の第1実施例における半導体装置の斜視
図。
FIG. 1 is a perspective view of a semiconductor device according to a first embodiment of the invention.

【図2】本発明の第1実施例における半導体装置の断面
図。
FIG. 2 is a sectional view of a semiconductor device according to a first embodiment of the present invention.

【図3】本発明で用いる外部端子と配線パターンを有す
る絶縁テープの断面図。
FIG. 3 is a cross-sectional view of an insulating tape having an external terminal and a wiring pattern used in the present invention.

【図4】本発明の第2実施例における半導体装置の断面
図。
FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【図5】本発明の第2実施例における半導体装置の断面
図。
FIG. 5 is a sectional view of a semiconductor device according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1…半導体チップ、2…電極、3…絶縁保護膜、4…絶
縁テープ、5…外部端子、6…配線パターン、7…金属
バンプ、8…接着剤、9…封止樹脂。
DESCRIPTION OF SYMBOLS 1 ... Semiconductor chip, 2 ... Electrode, 3 ... Insulation protective film, 4 ... Insulation tape, 5 ... External terminal, 6 ... Wiring pattern, 7 ... Metal bump, 8 ... Adhesive, 9 ... Sealing resin.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】電極を有する半導体チップと、外部端子と
配線パターンを有する絶縁テープと、前記半導体チップ
の前記電極と前記配線パターンとの電気的接続手段から
構成された半導体装置において、前記半導体チップの前
記電極と前記配線パターンとを金属バンプを介して電気
的に接続し、前記絶縁テープを1回以上折り曲げ、絶縁
テープに設けた前記外部端子を前記半導体チップの面内
の範囲に設けたことを特徴とする半導体装置。
1. A semiconductor device comprising a semiconductor chip having electrodes, an insulating tape having an external terminal and a wiring pattern, and a means for electrically connecting the electrodes of the semiconductor chip to the wiring pattern. The electrodes and the wiring pattern are electrically connected via metal bumps, the insulating tape is bent once or more, and the external terminals provided on the insulating tape are provided within a range of the surface of the semiconductor chip. A semiconductor device characterized by:
【請求項2】請求項1において、前記半導体チップの電
極との電気的接続を行う金属バンプを含む前記絶縁テー
プの面の裏面と前記外部端子を含む前記絶縁テープの面
の裏面の間を弾性率の低い接着剤で一部あるいは全面で
接着した半導体装置。
2. The elastic member between the back surface of the surface of the insulating tape including metal bumps for electrically connecting to the electrodes of the semiconductor chip and the back surface of the surface of the insulating tape including the external terminals according to claim 1. A semiconductor device that is partially or entirely bonded with an adhesive with a low rate.
【請求項3】請求項1において、前記半導体チップの回
路形成面またはその裏面を樹脂封止した半導体装置。
3. The semiconductor device according to claim 1, wherein the circuit formation surface of the semiconductor chip or the back surface thereof is resin-sealed.
JP16950695A 1995-07-05 1995-07-05 Semiconductor device Pending JPH0922956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16950695A JPH0922956A (en) 1995-07-05 1995-07-05 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16950695A JPH0922956A (en) 1995-07-05 1995-07-05 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0922956A true JPH0922956A (en) 1997-01-21

Family

ID=15887782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16950695A Pending JPH0922956A (en) 1995-07-05 1995-07-05 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0922956A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087716A (en) * 1997-02-03 2000-07-11 Nec Corporation Semiconductor device package having a connection substrate with turned back leads and method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6087716A (en) * 1997-02-03 2000-07-11 Nec Corporation Semiconductor device package having a connection substrate with turned back leads and method thereof
KR100281667B1 (en) * 1997-02-03 2001-02-15 가네꼬 히사시 Semiconductor device mounting structure and semiconductor device mounting method

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