JPH0922944A - Designing method for semiconductor integrated circuit device and semiconductor integrated circuit device by use of this - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise the packaging rate and to prevent the generation of migration errors by determining the arrangement of cells on the basis of the power consumption of the cells and their line-direction length, and scattering cells of larger power consumption and smaller size, on the occasion of arranging the cells in the direction of lines. SOLUTION: On the occasion of arranging cells 4 in the direction of lines, power consumptions and line-direction lengths of individual cells 4 are calculated, and the arrangement of the cells 4 is determined on the basis of these calculated power consumptions and line-direction lengths, and cells 4 of larger power consumption and smaller size are scattered. In that case, on the occasion of determining the arrangement of the cells 4, arrangement inhibited regions 5 are set around cells 4 of larger power consumption. In that case, a length capable of satisfying pi/(li+Δli) <=P/L, when the length and the permissible power consumption value of the line of cells 4 arranged in the line direction are represented as L and P, and the length and power consumption of an arbitrary cell in the line of these cells 4 are represented as 1i and pi, is provided in the periphery of this arbitrary cell 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device design technology, and algorithmically determines the intervals between power supply trunk lines in a cell layout in consideration of mounting rate and electromigration in a CMOS LSI, particularly in a polycell type gate array design. The present invention also relates to a technique effectively applied to a method of designing a semiconductor integrated circuit device in which cells can be arranged so that a migration error does not occur regardless of an automatic cell arrangement method.

[0002]

2. Description of the Related Art For example, according to a study made by the inventor, a technique disclosed in Japanese Patent Laid-Open No. 3-273640 can be considered to prevent electromigration due to power concentration. In this technique, by further providing an emitter electrode on the comb-shaped wiring for emitter, the wiring resistance component is reduced, the entire emitter region is effectively operated, and electromigration due to power concentration can be prevented. .

[0003]

By the way, in the electromigration prevention technique as described above, electromigration is a phenomenon in which a wiring is broken as a result of a high-density current flowing for a long time, and this phenomenon is consumed. It is considered that cells with high power are concentrated at one location.

For example, in a CMOS LSI having a poly-cell type gate array design, when considering three cells forming a cell row sandwiched between power supply main lines, the sum of the power consumption values of these three cells is the allowable power consumption value of the cell row. It is conceivable that a migration error will occur if the value exceeds.

As a countermeasure against this, for example, in DA, a cell with a large power consumption and a cell with a small power consumption are set so that the total value of the power consumption of the cell row does not exceed the allowable power consumption value of the cell row during automatic placement. The cells are arranged in combination. In this case, the cell mounting rate is considered to be a problem.

Most CADs do not consider migration at the time of automatic placement, and when mounting an LSI using such CAD, regardless of the automatic placement method, It is necessary to find a new implementation method that can consider migration.

Therefore, an object of the present invention is to improve the mounting rate by automatically finding the interval between the power supply main lines algorithmically in the cell layout in which the mounting rate and electromigration are taken into consideration. It is an object of the present invention to provide a method for designing a semiconductor integrated circuit device in which cells can be arranged so that a migration error does not occur regardless of the method, and a highly reliable semiconductor integrated circuit device using the method.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the method for designing a semiconductor integrated circuit device of the present invention is applied to a cell layout design in consideration of the mounting rate and electromigration, and when the cells are arranged in the column direction, The power consumption of the cells and the length in the column direction are calculated, and the arrangement of the cells is determined based on the calculated power consumption and the length in the column direction.

Specifically, when deciding the cell arrangement based on the power consumption and the length in the column direction, an arrangement prohibition area is set around a cell having a large power consumption, and the arrangement prohibition area is set in the column direction. Let L be the length of the cell row arranged in the above, and let P be the allowable power consumption value, and let l _{i be} the length of any cell in this cell row.
When the power consumption is p _i , a placement prohibited area having a length Δl _i that can satisfy p _i / (l _i + Δl _i ) ≦ P / L is provided around this cell.

Further, in consideration of the entire semiconductor integrated circuit device, the disposition prohibited region of this semiconductor integrated circuit device is represented by the sum of a region set around a cell with large power consumption and a region through which a power supply main line passes. , L is the interval between the power trunk lines, W is the width of the power trunk lines, and A, B, and C are constants based on the design specifications, X _M ≧ AL + B / (L + W) + C is satisfied, and the area X _{M of the} placement prohibited area is satisfied. The power supply trunk line interval L that minimizes is determined, and the power supply trunk lines are arranged at this interval.

Further, the layout is fixed for the cells for which the layout prohibited area is provided, and the layout is improved for the other cells in consideration of the wiring length and the like.

Further, in the semiconductor integrated circuit device of the present invention, cells having large power consumption and small size are dispersed and arranged, and then the cells are wired to form a CMOSLSI having a polycell type gate array design. It is a thing.

[0015]

According to the above-described method for designing a semiconductor integrated circuit device and the semiconductor integrated circuit device using the same, the arrangement of cells is determined based on the power consumption of each cell forming the cell row and the length in the row direction. By doing so, cells with high power consumption and small size can be dispersed to prevent electromigration due to power concentration.

Specifically, by setting the placement prohibited area around the cells with high power consumption, cells with high power consumption will not be concentrated in one cell row, and the occurrence of migration error can be prevented. You can That is, by apparently enlarging the cell frame of a cell with large power consumption, the current density of the cell, which causes a migration error, can be reduced.

Further, the area of the placement prohibited area set on the chip is minimized by calculating the interval between the power supply main lines which minimizes the placement prohibited area, and the area where the cells can be placed is maximized in this case. Therefore, the cell mounting rate can be improved.

Furthermore, by improving the layout of the cells other than the cells to be provided with the layout prohibited area in consideration of the wiring length and the like, the wiring length between the cells can be shortened and a better layout is achieved. be able to.

As a result, in the cell layout design of the semiconductor integrated circuit device, the dimensions of the cell frame and the power supply trunk line interval are determined prior to the automatic placement, so that the packaging rate is improved.
Prevent the occurrence of electromigration errors,
In particular, CMOS LSI with poly-cell type gate array design
It is possible to form a highly reliable semiconductor integrated circuit device such as.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a schematic layout diagram for explaining a method of designing a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG.
Is an explanatory view showing a design principle in the present embodiment, FIG. 3 is an explanatory view showing a schematic shape, FIG. 4 is a flow chart showing a mounting procedure,
FIG. 5 is an explanatory view showing shape dimensions, FIG. 6 is an explanatory view showing a list of cell types, FIGS. 7 and 8 are explanatory views showing a relationship between a placement prohibited area and a power supply trunk line interval, and FIG. 9 is a placement prohibited of cell types. FIG. 10 is an explanatory diagram showing a region list, and FIG. 10 is an explanatory diagram showing layout improvement in consideration of the wiring length.

First, a method of designing a semiconductor integrated circuit device according to this embodiment will be described with reference to FIGS.

The semiconductor integrated circuit device of this embodiment is a CMOS LSI designed by, for example, a polycell type gate array.
As shown in FIG. 1, Al1 is used as the wiring for the power supply.
The power supply line 1 to each cell of the cell row is formed in the layer, the power supply main line 2 between the cells is formed in the Al2 layer, and the power supply main line 3 in the peripheral portion of the chip is formed in the Al3 layer. And each block is provided with one or more cells 4.

For example, in the upper right block of FIG. 1, let us consider the cells 4 forming a cell row sandwiched between the power supply main lines 2 of the Al2 layer, and the power consumption of each cell 4 is p.
_{In the case of 1} , p ₂ and p ₃ , the sum of the power consumption values of these three cells 4 becomes (p ₁ + p ₂ + p ₃ ), and when this value exceeds the power consumption allowable value (P) of the cell string. A migration error may occur.

That is, in the automatic arrangement of the cells 4, if no measures are taken against migration,
As shown in FIG. 2 (a), the cells 4 with large power consumption may be concentrated in one cell row and a migration error may occur. As a countermeasure against this point, a prohibited area 5 is set around the cell 4 with large power consumption as shown in FIG.
By temporarily enlarging the cell frame, the current density of the cell can be reduced, and the occurrence of migration error can be prevented.

Generally, when the length of the cell type i is l _i and the power consumption is p _i , p _i / l _i ≤P / L for a cell string having a length L and an allowable power consumption value P. If the relationship of (Equation 1) is satisfied, it is considered that no migration error will occur regardless of how many cells 4 of this type are gathered. Therefore, for cell type i that consumes a large amount of power and cannot satisfy the above (formula 1), p _i / (l _i + Δl _i ) ≦ P / L (formula 2) can be satisfied. By providing the placement prohibited area 5 having the length Δl _i around the cell 4, the length is apparently (l
_i + Δl _i ) cells 4, the density of power consumption per cell can be reduced, and migration errors can be avoided.

By the way, the disposition prohibited area 5 which must be set in the entire chip of the semiconductor integrated circuit device is set around the cell 4 having large power consumption, and the power supply trunk lines 2 and 3 on the chip pass through. It can be represented by the sum of the two parts.

However, since the interval between the power supply trunk lines 3 has nothing to do with the occurrence of a migration error, the disposition prohibited area due to the passage of the power supply trunk lines 3 is considered to be constant for each chip. Only the power supply trunk line 2 is considered as the placement prohibited area due to passage.

Therefore, assuming that the length of the chip in the Y direction is C _Ly , the length of the cell 4 in the Y direction is l _y , the width of the power supply trunk line 2 is W, and the number of the power supply trunk lines 2 is n, this placement prohibited area is assumed. The area X _M of 5 is

[0030]

[Equation 1]

Further, as shown in FIG. 3, between the interval L between the power supply trunk lines 2 (the length of the cell row), the number n of the power supply trunk lines 2, the width W of the power supply trunk lines 2, and the length C _Lx of the chip in the X direction. , It turns out that there is the following relationship.

C _Lx = nW + (n−1) L (Equation 4) From (Equation 2) to (Equation 4), the area X _M of the placement prohibited region 5 is
As a function of the distance L of the power mains 2, it can be expressed as follows.

[0033]

[Equation 2]

Looking at (Equation 5), P, W, C
_Lx, C _Ly, l _y is a constant which is determined by the chip to be designed. Also, since the cell composition to be arranged, that is, how many cells 4 to arrange on the chip are known in advance, p _i and l _i are also known. Therefore, (Equation 5) can be rewritten as follows.

[0035]

(Equation 3)

The area of the placement prohibited region 5 set on the chip is minimized by determining the interval L between the power supply main lines 2 that satisfies the expression (6) and minimizes the area X _M of the placement prohibited region 5. In this case, The area where the cells 4 can be arranged is maximum.

Based on the above design principle, electromigration and cell placement can be performed in consideration of the mounting rate of the cells 4.

Next, regarding the operation of this embodiment, the mounting procedure of the semiconductor integrated circuit device will be described first with reference to FIG. In this case, it is assumed that the power consumption of each cell 4 and the length in the column direction are calculated and known in advance.

First, prior to the automatic placement, the spacing L between the power supply trunk lines 2 that minimizes the area X _M of the placement prohibited area 5 is determined by the above (formula 6), and the spacing between the power supply trunk lines 2 is determined (step S6). 401). Further, in order to temporarily expand the cell frame of the cell type that is the target of the migration error, the length Δl _i that satisfies the above (Formula 2) is obtained, and the placement prohibited area 5 provided around the cell 4 is set (step 402).

The value of the apparent cell length l _i + Δl _i obtained from the interval L of the power supply main line 2 obtained in step 401 and the length Δl _i of the placement prohibited area 5 obtained in step 402 is used as a parameter. Set (step 403). As a result, the subsequent automatic placement (step 404) and automatic wiring (step 405) are performed,
After further artwork conversion (step 40
6), EB data of the pattern drawing device (step 407).

Next, an example in which the cells 4 of the cell type list shown in FIG. 6 are specifically arranged on a chip having the size shown in FIG. 5 without causing a migration error will be described.

First, the area X of the placement prohibited region 5 of (Equation 6)
It is considered that the distance L between the power supply main lines 2 that minimizes _M is obtained. In order to check what kind of graph the right side of (Equation 6) becomes as a function of L, the right side of (Equation 6) is set to f (L).
Then, the increase / decrease of this function f (L) is examined.

For example, an expression in which the right side of (Expression 6) is f (L) is defined as (Expression 7), and both sides are differentiated by L to obtain (Expression 8): f (L) = AL + B / (L + W) + C (Equation 7) f '(L) = AB / (L + W) ² (Equation 8) As a result, the increase / decrease table of f (L) is as shown in FIG. Therefore, the relationship between f (L) and L is expressed as shown in FIG. 8, and L = (B / A) ^1/2 -W (Equation 9) In this (Equation 9), f (L) is the minimum Becomes Therefore,
The area X _M of the placement prohibited region 5 in (Equation 6) is also minimized at the interval L between the power supply main lines 2 that satisfies (Equation 9).

Therefore, in the example of arranging the cell 4 of FIG. 6 in the chip of FIG. 5, (Equation 9) to (Equation 10) to (Equation 12)
When the interval L between the power supply mains 2 is calculated by substituting the numerical values in accordance with the above, it is determined to be 3.21 × 10 ² .

[0045]

(Equation 4)

B = (C _Lx −W) WC _Ly = (4928−26) × 26 × 4928 = 6.28 × 10 ⁸ (Equation 11) L = (B / A) ^1/2 −W = (6.28 × 10 ⁸ /5.22×10 ³ ) ^1/2 −26 = 3.21 × 10 ² (Equation 12) Under the interval L of the power supply trunk line 2 determined in this way Then, of the cell types in FIG. 6, the length Δ of the placement prohibited area 5 to be set for those that cannot satisfy (Equation 1).
Find l _i . According to (Equation 2), the placement prohibited area 5 to be set
The length .DELTA.l _i is expressed by Equation (13), .DELTA.l _i ≧ about ^{(3.21 × 10 2/1000)} p i -l i ··· ( Equation 13) each cell type, the power consumption value of the cell 4 By substituting p _i and the length l _i of the cell 4, the result of FIG. 9 is obtained for the length Δl _i of the placement prohibited area 5.

With the above design method, the interval L between the power supply trunk lines 2 and the length Δl _i of the placement prohibited area 5 set next to the cell 4 having a large power consumption can be determined. The interval L between the power supply main lines 2 determined in this way
If the mounting is performed according to the flow of FIG. 4 under the length Δl _i of the placement prohibited area 5, a chip in which no migration error occurs can be manufactured.

Furthermore, after the cells 4 are arranged by the above design method so that the migration error does not occur, the expression (1) cannot be satisfied as shown in FIG. For the cell 4 which has a fixed arrangement and satisfies the other (formula 1) and which is not the target of the migration error, if the arrangement is improved in consideration of the wiring length, the length of the wiring 6 should be shortened. It is possible to improve the arrangement.

Therefore, according to the method for designing a semiconductor integrated circuit device of this embodiment, the disposition prohibited region 5 is set around the cell 4 with large power consumption, and the cell frame of the cell 4 with large power consumption is apparently formed. Since the current density of the cells 4 can be reduced by enlarging the cells 4, the cells 4 with high power consumption are not concentrated in one cell row, and the occurrence of migration error can be prevented.

Further, the space between the power supply main lines 2 which minimizes the layout prohibited area 5 is obtained, and the layout prohibited area 5 is set on the chip.
The area where the cells 4 can be arranged can be maximized and the area where the cells 4 can be arranged can be maximized, so that the packaging rate of the cells 4 can be improved.

Furthermore, by improving the placement of the cells 4 other than the cells 4 in which the placement prohibited area 5 is provided, the cells 4 are placed.
The wiring length between them can be shortened, and the layout can be improved with the wiring 6 taken into consideration.

The invention made by the present inventor has been specifically described above based on the embodiments, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, the chip configuration, dimensions, cell arrangement, cell type, etc. of the semiconductor integrated circuit device are not limited to those shown in the above-mentioned embodiments, but various modifications are possible.

In the above description, the invention mainly made by the present inventor is mainly applied to the CMOS LSI,
In particular, the case where the present invention is applied to a semiconductor integrated circuit device in a polycell type gate array design has been described, but the present invention is not limited to this, and is widely applicable to a semiconductor integrated circuit device by other design methods such as standard cell design. Especially, it can be well applied to a cell arrangement in which a cell row is surrounded by a power supply main line.

[0055]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). It is possible to disperse cells having large power consumption and small size by determining the cell arrangement based on the power consumption of each cell constituting the cell row and the length in the column direction. Therefore, it is possible to prevent electromigration due to electric power concentration.

(2). It is possible to prevent the occurrence of migration error by setting the placement prohibited area around the cells with large power consumption so that the cells with large power consumption are not concentrated in one cell row. It becomes possible to do.

(3) It is possible to obtain the interval between the power supply trunk lines that minimizes the placement prohibited area algorithmically and minimize the area of the placement prohibited area set on the chip to maximize the area where cells can be placed. Therefore, the cell mounting rate can be improved.

(4). The layout of the cells other than the cells to be provided with the layout prohibited area can be improved by considering the wiring length and the like, and the wiring length between the cells can be shortened. It becomes possible to do.

(5) According to the above (1) to (4), in the cell layout design of the semiconductor integrated circuit device, the dimensions of the cell frame and the power supply trunk line interval are determined prior to the automatic layout, and the function of the automatic layout is affected. Since it can be carried out without being carried out, it is highly practical, and it is possible to improve the packaging rate and prevent the occurrence of electromigration errors. In particular, a highly reliable semiconductor integrated circuit device such as a CMOS LSI having a polycell type gate array design. Can be formed.

[Brief description of drawings]

FIG. 1 is a schematic layout diagram for explaining a method for designing a semiconductor integrated circuit device that is an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a design principle in the present embodiment.

FIG. 3 is an explanatory diagram showing a schematic shape in the present embodiment.

FIG. 4 is a flowchart showing a mounting procedure in the present embodiment.

FIG. 5 is an explanatory diagram showing a geometrical dimension in the present embodiment.

FIG. 6 is an explanatory diagram showing a cell type list in the present embodiment.

FIG. 7 is an explanatory diagram showing a relationship between a placement prohibited area and a power supply trunk line interval in the present embodiment.

FIG. 8 is an explanatory diagram showing a relationship between a placement prohibited area and a power supply trunk line interval in the present embodiment.

FIG. 9 is an explanatory diagram showing a list of cell type placement prohibited areas in the present embodiment.

FIG. 10 is an explanatory diagram showing a layout improvement in consideration of a wiring length in the present embodiment.

[Explanation of symbols]

 1 Power supply line 2, 3 Power supply main line 4 Cell 5 Placement prohibited area 6 Wiring

Claims (6)

[Claims] 1. A method of designing a semiconductor integrated circuit device, comprising: arranging a plurality of cells according to a basic circuit; and wiring between the arranged cells to form a desired integrated circuit, wherein the cells are arranged in a column direction. When arranging, the power consumption of each cell and the length in the column direction are calculated, and the arrangement of the cells is determined based on the calculated power consumption and the length in the column direction, resulting in a large power consumption. A method for designing a semiconductor integrated circuit device, characterized in that cells having small sizes are dispersed. 2. The method for designing a semiconductor integrated circuit device according to claim 1, wherein when arranging the cells based on the power consumption and the length in the column direction, a cell having a large power consumption is surrounded. A method for designing a semiconductor integrated circuit device, comprising setting a placement prohibited area. 3. The method for designing a semiconductor integrated circuit device according to claim 2, wherein when setting the placement prohibited area, the length of the cell column arranged in the column direction is L, and the allowable power consumption value is set. Let P be the length of any cell in this cell string l _i ,
When the power consumption is p _i , a placement prohibited region having a length Δl _i that can satisfy p _i / (l _i + Δl _i ) ≦ P / L is provided around this cell. Circuit device design method. 4. The method for designing a semiconductor integrated circuit device according to claim 1, 2, or 3, wherein an area where the entire layout of the semiconductor integrated circuit device is prohibited is set around the cell with large power consumption. And the area through which the power supply trunk passes, where L is the interval of the power supply trunks, W is the width of the power supply trunks, and A, B, and C are constants based on the design specifications, X _M ≧ AL + B / ( A method of designing a semiconductor integrated circuit device, characterized in that an interval L between power supply main lines that satisfies L + W) + C 2 and minimizes an area X _M of a placement prohibited region is determined, and the power supply main lines are arranged at this interval. 5. The method for designing a semiconductor integrated circuit device according to claim 1, 2, 3 or 4, wherein a layout is fixed for a cell to be provided with the layout prohibited area, and other cells are fixed. A method for designing a semiconductor integrated circuit device, characterized by performing layout improvement in consideration of wiring length and the like. 6. A semiconductor integrated circuit device using the method for designing a semiconductor integrated circuit device according to claim 1, wherein the cells with large power consumption and small size are dispersed. After arranging them, wiring between these cells is carried out, and a CMOS LSI by a polycell type gate array design
Forming a semiconductor integrated circuit device.