JPH0922897A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the supply of a high quality fine semiconductor device at lower cost and stably by improving the easiness of the coating of metal wiring, the contact characteristic of through holes and the adhesion of an interlayer film and a protecting film. SOLUTION: After opening a contact hole 20 in an interlayer insulating film 17, the interlayer insulating film 17 is plasma etched at the pressure in the neighborhood of the atmosphere and treated by smoothing, the upper edge of the hole 20 is tapered and after plasma oxidizing the surface of the substrate 11 of the hole 20 at the pressure in the neighborhood of the atmosphere, metal wiring 18 is applied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique for connecting miniaturized interlayer wiring.

[0002]

2. Description of the Related Art Conventionally, a method of manufacturing a semiconductor device including a multi-layer wiring structure is, for example, after forming a field insulating film by a selective oxidation method or the like on a silicon substrate on which P-type and N-type wells are formed. A gate oxide film, a gate electrode, a sidewall spacer made of a silicon oxide film, an impurity layer such as a source and a drain are formed in the active region, and a vapor-phase reacted silicon oxide film is formed as a first interlayer insulating film, or BP on the silicon oxide film.
SG (boron, phosphorus glass) film about 4000-1000
Laminate about 0Å and anneal at around 900 ° C to flatten. Next, in order to extract the electrode from the gate electrode and the impurity layer, the contact hole of about 0.5 to 0.8 μm, which is a contact hole, is changed by isotropic etching with an aqueous solution containing hydrofluoric acid and reactive ion etcher (RIE). After forming by combining isotropic dry etching, an alloy in which Si, Cu or the like is added to Al is sputtered and then selectively etched to form a first metal wiring. Further, in order to have a multilayer structure wiring structure, as the second interlayer insulating film, for example, Japanese Patent Publication No. 51-21753, Japanese Unexamined Patent Publication No. 63-208243, S. Wolf, SILICON PROSESSING
FOR THE VLSI ERA, RATTICE PRESS, section 4.4.9, as shown in SiH4 or TEOS [Si (OC
₂ H ₅ ) ₄ ] and the first silicon oxide film formed by thermally reacting an oxidizing gas such as O ₂ , O ₃ or N ₂ O with plasma or 5000
Vapor growth of about 7,000Å and spin coating of coated glass with siloxane polymer dissolved in an organic solvent due to the need for flattening in the miniaturized structure, and annealing at a temperature that does not interfere with the first metal wiring. . Then, a desired amount of the coated glass and the silicon oxide film is dry-etched to grow a second silicon oxide film by 1000 to 5000Å to a total interlayer insulating film thickness of 5000 to 8000Å, and then a through hole is opened and then 6000. Al of about 10000Å
The alloy is sputtered, the second metal wiring is formed by selective etching, the bonding pad portion is opened after forming the final protective insulating film.

[0003]

However, the above-mentioned conventional method of manufacturing a semiconductor device has the following problems.

First, due to the miniaturization, the aspect ratio of contact holes such as contact holes and through holes has become large, and the distribution of metal wiring has become difficult. Therefore, there is an attempt to increase the amount of isotropic etching at the time of opening the contact hole and to make the taper gentle, but the etching rate of BPSG with respect to hydrofluoric acid is large, so that the penetration occurs and the adjacent hole or gate electrode is formed. Since there are cases where holes are formed even up to the point where it is difficult to stably form connection holes, taper etching with hydrofluoric acid has become impossible. Also, RIE alone has a strong anisotropy, making it difficult to form a tapered hole, and it has become difficult to secure reliability such as wiring and migration due to miniaturization.

Although Al is used as the metal wiring material, in order to prevent the penetration of the PN junction due to the alloying of the impurity layer with Si, Al is made to contain Si in an amount of 0.2 to 2.0% in advance. However, the Si in the metal wiring grows on the substrate surface inside the contact hole at low temperature by solid phase growth at the substrate surface inside the contact hole due to the heat during sputtering or the subsequent process, and the inside of the contact is filled with high resistance Si nodules. Therefore, an increase or variation in connection resistance has been a problem. Furthermore, the first and second
The interlayer insulating film of the metal wiring is made of organically coated glass for flattening, but its surface is hydrophobic, so its adhesion to the second silicon oxide film to be laminated is poor, and stress in the subsequent process is increased. As a result, peeling or swelling occurs in the interlayer film or the protective film, which has been a problem in quality reliability.

The present invention, however, solves such a problem. By performing plasma oxidation or plasma etching of an interlayer film or a contact hole under a pressure near the atmospheric pressure, the quality around metal wiring including the interlayer insulating film is improved. It is intended to improve the characteristics and yields involved and to stably supply a fine and multifunctional semiconductor device at low cost by an easy process.

[0007]

[Means for Solving the Problems]

(Means 1) In order to solve the above problems, a semiconductor device manufacturing method according to the present invention includes a step of forming at least an insulating film on a substrate having a semiconductor element or the like formed on a desired surface, and a lower layer semiconductor on the insulating film. A step of forming a connection hole for electrical connection from the element, a step of forming a metal wiring after etching a desired amount of the insulating film with plasma generated under a pressure near atmospheric pressure by a predetermined gas. It is characterized by having.

(Means 2) Furthermore, in the method of manufacturing a semiconductor device of the present invention, at least a step of forming an insulating film on a substrate having a semiconductor element or the like formed on a desired surface, the insulating film being formed from a lower semiconductor element The method is characterized by including a step of forming a connection hole for electrical connection and a step of forming a metal wiring after performing a plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure.

(Means 3) Further, in the method of manufacturing a semiconductor device of the present invention, at least a step of forming an insulating film on a substrate having a semiconductor element or the like formed on a desired surface thereof, from the lower semiconductor element to the insulating film. Metal wiring after the process of forming a connection hole for electrical connection, the process of forming a conductive barrier layer by sputtering, and the plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure. Is provided.

(Means 4) Further, in the method for manufacturing a semiconductor device of the present invention, in the semiconductor device having a multilayer wiring structure,
At least, a step of forming a first metal wiring, a step of laminating a first silicon oxide film on a semiconductor substrate having a device surface formed on a desired surface, a step of laminating a first silicon oxide film, A step of etching a desired amount of the insulating film with plasma, a step of laminating coated glass,
The method is characterized by including a step of laminating a second silicon oxide film and a step of forming a second metal wiring after forming a connection hole for making an electrical connection to the first metal wiring.

(Means 5) Further, in the semiconductor device manufacturing method of the present invention, in a semiconductor device having a multilayer wiring structure, at least a first metal wiring is formed on a semiconductor substrate having an element region formed on a desired surface. Forming a first silicon oxide film, laminating a first silicon oxide film, laminating a coated glass, performing a plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure, and forming a second silicon oxide film. The method is characterized by including a step of laminating and a step of forming a second metal wiring after forming a connection hole for making an electrical connection in the first metal wiring.

[0012]

According to the means 1, it is possible to easily form a taper shape at the upper end of the fine connection hole, improve the distribution of the metal wiring, and improve the quality.

According to the means 2, the solid phase growth of Si from the wiring metal in the connection hole on the surface of the silicon substrate can be prevented, the increase in the connection resistance can be suppressed, and the characteristics of the semiconductor device can be improved.

According to the means 3, the barrier property to the metal wiring in the connection hole can be increased and the long-term reliability can be improved.

According to the means 4, the interlayer insulating film is easily smoothed before coating the coated glass, and the interlayer film can be further flattened.

According to the means 5, the surface of the organic coated glass can be easily made hydrophilic, and peeling or swelling of the interlayer film or the protective film can be prevented, and the reliability can be improved.

[0017]

EXAMPLE As an example of the present invention, a submicron rule silicon gate CMOS integrated circuit was manufactured.
It demonstrates based on the process in FIG.1 (a) -FIG.1 (c).
P-type and N-type wells are formed in a silicon substrate 11 having a specific resistance of 10 Ωcm, a field insulating film 12 is formed by selective oxidation, and a gate oxide film 13 and Poly are formed in the active region.
Gate electrode 1 having a polycide structure in which Si and high melting point silicide are laminated and having an immediate wall spacer 15 of a silicon oxide film
4 is formed, P and As for Nch, B and BF for Pch
LDD (Lightly Dope) in which 2 is ion-implanted
An impurity layer 16 having a d Drain) structure was formed. Next, a silicon oxide film of about 1500 Å, which was obtained by heat-reacting SiH ₄ and N ₂ O under reduced pressure, and a BPSG film, which was heat-reacted at atmospheric pressure, were laminated by vapor phase growth, and flowed in a nitrogen atmosphere at 900 ° C. to be flattened. The interlayer insulating film 17 was formed. Next, using a photoresist as a mask, CHF ₃ and CF ₄ are anisotropically etched by RIE using an inert gas such as Ar or He as a carrier gas to open a contact hole 20 of 0.5 to 0.8 μm. The photoresist was stripped.

Subsequently, CF ₄ and CHF ₃ and nitrogen gas are introduced under atmospheric pressure by using an etching apparatus shown in FIG. 3 to etch the interlayer insulating film 17 at 13.56 MHz and 80 w for about 60 seconds. Then, the upper end of the contact hole 20 was gradually tapered and smoothed as a whole. In FIG. 3, the surface of the lower electrode 33 made of Al is 100
It is formed into alumite 32 with a thickness of up to 150 μm and also serves to hold the silicon substrate 31. The opposing upper electrode 34 is made of a stainless porous material, and the surface is covered with a dielectric material 35 made of a porous ceramic.
It is connected to a high-frequency power source 36 of 50 W, and the upper gas inlet 3
A predetermined gas is introduced from No. 7 and plasma is excited between the electrodes (interval 3 to 10 mm) under a pressure near the atmosphere to perform etching or oxidation treatment. Further, a transfer machine capable of automatically carrying the silicon substrate 31 is provided, the whole is made of a quartz or stainless chamber type, and an exhaust line for an exostar is also provided. Since it can be transported to the atmosphere and has a high processing capacity, and plasma can be generated under a pressure near atmospheric pressure, there is no need to separate the atmosphere inside the reaction tube from the atmosphere, which is advantageous in terms of cost and workability, and can be used for vacuuming and purging processes. Since there are no repetitions, few particles are generated. This atmospheric pressure plasma etching is convenient because the anisotropy is weak and Si in the bottom region of the deep and narrow contact is hardly etched. Although the taper of the upper end of the hole by the plasma treatment in the vicinity of the atmospheric pressure at the time of forming the contact hole has been described as an example, the present invention can be applied to a through hole connecting Al wirings. Continuously, 600SCCM in He of 20SLM under the pressure of the atmosphere in the same device.
A gas containing 1.0% Si immediately after being left for 15 to 60 seconds in plasma excited by introducing and exciting a gas containing oxygen.
After the l-Cu alloy was sputtered, it was selectively etched to form a metal wiring 18, plasma silicon nitride was used as a protective film, and a bonding pad was opened.

The semiconductor device manufactured through such steps does not require a dangerous process such as hydrofluoric acid etching which is poor in controllability, and has good reproducibility of contact hole size and shape. Since the combined spatter condition can be made constant, metal wiring with good coverage can be provided and reliability is stable. Further, in the case of the plasma exposed to the plasma near the atmospheric pressure before the sputtering, the generation of solid-phase-grown Si nodules almost disappeared as in the conventional case, and it was possible to contribute to the reduction and stabilization of the connection resistance. However, if the oxidation time is long, the oxide film may become thicker as the temperature rises, and conversely the connection resistance may become extremely high. Therefore, the limit is about 180 seconds, and the mixing ratio of oxygen is 1.0 to 20. Up to% is appropriate.

As another embodiment, in order to further improve the barrier property of the contact, after forming a contact hole, Ti is about 200Å and TiN is about 1 as a barrier layer.
After sputtering 000Å and then leaving it in a plasma excited by a gas in which nitrogen is mixed with 75 to 100% of oxygen under a pressure of about 80 to 30 seconds for about 60 to 60 seconds, S
A semiconductor device was manufactured by using 8000Å sputter of Al-Cu alloy containing no i and selective etching to form metal wiring. However, in the case where plasma oxidation treatment in the vicinity of atmospheric pressure was not performed, the penetration of the junction was exceeded by sintering over 450 ° C. Although it started, the junction resistance did not increase even if sintering was performed at 550 ° C., and it was possible to supply a semiconductor device in which punch-through leakage did not occur.

Further, as another embodiment, for example, A
Half-micron CMO with two-layer wiring structure using l alloy
When applied to an S-LSI, a silicon substrate 21 on which semiconductor elements such as MOS transistors and resistors are formed
A contact hole is formed in the field insulating film 22 or the like in which a silicon oxide film is laminated by selective thermal oxidation or vapor phase growth, and an Al alloy containing Si or Cu is sputtered for 5000 Å, and then Cl ₂ and BCl ₃ gas is used. The sputtered film is selectively etched by the dry etcher used to remove the first metal wiring 23.
And Next, as an interlayer insulating film, first, a first silicon oxide film 24, which was obtained by subjecting TEOS and O ₂ to plasma vapor phase reaction at approximately 380 ° C. and approximately 5 to 10 torr, was approximately 5000 Å vapor phase grown. Subsequently, the methyl siloxane polymer was dissolved in an organic solvent and spin-coated, then the solvent was vaporized at 100 to 250 ° C., and then 20 to 60 at about 425 ° C. in N 2 atmosphere.
When the annealing is performed for about 10 minutes, about 700 to 1000 Å is formed on the flat portion on the first metal wiring 23 area, and the coating glass 25 is accumulated on the step portion and the groove portion according to the step amount (FIG. 2).
(A)). Next, the mixed gas of C ₂ F ₆ and He is added to 0.2
˜0.5 torr, 300-800 w of RIE are used to etch back, and at least about 150 of the coating glass 25 and the first silicon oxide film 24 on the first metal wiring 23 region are etched.
Remove 0Å. In this etch back, coated glass 2
As for the selection ratio of 5 and the silicon oxide film 24, a low etching condition is preferable from the viewpoint of ensuring flatness. Subsequently, 90 w of oxygen plasma 3 excited by a gas obtained by mixing 75 to 100% oxygen in nitrogen under a pressure near the atmosphere in the same apparatus shown in FIG.
Surface 2 of coated glass 25 when left in 0 for 30 to 60 seconds
6 becomes hydrophilic. Subsequently, a second silicon oxide film 27 having a thickness of about 3000 Å is vapor-deposited under the same conditions as the first silicon oxide film 24, and then HF (about 49% aqueous solution): N
H ₄ F (about 40% aqueous solution) = 1: 20 (20-40 ° C.)
The second silicon oxide film 27 is wet-etched by about 3000 Å using, and then RF power is 300-800 w, 100-300 m using CHF ₃ , CF ₄ and He gas.
Anisotropic selective dry etching is performed at a pressure of torr to open a through hole, and then an Al alloy is sputter grown to a thickness of 8500Å, and the laminated film is selectively etched to form a second layer.
Of the metal wiring 28 (FIG. 2B). Next, a silicon nitride film obtained by plasma-reacting SiH ₄ and NH ₃ was laminated as a protective film, and a bonding pad portion was opened to take out an electrode to the outside.

In the semiconductor device manufactured in this manner, the surface 26 of the coated glass 25 becomes hydrophilic, so that the adhesion with the second silicon oxide film 27 is improved, and voids due to side etching and post-processes occur. There was no swelling or peeling, and it was possible to reduce particles, improve yield and moisture resistance, and contribute to mass productivity and reliability improvement.

Further, in this embodiment, before spin coating the coated glass 25, CF ₄ , CHF ₃ , He and N ₂ gas were introduced by a plasma device at atmospheric pressure shown in FIG.
The surface of the first silicon oxide film 24 was smoothed by etching the first silicon oxide film 24 at 3.56 MHz, 90 w for about 90 seconds. However, in the conventional case, the coating glass is difficult to enter particularly in a place where the space of the first metal wiring 23 is narrow, and voids are generated. There was nothing that had been formed.

The etching gas used for the plasma treatment is, in addition to those shown in the examples, a Freon system such as C ₂ F ₆ or S.
F _6, NF ₃ and HBr, a mixture of inert and oxidizing gas to the halogen-based such as chlorine, and the gas in the oxidation process O ₂
In addition to the above, those mixed with N ₂ O, CO, O _3, etc. or an inert gas can be applied.

[0025]

As described above, according to the present invention, particularly in the production of integrated circuits having a multi-layered wiring structure, plasma etching or oxidation treatment is performed under a pressure near the atmosphere without using a vacuum device. This makes it possible to easily improve the coverage of metal wiring, the contact characteristics of through holes, the adhesion of interlayer films and protective films, and improve the electrical characteristics, yield and reliability, and stabilize the cost of high-quality fine semiconductor devices at low cost. It enables supply.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing a manufacturing process of a semiconductor device according to an embodiment of the invention.

FIG. 2 is a schematic cross-sectional view showing the manufacturing process of the semiconductor device according to the example of the invention.

FIG. 3 is a schematic diagram showing a plasma device according to an embodiment of the present invention.

[Explanation of symbols]

 11, 21, 31 ... Silicon substrate 12, 22 ... Field insulating film 13 ... Gate insulating film 14 ... Gate electrode 15 ... Side wall 16 ... Impurity layer 17 ... Interlayer insulating film 18 ... Metal wiring 19 ... Plasma 20 ... Contact hole 23 ... First metal wiring 24 ... First silicon oxide film 25 ... Coating glass 26 ... Coating glass surface 27・ ・ ・ Second silicon oxide film 28 ・ ・ ・ Second metal wiring 32 ・ ・ ・ Alumite 33 ・ ・ ・ Lower electrode 34 ・ ・ ・ Upper electrode 35 ・ ・ ・ Dielectric 36 ・ ・ ・ High frequency power supply 37 ・ ・・ Gas inlet

Claims (5)

[Claims] 1. A step of forming at least an insulating film on a substrate having a semiconductor element or the like formed on a desired surface, and a step of forming a connection hole in the insulating film for electrically connecting from a lower layer semiconductor element, A method of manufacturing a semiconductor device, comprising the step of forming a metal wiring after etching a desired amount of the insulating film with plasma generated under a pressure near atmospheric pressure by a predetermined gas. 2. A step of forming at least an insulating film on a substrate having a semiconductor element or the like formed on a desired surface thereof, and a step of forming a connection hole in the insulating film for electrically connecting the lower layer semiconductor element, A method for manufacturing a semiconductor device, comprising a step of forming a metal wiring after performing a plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure. 3. A step of forming at least an insulating film on a substrate having a semiconductor element or the like formed on a desired surface, and a step of forming a connection hole in the insulating film for making an electrical connection from a lower layer semiconductor element, A semiconductor device comprising: a step of forming a conductive barrier layer by sputtering; and a step of forming a metal wiring after performing a plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure. Manufacturing method. 4. A step of forming a first metal wiring, a step of laminating a first silicon oxide film on a semiconductor substrate having an element region formed on a desired surface, and a step of applying a predetermined gas under a pressure near atmospheric pressure. A step of etching a desired amount of the insulating film by the plasma generated in step 2, a step of laminating coated glass,
A semiconductor device comprising: a step of stacking a second silicon oxide film; and a step of forming a second metal wiring after forming a connection hole for electrically connecting to the first metal wiring. Manufacturing method. 5. A step of forming a first metal wiring on a semiconductor substrate having an element region formed on a desired surface, a step of laminating a first silicon oxide film, a step of laminating coated glass,
After performing a plasma treatment in which an oxidizing gas is excited under a pressure near atmospheric pressure, a step of laminating a second silicon oxide film, and after forming a connection hole for electrically connecting to the first metal wiring. A method of manufacturing a semiconductor device, comprising: forming a second metal wiring.