JPH0922888A - Abrasive, polishing method, and manufacture of semiconductor device - Google Patents
Abrasive, polishing method, and manufacture of semiconductor deviceInfo
- Publication number
- JPH0922888A JPH0922888A JP7169057A JP16905795A JPH0922888A JP H0922888 A JPH0922888 A JP H0922888A JP 7169057 A JP7169057 A JP 7169057A JP 16905795 A JP16905795 A JP 16905795A JP H0922888 A JPH0922888 A JP H0922888A
- Authority
- JP
- Japan
- Prior art keywords
- polishing
- abrasive
- semiconductor device
- layer
- abrasive grains
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005498 polishing Methods 0.000 title claims abstract description 66
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004020 conductor Substances 0.000 claims abstract description 59
- 239000006061 abrasive grain Substances 0.000 claims abstract description 34
- 239000007800 oxidant agent Substances 0.000 claims abstract description 24
- 238000004140 cleaning Methods 0.000 claims description 28
- 239000000758 substrate Substances 0.000 claims description 18
- 239000002253 acid Substances 0.000 claims description 16
- 239000003795 chemical substances by application Substances 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 4
- 239000011259 mixed solution Substances 0.000 claims description 3
- NUJOXMJBOLGQSY-UHFFFAOYSA-N manganese dioxide Chemical compound O=[Mn]=O NUJOXMJBOLGQSY-UHFFFAOYSA-N 0.000 abstract description 12
- 239000007788 liquid Substances 0.000 abstract description 5
- 238000010306 acid treatment Methods 0.000 abstract description 2
- 230000003628 erosive effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 64
- 229910052751 metal Inorganic materials 0.000 description 12
- 239000002184 metal Substances 0.000 description 12
- 238000009792 diffusion process Methods 0.000 description 10
- 239000002245 particle Substances 0.000 description 10
- 238000007517 polishing process Methods 0.000 description 10
- 238000012360 testing method Methods 0.000 description 9
- 238000011109 contamination Methods 0.000 description 7
- 238000002474 experimental method Methods 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 6
- 230000001590 oxidative effect Effects 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004744 fabric Substances 0.000 description 4
- 238000005406 washing Methods 0.000 description 4
- 239000007795 chemical reaction product Substances 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229920002803 thermoplastic polyurethane Polymers 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910018404 Al2 O3 Inorganic materials 0.000 description 1
- 235000006481 Colocasia esculenta Nutrition 0.000 description 1
- 240000004270 Colocasia esculenta var. antiquorum Species 0.000 description 1
- 229910017435 S2 In Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- GOMCKELMLXHYHH-UHFFFAOYSA-L dipotassium;phthalate Chemical compound [K+].[K+].[O-]C(=O)C1=CC=CC=C1C([O-])=O GOMCKELMLXHYHH-UHFFFAOYSA-L 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- -1 polishing method Substances 0.000 description 1
- 238000005201 scrubbing Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09G—POLISHING COMPOSITIONS; SKI WAXES
- C09G1/00—Polishing compositions
- C09G1/02—Polishing compositions containing abrasives or grinding agents
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K3/00—Materials not provided for elsewhere
- C09K3/14—Anti-slip materials; Abrasives
- C09K3/1409—Abrasive particles per se
-
- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K3/00—Materials not provided for elsewhere
- C09K3/14—Anti-slip materials; Abrasives
- C09K3/1454—Abrasive powders, suspensions and pastes for polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
- H01L21/02074—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers the processing being a planarization of conductive layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Organic Chemistry (AREA)
- Materials Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Polishing Bodies And Polishing Tools (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は一般に半導体装置の
製造に関し、特に研磨工程を含む半導体装置の製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor device manufacturing, and more particularly to a method of manufacturing a semiconductor device including a polishing step.
【0002】[0002]
【従来の技術】半導体装置、特に半導体集積回路では、
基板上に形成した絶縁層上に配線パターンを埋め込んだ
配線構造を多層積層した多層配線構造が一般に使われ
る。このような多層配線構造では第1の、下層配線構造
上に他の配線構造が形成されるため、各々の配線構造は
平坦な表面を有することが要求される。2. Description of the Related Art In semiconductor devices, especially semiconductor integrated circuits,
A multilayer wiring structure is generally used in which a wiring structure in which a wiring pattern is embedded on an insulating layer formed on a substrate is multilayered. In such a multilayer wiring structure, since another wiring structure is formed on the first lower wiring structure, each wiring structure is required to have a flat surface.
【0003】そこで、従来より、多層配線構造を形成す
る場合には、絶縁層上にコンタクトホールあるいは配線
溝を形成し、かかる絶縁層上に、前記コンタクトホール
あるいは配線溝を埋めるように金属層を堆積し、次いで
かかる金属層を、前記絶縁層表面が露出するまで研磨に
より除去し、平坦な配線構造を形成することが行われて
いる。かかる配線構造は上主面が平坦であるため、その
上に次の配線構造を容易に形成することができる。Therefore, conventionally, when a multilayer wiring structure is formed, a contact hole or a wiring groove is formed on an insulating layer, and a metal layer is formed on the insulating layer so as to fill the contact hole or the wiring groove. It has been practiced to deposit and then remove such metal layer by polishing until the surface of the insulating layer is exposed to form a flat wiring structure. Since this wiring structure has a flat upper main surface, the next wiring structure can be easily formed thereon.
【0004】以下、かかる研磨工程を含む従来の半導体
装置の製造方法を、MOSトランジスタの製造工程を例
に、図4〜8を参照しながら説明する。図4(A)を参
照するに、MOSトランジスタは例えばp型にドープさ
れたSi基板1上に、前記基板1上に形成されたフィー
ルド酸化膜1aが画成する活性領域1Aに対応して形成
される。より具体的には、MOSトランジスタは前記活
性領域1A表面に形成されたn+ 型拡散領域1bと、前
記活性領域1A表面上に、前記拡散領域1bからMOS
トランジスタのチャネル領域1dにより隔てられて形成
された別の拡散領域1cと、前記チャネル領域1d上
に、ゲート酸化膜(図示せず)を挟んで形成されたゲー
ト電極2とより構成され、前記ゲート電極2の側壁には
側壁絶縁膜2a,2bが形成される。また、前記拡散領
域1bおよび1cはそれぞれMOSトランジスタのソー
ス領域およびドレイン領域として作用する。A conventional method of manufacturing a semiconductor device including such a polishing step will be described below with reference to FIGS. Referring to FIG. 4A, a MOS transistor is formed on, for example, a p-type doped Si substrate 1 corresponding to an active region 1A defined by a field oxide film 1a formed on the substrate 1. To be done. More specifically, the MOS transistor includes an n + -type diffusion region 1b formed on the surface of the active region 1A and a MOS region formed on the surface of the active region 1A from the diffusion region 1b.
The transistor includes a diffusion region 1c formed by being separated by a channel region 1d of a transistor, and a gate electrode 2 formed on the channel region 1d with a gate oxide film (not shown) interposed therebetween. Sidewall insulating films 2a and 2b are formed on the sidewalls of the electrode 2. The diffusion regions 1b and 1c function as a source region and a drain region of a MOS transistor, respectively.
【0005】図4(A)の工程では、かかるMOSトラ
ンジスタを埋め込むように、SiO 2 よりなる層間絶縁
膜3が、例えばCVD法等により、典型的には50nm
程度の厚さに堆積される。その結果、前記ゲート電極お
よび拡散領域1b,1cは前記絶縁膜3により覆われ
る。ただし、図4(A)に示すように、絶縁膜3の表面
は前記ゲート電極2に対応した凹凸を有する。In the process of FIG. 4A, the MOS transistor
Embedded in the transistor TwoInterlayer insulation consisting of
The film 3 has a thickness of typically 50 nm by a CVD method or the like.
Deposited to a thickness of the order of magnitude. As a result, the gate electrode and
And the diffusion regions 1b and 1c are covered with the insulating film 3.
You. However, as shown in FIG. 4A, the surface of the insulating film 3
Have irregularities corresponding to the gate electrode 2.
【0006】次に、図4(B)の工程で前記絶縁膜3の
表面が一様に研磨され、その結果絶縁膜3の表面が平坦
化される。さらに図5(C)の工程で、前記絶縁膜3が
レジスト(図示せず)を使ったフォトリソグラフィによ
りパターニングされ、その結果、前記絶縁膜3中に、前
記拡散領域1bに対応して、前記領域1bの表面を露出
するコンタクトホール3aが形成される。さらに、図5
(D)の工程において、図5(C)の構造上にW,A
l,Cu等の金属あるいは合金よりなる導体層4を一様
な厚さに、例えばCVD法により堆積する。その結果、
前記導体層4は前記コンタクトホール3aを埋め、前記
コンタクトホールにおいて拡散領域1bと電気的に接触
する。先にも説明したように、図5(D)の構造では前
記導体層4は前記コンタクトホール3aを埋めるため、
導体層4表面上には前記コンタクトホール3aに対応し
て凹部4aが現れる。換言すると、前記導体層4の表面
には凹凸が生じる。Next, in the step of FIG. 4B, the surface of the insulating film 3 is uniformly polished, and as a result, the surface of the insulating film 3 is flattened. Further, in the step of FIG. 5C, the insulating film 3 is patterned by photolithography using a resist (not shown), and as a result, the insulating film 3 is formed in the insulating film 3 corresponding to the diffusion region 1b. Contact hole 3a exposing the surface of region 1b is formed. Furthermore, FIG.
In the process of (D), W and A are formed on the structure of FIG.
The conductor layer 4 made of a metal or alloy such as l or Cu is deposited to a uniform thickness by, for example, the CVD method. as a result,
The conductor layer 4 fills the contact hole 3a and makes electrical contact with the diffusion region 1b in the contact hole. As described above, in the structure of FIG. 5D, the conductor layer 4 fills the contact hole 3a,
A recess 4a appears on the surface of the conductor layer 4 corresponding to the contact hole 3a. In other words, the surface of the conductor layer 4 has irregularities.
【0007】そこで、次に図6(E)の工程において前
記導体層4が一様に研磨され、図6(E)に示すように
絶縁膜3の表面が平坦な構造が得られる。かかる導体層
4の研磨は導体層4を構成する金属に対して選択的に作
用し、絶縁層3の上主面が露出した段階で停止する。そ
の結果前記コンタクトホール3aを埋めるように、前記
拡散領域1bに接触する導体プラグ4bが形成される。
研磨による平坦化の結果、前記導体プラグ4bの上主面
は前記絶縁膜3の上主面と一致する。Then, in the next step of FIG. 6E, the conductor layer 4 is uniformly polished to obtain a structure in which the surface of the insulating film 3 is flat as shown in FIG. 6E. The polishing of the conductor layer 4 selectively acts on the metal forming the conductor layer 4, and stops when the upper main surface of the insulating layer 3 is exposed. As a result, a conductor plug 4b contacting the diffusion region 1b is formed so as to fill the contact hole 3a.
As a result of the flattening by polishing, the upper main surface of the conductor plug 4b coincides with the upper main surface of the insulating film 3.
【0008】次に、図6(F)の工程において、前記平
坦化された図6(E)の構造上にSiO2 等よりなる別
の絶縁膜5が堆積され、図7(G)の工程でフォトリソ
グラフィ法によりパターニングされ、前記導体プラグ4
bを露出する溝5aが形成される。さらに図7(H)の
工程において、W,Al,Cu等の金属あるいは合金よ
りなる別の導体層6が、前記図7(G)の構造上に堆積
され、その結果前記溝5aに対応して導体層6には凹部
6aが、図7(H)に示すように形成される。Next, in the step of FIG. 6 (F), another insulating film 5 made of SiO 2 or the like is deposited on the flattened structure of FIG. 6 (E), and then the step of FIG. 7 (G). Is patterned by photolithography with the conductive plug 4
A groove 5a exposing b is formed. Further, in the step of FIG. 7 (H), another conductor layer 6 made of a metal or alloy such as W, Al, Cu is deposited on the structure of FIG. 7 (G), so that it corresponds to the groove 5a. A recess 6a is formed in the conductor layer 6 as shown in FIG. 7 (H).
【0009】さらに、図8(I)の工程において前記導
体層6を研磨し、図8(I)に示す平坦化された構造が
得られる。図8(I)の構造では、前記絶縁膜5中の溝
を前記導体層6の一部をなす導体パターン6bが埋め
る。さらにかかる構造上に、図8(I)の工程でさらに
別の絶縁層7を堆積する。かかる構造では、絶縁層7上
に必要に応じて様々な配線パターンを形成することがで
きる。Further, the conductor layer 6 is polished in the step of FIG. 8 (I) to obtain the flattened structure shown in FIG. 8 (I). In the structure of FIG. 8I, the groove in the insulating film 5 is filled with the conductor pattern 6b forming a part of the conductor layer 6. Further, another insulating layer 7 is deposited on the structure in the step of FIG. In such a structure, various wiring patterns can be formed on the insulating layer 7 as needed.
【0010】[0010]
【発明が解決しようとする課題】上記の半導体装置の製
造工程において、図6(E)あるいは図8(I)の導体
層4あるいは6の研磨工程は、α−Al2 O3 よりなる
砥粒とH2 O2 等よりなる酸化剤との混合物よりなる研
磨剤を使い、ウレタン樹脂等の研磨布上において実行さ
れる。例えば、かかる研磨剤として、Rodel-Nitta 社よ
り商品名 MSW1000として供給されている研磨剤が一般的
に使用されている。かかる研磨工程では、酸化剤が前記
導体層を酸化させ、形成された酸化物が砥粒により研削
・除去される。In the above-described semiconductor device manufacturing process, the polishing step for the conductor layer 4 or 6 in FIG. 6 (E) or FIG. 8 (I) is performed by using abrasive grains made of α-Al 2 O 3. And an oxidizer such as H 2 O 2 and the like, and a polishing cloth made of urethane resin or the like. For example, as such an abrasive, the abrasive supplied by Rodel-Nitta under the trade name MSW1000 is generally used. In such a polishing step, the oxidizing agent oxidizes the conductor layer, and the formed oxide is ground and removed by the abrasive grains.
【0011】例えば、Wよりなる導体層を前記α−Al
2 O3 砥粒により研磨する場合、H 2 O2 によりWの酸
化物Wx Oy が形成され、かかる酸化物が前記砥粒によ
り削られる。ところが、かかる酸化剤を含んだ研磨剤を
W等の導体層の研磨に使用すると、酸化剤が前記導体層
凹部、例えば凹部4aを埋める導体層4中に、前記導体
層4の堆積時に形成される継ぎ目部ないしシーム4cに
沿って侵入してしまい、その結果、かかる酸化剤の存在
下で実行される研磨工程により、前記シーム4cが、図
9(A)に示す状態から図9(B)に示す状態へと、酸
化剤のエッチング作用により拡大してしまう問題が発生
する。その結果、導体プラグ4bの中央部には前記拡大
したシーム4cに対応して大きくまた深い凹部が形成さ
れてしまい、コンタクトホール3aにおける拡散領域1
bと導体パターン6bとの接触が不確実になってしまう
問題点が生じる。かかる導体プラグに研磨時に形成され
る凹部は、特にコンタクトホール3aの大きさが0.5
μmあるいはそれ以下の高い集積密度を有する半導体装
置および集積回路において、特に深刻な信頼性の低下を
もたらす。前記シーム4cは、大きなアスペクト比を有
するコンタクトホールを導体層の堆積により埋める際
に、コンタクトホールの側壁面からコンタクトホール中
央部に向かって成長する導体層が、前記コンタクトホー
ル中央部で衝合することにより形成され、多量の欠陥を
含んでいると考えられる。このため、前記シーム4c
は、H2 O2 等の酸化剤により、容易にエッチングを受
ける。For example, a conductor layer made of W is used as the α-Al.
TwoOThreeWhen polishing with abrasive grains, H TwoOTwoBy the acid of W
Compound WxOyAre formed, and such oxides are formed by the abrasive grains.
It is scraped. However, an abrasive containing such an oxidizing agent
When used for polishing a conductor layer such as W, the oxidant is
In the conductor layer 4 filling the recess, for example, the recess 4a, the conductor
The seam or seam 4c formed during the deposition of layer 4
The presence of such oxidants as a result
By the polishing step performed below, the seam 4c is
The state shown in FIG. 9 (A) changes to the state shown in FIG. 9 (B).
There is a problem that it expands due to the etching action of the agent
I do. As a result, the enlarged portion is formed in the central portion of the conductor plug 4b.
Large and deep recesses are formed corresponding to the seams 4c
The diffusion region 1 in the contact hole 3a.
The contact between b and the conductor pattern 6b becomes uncertain.
Problems arise. Formed on such a conductor plug during polishing
In particular, the size of the contact hole 3a is 0.5.
A semiconductor device having a high integration density of μm or less
Devices and integrated circuits suffer particularly serious reliability degradation.
Bring. The seam 4c has a large aspect ratio.
When filling the contact hole by depositing the conductor layer
In the contact hole from the side wall surface of the contact hole
The conductor layer that grows toward the center is the contact hole.
Formed by abutting in the center of the
It is considered to include. Therefore, the seam 4c
Is HTwoOTwoEasily receives etching with an oxidizing agent such as
I can.
【0012】そこで、本発明は、上記の課題を解決した
新規で有用な研磨剤、砥粒、研磨方法、および半導体装
置の製造方法を提供することを概括的目的とする。本発
明のより具体的な目的は、酸化剤を含まない研磨剤、あ
るいは酸化剤と併用する必要のない砥粒、あるいはこれ
らを使った研磨方法、あるいはこれらを使った半導体装
置の製造方法を提供することにある。Therefore, it is a general object of the present invention to provide a new and useful polishing agent, abrasive grains, polishing method, and semiconductor device manufacturing method that solve the above problems. A more specific object of the present invention is to provide an abrasive containing no oxidizing agent, or an abrasive grain that does not need to be used in combination with an oxidizing agent, a polishing method using these, or a method for manufacturing a semiconductor device using these. To do.
【0013】[0013]
【課題を解決するための手段】そこで、本発明は上記の
課題を、請求項1に記載したように、MnO2 またはM
nO2 を主成分とする砥粒を含む研磨剤により、または
請求項2に記載したように、前記砥粒の粒径は10μm
以下であることを特徴とする請求項1記載の研磨剤によ
り、または請求項3に記載したように、MnO2 よりな
る砥粒を含む研磨剤を使うことを特徴とする研磨方法に
より、または請求項4に記載したように、基板上に絶縁
層を形成する工程と;前記絶縁層に凹部を形成する工程
と;前記凹部を埋めるように、前記絶縁層上に導体層を
堆積する工程と;前記導体層を、前記絶縁層が露出する
まで研磨する研磨工程とを含む半導体装置の製造方法に
おいて、前記研磨工程を、MnO2 を砥粒として含む研
磨剤を使って実行することを特徴とする半導体装置の製
造方法により、または請求項5に記載したように、さら
に、前記基板を酸で洗浄する洗浄工程を含み、前記洗浄
工程は前記研磨工程の後で実行されることを特徴とする
請求項4記載の半導体装置の製造方法により、または請
求項6に記載したように、前記洗浄工程は、前記酸と酸
化剤との混合液により実行されることを特徴とする請求
項5記載の半導体装置の製造方法により解決する。SUMMARY OF THE INVENTION Therefore, the present invention solves the above problems by using MnO 2 or M as described in claim 1.
With an abrasive containing abrasive grains containing nO 2 as a main component, or as described in claim 2, the grain size of the abrasive grains is 10 μm.
The method according to claim 1, which is characterized by the following, or the method according to claim 3, wherein an abrasive containing abrasive grains of MnO 2 is used, or Item 4, forming an insulating layer on a substrate; forming a recess in the insulating layer; depositing a conductor layer on the insulating layer so as to fill the recess; In a method of manufacturing a semiconductor device, including a polishing step of polishing the conductor layer until the insulating layer is exposed, the polishing step is performed using an abrasive containing MnO 2 as abrasive grains. According to a method of manufacturing a semiconductor device or as described in claim 5, further comprising a cleaning step of cleaning the substrate with an acid, wherein the cleaning step is performed after the polishing step. Semi conductor according to item 4 The method for manufacturing a semiconductor device according to claim 5, wherein the cleaning step is performed by a method for manufacturing a body device, or the cleaning step is performed by using a mixed solution of the acid and the oxidizing agent. To solve.
【0014】請求項1,3,および4の発明によれば、
導体層の研磨工程おいてMnO2 を砥粒として使うこと
により、MnO2 中の酸素が導体層を構成する金属を酸
化させる。その結果、このようにして生成した反応生成
物が、反応の結果還元されたMn2 O3 あるいは未反応
のMnO2 により研削されるものと考えられる。例え
ば、導体層がWで構成されている場合、研磨時に以下の
反応 MnO2 +W→Mn2 O3 +Wx Oy が砥粒と導体層との間に生じ、生成したWx Oy が研磨
布および未反応のMnO2 により研削・除去されるもの
と考えられる。本発明では、酸化作用を行うMnO2 が
固体であり、H2 O2 等の液体状の酸化剤は研磨時に使
用されないため、酸化剤がシームに侵入することがな
い。このため、図9(B)に示したシームのような、絶
縁体中に埋め込まれた微細な導体パターン中の欠陥部が
研磨の際にエッチングされてしまう問題が生じることが
なく、信頼性の高いコンタクトを形成することができ
る。According to the inventions of claims 1, 3, and 4,
By using MnO 2 as abrasive grains in the step of polishing the conductor layer, oxygen in MnO 2 oxidizes the metal forming the conductor layer. As a result, it is considered that the reaction product thus generated is ground by Mn 2 O 3 reduced as a result of the reaction or unreacted MnO 2 . For example, when the conductor layer is composed of W, the following reaction MnO 2 + W → Mn 2 O 3 + W x O y occurs between the abrasive grains and the conductor layer during polishing, and the generated W x O y is polished. It is considered to be ground and removed by the cloth and unreacted MnO2. In the present invention, MnO 2 that performs an oxidizing action is solid, and a liquid oxidizing agent such as H 2 O 2 is not used during polishing, so that the oxidizing agent does not enter the seam. Therefore, there is no problem that a defective portion in a fine conductor pattern embedded in an insulator is etched during polishing, such as a seam shown in FIG. High contacts can be formed.
【0015】請求項2に記載の本発明の特徴によれば、
Mn砥粒の粒径を10μm以下に設定することにより、
絶縁体中に埋め込まれた微細な導体パターン中に形成さ
れる凹部の大きさを最小化することができる。請求項4
記載の本発明の特徴によれば、本発明は半導体装置の配
線パターンに使われる導体の研磨に効果的であり、半導
体装置の製造に有用である。According to a feature of the present invention described in claim 2,
By setting the grain size of the Mn abrasive grains to 10 μm or less,
The size of the recess formed in the fine conductor pattern embedded in the insulator can be minimized. Claim 4
According to the features of the present invention described, the present invention is effective for polishing a conductor used for a wiring pattern of a semiconductor device, and is useful for manufacturing a semiconductor device.
【0016】請求項5記載の本発明の特徴によれば、研
磨工程の後、基板を酸、例えばHCl、H2 SO4 HN
O3 あるいはHFで洗浄することにより、MnO2 が、
例えば反応MnO2 +2HCl+H2 O2 →MnCl2
+2H2 O+O2 、あるいはMnO2 +2HNO3 +H
2 O2 →Mn(NO3 )2 +H2 O+O2 、あるいはM
nO2 +H2 SO4 +H2 O2 →MnSO4 +2H2 O
+O2 、あるいはMnO2 +2HF+H2 O2 →MnF
2 +2H2 O+O2により酸に溶解し、その結果基板の
Mnによる汚染および残留パーティクル量を最小化する
ことができる。ただし、上記反応において、反応生成物
MnCl2 ,Mn(NO3 )2 ,MnSO4 ,MnF2
はすべて水溶性化合物である。また、上記の洗浄工程で
は液体状の酸化剤であるH2 O2 が使われるが、研磨工
程と異なり、洗浄工程におけるH2 O2 の濃度は2%以
下(研磨工程の1/25)であり、また洗浄工程は短時
間で終了するため、また砥粒による研削がなされないた
め、かかる酸化剤による導電性プラグのシームの侵食は
実質的に生じない。According to a feature of the present invention as set forth in claim 5, after the polishing step, the substrate is treated with an acid such as HCl, H 2 SO 4 HN.
By washing with O 3 or HF, MnO 2
For example, the reaction MnO 2 + 2HCl + H 2 O 2 → MnCl 2
+ 2H 2 O + O 2 or MnO 2 + 2HNO 3 + H
2 O 2 → Mn (NO 3 ) 2 + H 2 O + O 2 or M
nO 2 + H 2 SO 4 + H 2 O 2 → MnSO 4 + 2H 2 O
+ O 2 or MnO 2 + 2HF + H 2 O 2 → MnF
2 + 2H 2 O + O 2 dissolves in acid, and as a result, contamination of the substrate by Mn and the amount of residual particles can be minimized. However, in the above reaction, the reaction products MnCl 2 , Mn (NO 3 ) 2 , MnSO 4 , MnF 2
Are all water-soluble compounds. Further, although H 2 O 2 which is a liquid oxidant is used in the above cleaning process, unlike the polishing process, the concentration of H 2 O 2 in the cleaning process is 2% or less (1/25 of the polishing process). In addition, since the cleaning process is completed in a short time, and since the abrasive grains do not grind, the seam of the conductive plug is not substantially eroded by the oxidizing agent.
【0017】請求項6記載の本発明の特徴によれば、洗
浄工程で、基板洗浄を酸と酸化剤の混合液により実行す
ることにより、洗浄効率を向上させることができる。こ
のため、本発明により、高い歩留りで半導体装置を製造
することができる。研磨工程と異なり、洗浄工程で酸化
剤を使用してもコンタクトホールを埋める導体プラグが
侵食されることはほとんどない。このため、かかる洗浄
工程の結果得られた半導体装置の信頼性が低下すること
はない。According to the sixth aspect of the present invention, the cleaning efficiency can be improved by cleaning the substrate with the mixed solution of the acid and the oxidizing agent in the cleaning step. Therefore, according to the present invention, semiconductor devices can be manufactured with high yield. Unlike the polishing process, even if an oxidizer is used in the cleaning process, the conductor plug filling the contact hole is hardly eroded. Therefore, the reliability of the semiconductor device obtained as a result of the cleaning process does not deteriorate.
【0018】[0018]
【発明の実施の形態】以下、本発明を、半導体装置の製
造に適用した場合につき、実施例にもとづいて説明す
る。BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the case where the present invention is applied to the manufacture of a semiconductor device will be described based on Examples.
【0019】[0019]
【実施例】図1は本発明の一実施例を説明する図であ
る。図1を参照するに、図示の構造は本発明の研磨剤の
効果を検証するために作成した試験片を示し、Si基板
11上に約50nmの厚さでCVD法により堆積された
SiO2 層12を含む。層12には複数のコンタクトホ
ール12aおよび12bが様々な内径D1 ,D2 で形成
されており、かかるコンタクトホール12a,12bを
埋めるようにW層13が約50nmの厚さで堆積され
る。W層13は例えばCVD法により堆積され、その表
面に、前記コンタクトホール12a,12bに対応して
凹部13aが形成される。さらに、コンタクトホール1
2aあるいは12bを埋めるWプラグ中には、W層13
の堆積に伴い、シーム13bが形成される。先にも説明
したように、かかるシーム13bは、W層13がコンタ
クトホール12a,12bの側壁から内方に成長する際
に、W層13の表面が収斂・衝合することにより形成さ
れ、多数の欠陥を含んでいる。DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram for explaining an embodiment of the present invention. Referring to FIG. 1, the structure shown is a test piece prepared for verifying the effect of the polishing agent of the present invention. A SiO 2 layer deposited on a Si substrate 11 to a thickness of about 50 nm by a CVD method. Including 12. A plurality of contact holes 12a and 12b are formed in the layer 12 with various inner diameters D 1 and D 2 , and a W layer 13 is deposited to a thickness of about 50 nm so as to fill the contact holes 12a and 12b. The W layer 13 is deposited by, for example, a CVD method, and a recess 13a is formed on the surface thereof so as to correspond to the contact holes 12a and 12b. Furthermore, contact hole 1
In the W plug filling 2a or 12b, the W layer 13
The seam 13b is formed in accordance with the accumulation of. As described above, the seam 13b is formed by the surface of the W layer 13 converging and abutting when the W layer 13 grows inward from the side walls of the contact holes 12a and 12b. Including defects.
【0020】以下、かかる試験片について、本発明者が
行った実験結果を説明する。本実験では、前記試験片上
のW層13表面を、様々な粒径のMnO2 とH2 Oの混
合物よりなる研磨剤により研磨した。ただし、研磨剤中
のMnO2 の割合は約20重量%程度に設定し、研磨
は、Rodel-Nitta 社から商品名SUBA400 として供給され
るウレタン樹脂研磨布を使って行った。また、研磨の際
の圧力は200〜700g/cm2 の範囲に設定した。The results of experiments conducted by the inventor of the test piece will be described below. In this experiment, the surface of the W layer 13 on the test piece was polished with an abrasive made of a mixture of MnO 2 and H 2 O having various particle sizes. However, the proportion of MnO 2 in the polishing agent was set to about 20% by weight, and polishing was performed using a urethane resin polishing cloth supplied under the trade name SUBA400 from Rodel-Nitta. The pressure during polishing was set in the range of 200 to 700 g / cm 2 .
【0021】さらに、比較のため、従来の研磨剤を使っ
て、同一の条件で図1の試験片のW層13を研磨した。
使用した従来の研磨剤はRodel-Nitta 社の商品番号 MSW
1000であり、α−Al2 O3 よりなる砥粒とフタル酸カ
リウムとを含む。ただし、この従来例の場合には、前記
研磨剤をH2 O2 と混合して使用した。Further, for comparison, the conventional polishing agent was used to polish the W layer 13 of the test piece of FIG. 1 under the same conditions.
The conventional abrasive used is Rodel-Nitta product number MSW.
1000, including abrasive grains made of α-Al2 O3 and potassium phthalate. However, in the case of this conventional example, the abrasive was mixed with H 2 O 2 and used.
【0022】また、本実験では、研磨剤の効果の評価
は、図1の試験片においてSiO2 層12上のW層13
が完全に除去された後さらに2分間オーバーエッチング
を行い、その後で図9(B)に示すような、コンタクト
ホール3aあるいは12bを埋める導体プラグ中に形成
された凹部の深さを、試験片の断面をSEMで観察する
ことにより求めることにより行った。In this experiment, the effect of the abrasive was evaluated by the W layer 13 on the SiO2 layer 12 in the test piece of FIG.
Is completely removed, overetching is further performed for 2 minutes, and then the depth of the recess formed in the conductor plug filling the contact hole 3a or 12b as shown in FIG. It was performed by observing the cross section by SEM.
【0023】図2は、圧力を350g/cm2 に設定し、パ
ターンの無いSiO2 (図中○で示す)およびCVD法
で堆積したW層(図中●で示す)の各々の研磨速度を示
す。図2よりわかるように、粒子系が2μm以上になる
と、SiO2 の研磨速度が上昇し、Wの研磨速度が低下
しはじめる。Wの研磨速度が大きいと、研磨のスループ
ットが向上する。また、SiO2 の研磨速度は小さい方
が、ストッパ効果が高いことを意味する。従ってSiO
2 の研磨速度は小さく、Wの研磨速度は大きいほうが良
い。図2より、粒径は10μm以下が好ましいことがわ
かる。FIG. 2 shows the polishing rates of the SiO2 (shown by circles in the figure) without a pattern and the W layer (shown by ● in the figure) deposited by the CVD method with the pressure set at 350 g / cm 2 . . As can be seen from FIG. 2, when the particle size is 2 μm or more, the polishing rate of SiO 2 increases and the polishing rate of W begins to decrease. When the polishing rate of W is high, the polishing throughput is improved. Further, the smaller the polishing rate of SiO 2, the higher the stopper effect. Therefore SiO
It is better that the polishing rate of 2 is low and the polishing rate of W is high. It can be seen from FIG. 2 that the particle size is preferably 10 μm or less.
【0024】プラグの埋め込みを想定すると、粒子径が
大きい方が、プラグへ研磨剤が入り込まないためよいと
予想できる。しかし、図2に示す通り、実験にほり、粒
子径が10μm以下の方がよいことがわかった。上記の
ことから、本発明による研磨剤は、図4〜図8に説明し
た半導体装置の製造において、例えば図6(E)の工程
あるいは図8(I)の工程で導体層4あるいは6を絶縁
膜上から選択的に研磨・除去するのに有効であることが
わかる。先に説明したように、本発明によるMnO2 砥
粒を含んだ研磨剤は、粒径が10μmよりも小さい場
合、Wに対して選択的に作用するため、図6(E)の工
程において、導体層4をW層とした場合、層4下のSi
O2 層3が露出した時点で研磨は自動的に停止する。Assuming plug embedding, it can be expected that the larger the particle size, the better because the abrasive will not enter the plug. However, as shown in FIG. 2, it was found by experiment that it was better that the particle size was 10 μm or less. From the above, the abrasive according to the present invention insulates the conductor layer 4 or 6 in the step of FIG. 6E or the step of FIG. 8I in the manufacture of the semiconductor device described in FIGS. It can be seen that it is effective in selectively polishing and removing from the film. As described above, the abrasive containing MnO 2 abrasive grains according to the present invention selectively acts on W when the grain size is smaller than 10 μm, so that in the step of FIG. When the conductor layer 4 is a W layer, Si under the layer 4
Polishing is automatically stopped when the O 2 layer 3 is exposed.
【0025】一方、本発明の研磨剤を半導体装置の製造
に使う場合、研磨剤による金属汚染を回避するため、研
磨工程の後でMn砥粒を含む研磨剤を、洗浄により、基
板から実質的に完全に除去する必要がある。以下、Mn
O2 砥粒を使った研磨工程の後で実行されるかかる洗浄
工程を説明する。On the other hand, when the polishing agent of the present invention is used for manufacturing a semiconductor device, in order to avoid metal contamination by the polishing agent, the polishing agent containing Mn abrasive grains is substantially washed from the substrate after the polishing step by washing. Need to be completely removed. Below, Mn
The cleaning process performed after the polishing process using O 2 abrasive grains will be described.
【0026】本発明では残留しているMnO2 砥粒を、
様々な酸溶液中で洗浄することにより溶解し、除去す
る。本発明の発明者は、かかる洗浄処理について、以下
の様々な酸溶液を使って実験したところ、良好な結果を
得た。以下、本発明者が行った洗浄処理の実験について
説明する。In the present invention, the residual MnO 2 abrasive grains are
Dissolve and remove by washing in various acid solutions. The inventor of the present invention has conducted favorable experiments on the cleaning treatment using various acid solutions described below. Hereinafter, the experiment of the cleaning process performed by the present inventor will be described.
【0027】本実験では、前記研磨処理を行った試験片
を、 (A) HCl+H2 O2 +H2 O (1:1:48体
積比); (B) HNO3 +H2 O2 +H2 O (1:1:48
体積比); (C) H2 SO4 +H2 O2 +H2 O (1:1:4
8);および (D) HF+H2 O2 +H2 O(1:1:48) 中でそれぞれ30秒間処理し、引き続きスクラバ処理を
行った。このようにして得た試料をそれぞれ試料A,試
料B,試料C,試料Dとする。かかる試料A〜Dでは、
以下の反応 MnO2 +2HCl+H2 O2 →MnCl2 +2H2 O+O2 MnO2 +2HNO3 +H2 O2 →Mn(NO3 )2 +H2 O+O2 MnO2 +H2 SO4 +H2 O2 →MnSO4 +2H2 O+O2 MnO2 +2HF+H2 O2 →MnF2 +2H2 O+O2 がそれぞれ生じ、水溶性の反応生成物MnCl2 ,Mn
(NO3 )2 ,MnSO 4 ,MnF2 が形成されると予
想される。In this experiment, the test piece subjected to the polishing treatment was used.
(A) HCl + HTwoOTwo+ HTwoO (1: 1: 48 bodies
(Product ratio); (B) HNOThree+ HTwoOTwo+ HTwoO (1: 1: 48
Volume ratio); (C) HTwoSOFour+ HTwoOTwo+ HTwoO (1: 1: 4
8); and (D) HF + HTwoOTwo+ HTwoTreatment in O (1: 1: 48) for 30 seconds each, followed by scrubber treatment
went. The samples thus obtained are referred to as sample A and test, respectively.
Material B, Sample C, and Sample D. In such samples A to D,
The following reaction MnOTwo+ 2HCl + HTwoOTwo→ MnClTwo+ 2HTwoO + OTwo MnOTwo+ 2HNOThree+ HTwoOTwo→ Mn (NOThree)Two+ HTwoO + OTwo MnOTwo+ HTwoSOFour+ HTwoOTwo→ MnSOFour+ 2HTwoO + OTwo MnOTwo+ 2HF + HTwoOTwo→ MnFTwo+ 2HTwoO + OTwo And a water-soluble reaction product MnClTwo, Mn
(NOThree)Two, MnSO Four, MnFTwoIs formed
I am thought.
【0028】また、比較のため、前記試験片のうち、前
記MnO2 砥粒を含む研磨剤で研磨処理したものを酸処
理せずに直接スクラバ処理した試料、および前記α−A
l2O3 研磨剤(Rodel-Nitta MSW1000)で研磨したもの
を直接スクラバ処理した試料を作成し、これらの試料を
それぞれ試料Eおよび試料Fとした。For comparison, among the test pieces, a sample which was polished with an abrasive containing MnO2 abrasive grains was directly scrubbed without acid treatment, and the α-A.
Samples obtained by directly scrubbing those polished with an l 2 O 3 abrasive (Rodel-Nitta MSW1000) were designated as sample E and sample F, respectively.
【0029】このようにして得た試料A〜Fについて、
いずれも0.5%の濃度のHFに20秒間浸漬した後、
金属汚染および残留粒子を評価した。その結果を以下の
表に示す。With respect to the samples A to F thus obtained,
After soaking in HF with a concentration of 0.5% for 20 seconds,
Metal contamination and residual particles were evaluated. The results are shown in the table below.
【0030】[0030]
【表1】 [Table 1]
【0031】このように、本発明の洗浄工程を適用した
試料A〜Dでは、いずれもMnによる汚染は無視できる
程度であり、また残留粒子数も従来のもの(試料F)よ
りも少ないことがわかる。また、前記試料A〜Dでは、
酸洗浄を省略したもの(試料E)に対してもMnによる
金属汚染が減少していることがわかる。この結果は、洗
浄により前記化学式で示した反応が生じ、残留MnO2
が溶解されることを示している。As described above, in each of the samples A to D to which the cleaning process of the present invention is applied, the contamination by Mn is negligible, and the number of residual particles is smaller than that of the conventional sample (sample F). Recognize. Further, in the samples A to D,
It can be seen that the metal contamination due to Mn is reduced even in the case where the acid cleaning is omitted (Sample E). This result indicates that the reaction represented by the above chemical formula occurs due to the washing and residual MnO 2
Are dissolved.
【0032】以上の研磨工程において、MnO2 を砥粒
とする本発明の研磨剤が有効な被研磨物は、前記W層に
限定されるものではなく、AlやCu等の金属あるいは
合金も含まれる。図3は、本発明による研磨工程を含ん
だ半導体装置の製造工程を示すフローチャートである。In the above polishing step, the object to be polished, in which the polishing agent of the present invention containing MnO 2 as abrasive grains is effective, is not limited to the W layer, but includes metals or alloys such as Al and Cu. Be done. FIG. 3 is a flowchart showing a manufacturing process of a semiconductor device including a polishing process according to the present invention.
【0033】図3を参照するに、工程S1において基板
あるいはウェハ上にデバイス構造が形成され、工程S2
において、かかるデバイス構造を覆うように絶縁膜が堆
積される。この絶縁膜は、例えば図4(B)に示すよう
にCVD法で堆積したSiO 2 膜でもよいが、例えばB
SGやBPSG等の他の組成の絶縁膜、あるいはSOG
等、他の方法で堆積したSiO2 膜でもよい。Referring to FIG. 3, in step S1, the substrate
Alternatively, a device structure is formed on the wafer, and step S2
In this case, an insulating film is deposited to cover such device structure.
Be stacked. This insulating film is, for example, as shown in FIG.
Deposited on the surface by CVD method TwoIt may be a membrane, but for example B
Insulating film of other composition such as SG or BPSG, or SOG
SiO deposited by other methods such asTwoIt may be a membrane.
【0034】さらに工程S3で、先に工程S2で堆積し
た絶縁膜をパターニングし、絶縁膜中に、図5(C)の
コンタクトホール3aに相当するコンタクトホールある
いは溝等の凹パターンを形成する。さらに、工程S4
で、かかる絶縁膜上に、前記凹パターンを埋めるように
導体層4に対応する導体層を堆積する。ここで導体層は
W以外に、半導体集積回路で一般的に使われているA
l,Cu等の金属あるいは合金であってもよい。In step S3, the insulating film previously deposited in step S2 is patterned to form a concave pattern such as a contact hole or a groove corresponding to the contact hole 3a in FIG. 5C in the insulating film. Further, step S4
Then, a conductor layer corresponding to the conductor layer 4 is deposited on the insulating film so as to fill the concave pattern. Here, the conductor layer is A, which is generally used in semiconductor integrated circuits, in addition to W.
It may be a metal or alloy such as l or Cu.
【0035】次に、工程S5において、前記導体層を、
本発明によるMnO2 を砥粒として含む研磨剤により、
通常の研磨布上で研磨する。この研磨工程では、MnO
2 砥粒はH2 O等の溶媒中に懸濁して使用されるが、本
発明では前記溶媒に酸化剤を添加することはしない。そ
の結果、研磨の際に前記凹パターンを埋めている導体層
中に形成されているシームが酸化剤に侵食されることが
なく、また砥粒により研磨されてしまうことがない。Next, in step S5, the conductor layer is
With the abrasive containing MnO 2 according to the present invention as abrasive grains,
Polish on a normal polishing cloth. In this polishing process, MnO
The 2 abrasive grains are used by suspending them in a solvent such as H 2 O, but in the present invention, an oxidizing agent is not added to the solvent. As a result, at the time of polishing, the seam formed in the conductor layer filling the concave pattern is not eroded by the oxidizing agent and is not polished by the abrasive grains.
【0036】次に、工程S6において、前記工程S5で
研磨した基板を酸中で処理し、残留しているMnO2 を
酸に溶解させて除去する。この工程では、先に説明した
HCl,H2 SO4 ,HNO3 ,HF等の酸に酸化剤を
混合し、残留しているMnO 2 を溶解・除去する。その
結果、砥粒として使ったMnO2 による基板の金属汚染
が除去され、さらに残留粒子数が減少する。Next, in step S6, in step S5
Treat the polished substrate in acid to remove residual MnO2
Dissolve in acid and remove. In this process,
HCl, HTwoSOFour, HNOThree, HF and other acids with oxidants
MnO remaining after mixing TwoIs dissolved and removed. That
As a result, MnO used as abrasive grainsTwoSubstrate metal contamination by
Are removed, and the number of residual particles is further reduced.
【0037】さらに、工程S6の後、このようにして得
られた構造上にさらに別の構造を次の工程で形成しても
よい。工程S6で得られた構造は、清浄で平坦な上主面
を有するため、その上に容易に次の構造を形成すること
ができる。また、本発明による、MnO2 よりなる砥
粒,かかる砥粒を含む研磨剤、およびかかる研磨剤を使
った研磨方法は、半導体装置の製造に限定されるもので
はなく、一般の研磨工程にも有用である。Further, after step S6, another structure may be formed in the next step on the structure thus obtained. Since the structure obtained in step S6 has a clean and flat upper main surface, the next structure can be easily formed thereon. Further, the abrasive grains made of MnO 2 , the polishing agent containing the abrasive grains, and the polishing method using the polishing agent according to the present invention are not limited to the manufacture of semiconductor devices, and can be applied to general polishing steps. It is useful.
【0038】以上、本発明を好ましい実施例にもとづい
て説明したが、本発明はかかる実施例に限定されるもの
ではなく、その要旨内において様々な変形・変更が可能
である。Although the present invention has been described above based on the preferred embodiments, the present invention is not limited to such embodiments, and various modifications and changes can be made within the scope thereof.
【0039】[0039]
【発明の効果】請求項1,3および4の発明によれば、
従来の研磨剤で砥粒と併用される液体の酸化剤が本発明
では使われないため、かかる酸化剤が研磨工程で導体プ
ラグのシーム等、コンタクトを形成する導体パターン中
の欠陥部に侵入することがない。このため、信頼性の高
いコンタクトを形成することができる。According to the inventions of claims 1, 3 and 4,
Since a liquid oxidizer that is used together with abrasive grains in a conventional polishing agent is not used in the present invention, such an oxidant penetrates into a defective portion in a conductor pattern forming a contact such as a seam of a conductor plug in a polishing process. Never. Therefore, a highly reliable contact can be formed.
【0040】請求項2に記載の本発明の特徴によれば、
Mn砥粒の粒径を10μm以下に設定することにより、
絶縁層中に埋め込まれた微細な導体パターン中に研磨の
際に形成される凹部の大きさを最小化することができ
る。請求項4記載の本発明の特徴によれば、本発明は半
導体装置の配線パターンに使われる導体の研磨に効果的
であり、半導体装置の製造に有用である。According to a feature of the present invention described in claim 2,
By setting the grain size of the Mn abrasive grains to 10 μm or less,
It is possible to minimize the size of the recesses formed during polishing in the fine conductor pattern embedded in the insulating layer. According to the features of the present invention described in claim 4, the present invention is effective for polishing a conductor used for a wiring pattern of a semiconductor device, and is useful for manufacturing a semiconductor device.
【0041】請求項5記載の本発明の特徴によれば、研
磨工程の後、基板を酸、例えばHCl、H2 SO4 HN
O3 あるいはHFで洗浄することにより、結果基板のM
nによる汚染および残留パーティクル量を最小化するこ
とができる。請求項6記載の本発明の特徴によれば、洗
浄工程で、基板洗浄を酸と酸化剤の混合液により実行す
ることにより、洗浄効率を向上させることができ、その
結果高い歩留りで半導体装置を製造することができる。
研磨工程と異なり、洗浄工程で酸化剤を使用してもコン
タクトホールを埋める導体プラグが侵食されることはほ
とんどない。このため、かかる洗浄工程の結果得られた
半導体装置の信頼性が低下することはない。According to a feature of the present invention as set forth in claim 5, after the polishing step, the substrate is treated with an acid such as HCl, H 2 SO 4 HN.
By cleaning with O 3 or HF, M
Contamination due to n and the amount of residual particles can be minimized. According to the feature of the present invention described in claim 6, the cleaning efficiency can be improved by performing the substrate cleaning in the cleaning step with the mixed liquid of the acid and the oxidant, and as a result, the semiconductor device can be manufactured with a high yield. It can be manufactured.
Unlike the polishing process, even if an oxidizer is used in the cleaning process, the conductor plug filling the contact hole is hardly eroded. Therefore, the reliability of the semiconductor device obtained as a result of the cleaning process does not deteriorate.
【図1】本発明で使った試験片の構成を示す図である。FIG. 1 is a diagram showing a configuration of a test piece used in the present invention.
【図2】本発明の効果を示す図である。FIG. 2 is a diagram showing the effect of the present invention.
【図3】本発明の研磨工程を使った半導体装置の製造方
法を示す図である。FIG. 3 is a diagram showing a method for manufacturing a semiconductor device using the polishing process of the present invention.
【図4】(A),(B)は従来の半導体装置の製造工程
を示す図(その一)である。4A and 4B are views (No. 1) showing a manufacturing process of a conventional semiconductor device.
【図5】(C),(D)は従来の半導体装置の製造工程
を示す図(その二)である。5 (C) and 5 (D) are views showing a conventional manufacturing process of a semiconductor device (No. 2).
【図6】(E),(F)は従来の半導体装置の製造工程
を示す図(その三)である。6 (E) and 6 (F) are views (No. 3) showing a conventional manufacturing process of a semiconductor device.
【図7】(G),(H)は従来の半導体装置の製造工程
を示す図(その四)である。7 (G) and 7 (H) are views showing a conventional semiconductor device manufacturing process (No. 4).
【図8】(I),(J)は従来の半導体装置の製造工程
を示す図(その五)である。8 (I) and 8 (J) are views showing a conventional semiconductor device manufacturing process (No. 5).
【図9】(A),(B)は、従来の研磨工程で発生して
いた問題点を示す図である。9 (A) and 9 (B) are views showing a problem that has occurred in a conventional polishing process.
1,11 基板 1a フィールド酸化膜 1b,1c 拡散領域 1d チャネル領域 2 ゲート電極 2a,2b ゲート側壁絶縁膜 3,5,7,12 絶縁膜 3a コンタクトホール 4,6 導体層 4a 凹部 4b 導体プラグ 4c シーム 5a 溝 6a 凹部 6b 導体パターン 12a コンタクトホール 13a 導体パターン凹部 13b シーム 1, 11 substrate 1a field oxide film 1b, 1c diffusion region 1d channel region 2 gate electrodes 2a, 2b gate sidewall insulating film 3, 5, 7, 12 insulating film 3a contact hole 4,6 conductor layer 4a recess 4b conductor plug 4c seam 5a groove 6a recess 6b conductor pattern 12a contact hole 13a conductor pattern recess 13b seam
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大石 明良 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 鈴木 隣太郎 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 塙 健三 埼玉県上尾市原市1380−1 (72)発明者 植田 成生 埼玉県北足立郡吹上町富士見4−12−25 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Akira Oishi, Akira Oishi, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Rentaro Taro, 1015, Uedanaka, Nakahara-ku, Kawasaki, Kanagawa, Fujitsu Limited (72) Inventor Kenzo Hanawa 1380-1 Hara City, Ageo City, Saitama Prefecture (72) Inventor Shigeo Ueda 4-12-25 Fujimi, Fukiage Town, Kitadachi-gun, Saitama Prefecture
Claims (6)
砥粒を含む研磨剤。1. An abrasive containing MnO 2 or abrasive grains containing MnO 2 as a main component.
とを特徴とする請求項1記載の研磨剤。2. The abrasive according to claim 1, wherein the grain size of the abrasive grains is 10 μm or less.
うことを特徴とする研磨方法。3. A polishing method using an abrasive containing abrasive grains of MnO 2 .
絶縁層に凹部を形成する工程と;前記凹部を埋めるよう
に、前記絶縁層上に導体層を堆積する工程と;前記導体
層を、前記絶縁層が露出するまで研磨する研磨工程とを
含む半導体装置の製造方法において、 前記研磨工程を、MnO2 を砥粒として含む研磨剤を使
って実行することを特徴とする半導体装置の製造方法。4. A step of forming an insulating layer on a substrate; a step of forming a recess in the insulating layer; a step of depositing a conductor layer on the insulating layer so as to fill the recess; And a polishing step of polishing the insulating layer until the insulating layer is exposed, wherein the polishing step is performed using a polishing agent containing MnO 2 as abrasive grains. Production method.
程を含み、前記洗浄工程は前記研磨工程の後で実行され
ることを特徴とする請求項4記載の半導体装置の製造方
法。5. The method of manufacturing a semiconductor device according to claim 4, further comprising a cleaning step of cleaning the substrate with an acid, the cleaning step being performed after the polishing step.
合液により実行されることを特徴とする請求項5記載の
半導体装置の製造方法。6. The method of manufacturing a semiconductor device according to claim 5, wherein the cleaning step is performed with a mixed solution of the acid and the oxidizing agent.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16905795A JP3529902B2 (en) | 1995-07-04 | 1995-07-04 | Method for manufacturing semiconductor device |
TW085108035A TW317003B (en) | 1995-07-04 | 1996-07-03 | Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry |
KR1019960027065A KR100251057B1 (en) | 1995-07-04 | 1996-07-04 | Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry |
US08/884,165 US6159858A (en) | 1995-07-04 | 1997-06-27 | Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16905795A JP3529902B2 (en) | 1995-07-04 | 1995-07-04 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0922888A true JPH0922888A (en) | 1997-01-21 |
JP3529902B2 JP3529902B2 (en) | 2004-05-24 |
Family
ID=15879549
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16905795A Expired - Fee Related JP3529902B2 (en) | 1995-07-04 | 1995-07-04 | Method for manufacturing semiconductor device |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP3529902B2 (en) |
KR (1) | KR100251057B1 (en) |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001196335A (en) * | 1999-11-29 | 2001-07-19 | Applied Materials Inc | Method and device for electrochemical mechanical planarization |
US6361403B1 (en) | 1998-12-18 | 2002-03-26 | Tosoh Corporation | Abrasive member, abrasive disc provided with same, and polishing process |
US6375543B1 (en) | 1998-12-28 | 2002-04-23 | Tosoh Corporation | Abrasive molding, abrasive disc and polishing process using the abrasive disc |
US7637270B2 (en) | 2002-05-21 | 2009-12-29 | Fujitsu Limited | Method of washing a polished object |
WO2011070839A1 (en) | 2009-12-11 | 2011-06-16 | 三井金属鉱業株式会社 | Abrasive material |
DE112010005467T5 (en) | 2010-04-09 | 2013-01-31 | Mitsui Mining & Smelting Co., Ltd. | Polish and polishing process with it |
US8702826B2 (en) | 2012-06-14 | 2014-04-22 | Fujitsu Limited | Abrasive agent, method for producing abrasive agents, and electronic device |
US10323162B2 (en) | 2009-12-11 | 2019-06-18 | Mitsui Minig & Smelting Co., Ltd. | Abrasive material |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100444307B1 (en) * | 2001-12-28 | 2004-08-16 | 주식회사 하이닉스반도체 | Method for manufacturing of metal line contact plug of semiconductor device |
-
1995
- 1995-07-04 JP JP16905795A patent/JP3529902B2/en not_active Expired - Fee Related
-
1996
- 1996-07-04 KR KR1019960027065A patent/KR100251057B1/en not_active IP Right Cessation
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6361403B1 (en) | 1998-12-18 | 2002-03-26 | Tosoh Corporation | Abrasive member, abrasive disc provided with same, and polishing process |
US6375543B1 (en) | 1998-12-28 | 2002-04-23 | Tosoh Corporation | Abrasive molding, abrasive disc and polishing process using the abrasive disc |
KR100637887B1 (en) * | 1998-12-28 | 2006-10-23 | 도소 가부시키가이샤 | Molded body for polishing, surface plate for polishing and polishing method using the same |
JP2001196335A (en) * | 1999-11-29 | 2001-07-19 | Applied Materials Inc | Method and device for electrochemical mechanical planarization |
US7637270B2 (en) | 2002-05-21 | 2009-12-29 | Fujitsu Limited | Method of washing a polished object |
WO2011070839A1 (en) | 2009-12-11 | 2011-06-16 | 三井金属鉱業株式会社 | Abrasive material |
US10323162B2 (en) | 2009-12-11 | 2019-06-18 | Mitsui Minig & Smelting Co., Ltd. | Abrasive material |
DE112010005467T5 (en) | 2010-04-09 | 2013-01-31 | Mitsui Mining & Smelting Co., Ltd. | Polish and polishing process with it |
US8702826B2 (en) | 2012-06-14 | 2014-04-22 | Fujitsu Limited | Abrasive agent, method for producing abrasive agents, and electronic device |
Also Published As
Publication number | Publication date |
---|---|
KR100251057B1 (en) | 2000-04-15 |
KR970008387A (en) | 1997-02-24 |
JP3529902B2 (en) | 2004-05-24 |
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