KR100251057B1 - Slurry containing manganese oxide and a fabrication process of a semiconductor device using such a slurry - Google Patents

Abstract

The slurry contains MnO ₂ or other manganese oxide as the main component of the abrasive particles. Furthermore, a polishing process using such a manganese oxide abrasive and a method of manufacturing a semiconductor device using such a polishing process are provided.

Description

Slurry containing manganese oxide and method of manufacturing semiconductor device using same

1A-J illustrate a conventional semiconductor device manufacturing method including a polishing process.

2a and b are diagrams illustrating a problem of erosion of a seam in a conventional polishing process.

3 shows the configuration of test pieces used in the experiments underlying the present invention to investigate the polishing rates achieved by various slurries.

4 is a diagram schematically showing the configuration of a polishing apparatus used in the present invention.

5 is a graph showing the experimental results.

6A-J illustrate a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

7 is a flowchart showing a method of manufacturing a semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a diagram showing a phase of manganese oxide which forms the basis of the semiconductor device according to the second embodiment of the present invention.

9A-C illustrate a method of manufacturing a semiconductor device in accordance with a second embodiment of the present invention.

10 is a view comparing step heights remaining on a semiconductor surface after various polishing processes including the manufacturing method according to the second embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the manufacture of semiconductor devices, and more particularly, to a method of manufacturing a semiconductor device including a polishing process and a slurry used in such a polishing process.

BACKGROUND OF THE INVENTION In semiconductor integrated circuits, multilayer wiring structures are typically used to achieve electrical wiring between various semiconductor devices formed on a conventional semiconductor substrate. In general, a multilayer wiring structure includes an insulating layer formed on a semiconductor substrate and a wiring pattern embedded in the insulating layer. Since such a multi-layered wiring structure includes a plurality of wiring layers stacked on each other, it is necessary that each wiring layer has a flat upper main surface to allow the lamination of such wiring layers.

Thus, conventionally, a multi-layered wiring is formed by forming contact holes or wiring grooves on the insulating layer, filling contact holes or wiring grooves with the conductive layer, and polishing the conductive layer until the surface of the insulating layer is exposed. Forming the structure was done. This ensures a flat surface for each wiring layer, and makes it possible to easily form another wiring layer including the insulating layer and the conductor pattern embedded therein.

1A to 1J show a process of forming such a multilayer wiring structure including a polishing process as applied to the manufacturing process of the MOS transistor.

Referring to FIG. 1A, a MOS transistor is formed on one Si substrate coated in a P-type corresponding to the active region 1A defined by the field oxide film 1a. More specifically, the MOS transistor is separated from each other by the n ⁺ type diffusion region 1b formed on the surface of the active region 1A and the other n ⁺ type diffusion region 1C formed on the surface of the active region 1A by the channel region 1b of the MOS transistor. have. On the substrate 1, the gate electrode 2 is formed so as to cover the channel region 1d with the gate oxide film (not shown) interposed therebetween. Furthermore, the gate electrode 2 has sidewall insulating films 2a and 2b on each opposite sidewall. The diffusion regions 1b and 1c serve as the source and the drain of the MOS transistor, respectively.

In the step of FIG. 1A, an interlayer insulating film 3 of SiO ₂ is typically deposited to a thickness of about 50 nm by a CVD process so as to embed the MOS transistor formed by itself. As a result of deposition of the interlayer insulating film, the diffusion regions 1b and 1c are covered with the SiO ₂ film 3 in addition to the gate electrode 2. As a result, the interlayer insulating film 3 shows protrusions and recesses in accordance with the above-described gate electrode 2 as shown in FIG. 1A.

Next, in the step of FIG. 1B, the surface of the insulating film 3 is polished uniformly to planarize the structure of FIG. 1A. Furthermore, in the step of FIG. 1C, the insulating film 3 is subjected to a photolithography patterning process to form a contact hole 3a in the insulating film 3 to expose the surface of the diffusion region 1b, and in the step of FIG. 1D, the structure of FIG. Is deposited uniformly by a four-layer CVD process of a conductive layer of a metal or alloy such as W, Al, or Cu. As a result, the conductor layer 4 fills the contact hole 3a, and the conductor layer 4 contacts the diffusion region 1b in the contact hole 3a described above. As described above, the conductor layer 4 exhibits a recessed portion on its upper main surface corresponding to the contact hole 3a.

Next, the conductor layer 4 is uniformly polished to obtain the structure shown in FIG. 1E. In the structure of FIG. 1E, a flat surface corresponding to the upper main surface of the insulating film 3 is obtained. Preferably, polishing of the conductor layer 4 selectively acts on the metal forming the conductor layer 4 to stop spontaneously for some time upon exposure of the upper main surface of the insulating film 3. As a result of this polishing, the conductive plug 4b is formed in contact with the diffusion region 1b so that the conductive plug 4b fills the contact hole 3a. As a result of the planarization achieved by the polishing process, the conductive plug 4b has an upper main surface corresponding to the upper main surface of the insulating film 3.

Next, in the step of FIG. 1f, another insulating film 5 such as SiO ₂ is formed on the flat structure of FIG. 1e to perform a photolithography patterning process to form the grooves 5a as shown in FIG. The conductive plug 4b is exposed. Furthermore, in the step of FIG. 1h, another conductor layer 6 formed of a metal or an alloy such as W, Al, Cu, or the like is deposited on the structure of FIG. 1g. As a result, the recessed portions 6a are formed on the conductor layer 6 as shown in FIG. 1H corresponding to the grooves 5a.

Furthermore, in FIG. 1I, the groove layer 5a is filled by the conductor pattern 6b which forms the planarization structure by grinding the conductor layer 6 to form a flattening structure. After formation of the structure of FIG. 1i, another insulating film 7 is formed as shown in FIG. 1j. As a result, various wiring patterns can be formed on the insulating film 7.

In the above-mentioned manufacturing process, the polishing steps of 1e and 1i were carried out on the polishing cloth of the urethane resin by using a mixture of α-Al ₂ O ₃ and H ₂ O ₂ as the slurry. A typical example of a slurry is MSW-1000 (trade name) supplied by Rodel. In the case of using such a mixture of α-Al ₂ O ₃ and H ₂ O ₂ as a slurry, H ₂ O ₂ causes oxidation in the conductor layer to be polished, and α-Al ₂ O ₃ abrasive grains result in oxidation of the conductor layer. The oxide formed as is ground.

For example, the pulverization of the W layer by the slurry first causes the formation of W _x O _y as a result of the oxidation of H ₂ O ₂ , whereas the oxide (W _x O _y ) is α-Al ₂ O ₃ Easily removed by the particles.

On the other hand, when such a conventional slurry containing H ₂ O ₂ , which is a strong liquid oxidant, is applied to the polishing of a conductor layer such as W, H ₂ O ₂ is formed in the conductor layer 4 upon deposition on the conductor layer 4. The problem of deep penetration into the conductor layer 4 filling the contact hole 3a along the gap 4C occurs. As a result, the polishing of the conductor layer 4 performed in the presence of H ₂ O ₂ expands the recesses from the state of FIG. 2A to the state of FIG. 2B. That is, as shown in FIG. 2B, a large and deep recess is formed almost in the center of the conductive plug 4b corresponding to the gap 4C as described above, while such large recess causes a problem of reliability of electrical contact in the contact hole 3a. The problem of the formation of recesses in the contact holes as a result of the polishing is particularly serious in high density integrated circuits and semiconductor devices in which the diameter of the contact holes 3a is 0.5 mu m or less.

The above-mentioned gap 4C is formed as a result of the bonding of the conductor layer growing on both side walls of the contact hole 3a toward the center of the contact hole when the conductor layer is deposited. Because of the nature of these gaps, gap 4C contains a large amount of defects or imperfections and is extremely susceptible to oxidation by H ₂ O ₂ . The oxidized portion of the plug 4b is easily removed by a polishing treatment using abrasive particles such as α-Al ₂ O ₃ .

Accordingly, an object of the present invention is to provide a novel and useful method for producing a semiconductor device including a polishing step, and a slurry used in such polishing step, in order to solve the above-mentioned problems and the like.

Another more specific object of the present invention is to provide a method for manufacturing a semiconductor device comprising a slurry free of a fluid oxidant and a polishing process using the slurry.

Another object of the present invention is to provide a slurry composed of abrasive particles and a solvent in which the abrasive particles are dispersed, wherein the abrasive particles contain manganese oxide as a main component.

Still another object of the present invention is a method of manufacturing a semiconductor device comprising polishing a conductive layer provided on an insulating layer, the method comprising polishing the conductive layer using a slurry containing abrasive particles and a solvent. There is provided a method for manufacturing a semiconductor device in which the abrasive particles contain manganese oxide as a main component.

According to the present invention, a slurry containing manganese oxide as a main component of abrasive particles can successfully and efficiently polish the conductor layer, and polishing can be stopped spontaneously and accurately upon exposure of the underlying insulating layer.

In particular, by using MnO ₂ for abrasive particles, the abrasive particles release oxygen to act as a strong solid oxidant, effectively oxidizing the conductor layer to be polished. The metal oxide formed as a result of oxidation is easily removed by the grinding treatment associated with the polishing treatment by the abrasive particles.

For example, MnO ₂ acts on W in accordance with the following reaction.

Here, W _x O _y is easily removed as a result of grinding by Mn ₂ O ₃ product or unreacted MnO ₂ abrasive particles. On the other hand, the remaining MnO ₂ particles or Mn ₂ O ₃ product are later dissolved by a washing treatment performed in an acid such as HCl, H ₂ SO ₄ , HNO ₃ or HF and hydrogen peroxide, according to any of the following reactions.

Here, manganese reaction products such as MnCl ₂ , Mn (NO ₃ ) ₂ , MnSO ₄ and MnF ₂ are all dissolved in water. Thus, the present invention can effectively minimize the contamination of the semiconductor substrate by the remaining particles and Mn.

Since the abrasive particles act as oxidizing agents (solid oxidizing agents) as shown in the above reaction, the present invention does not require a fluid oxidizing agent such as H ₂ O ₂ in a solvent.

This successfully prevents the erosion problem of the gap caused by the penetration of the fluid oxidant in the gap as in the case of FIG. 2B, and makes reliable electrical contact. Generally, pure water (H ₂ O) or lower alcohol is used as the solvent. In the above washing treatment, H ₂ O is used, but the concentration of H ₂ O ₂ in the washing treatment is less than 2%, which is actually smaller than the concentration conventionally used in the polishing treatment (about 1/25). Thus, no substantial problem of crevices in the washing process occurs.

Another object of the present invention is to provide a slurry having a composition composed of abrasive particles and a solvent in which the abrasive particles are dispersed, wherein the abrasive particles are selected from Mn ₂ O ₃ , Mn ₃ O ₄ and mixtures thereof. .

According to the present invention, the slurry selectively acts on the insulating layer as compared to the semiconductor layer or the conductor and is effective for polishing the insulating layer in the method of manufacturing the semiconductor device.

Still another object of the present invention is a method of manufacturing a semiconductor device including a polishing process, comprising: polishing an insulating layer provided on a lower layer which is one of a conductor layer and a semiconductor layer with a slurry composed of abrasive particles and a solvent, and polishing The present invention provides a method for manufacturing a semiconductor device, wherein the particles comprise a step having a composition selected from Mn ₂ O ₃ , Mn ₃ O _4, and mixtures thereof.

According to the invention, the polishing step of the insulating layer spontaneously stops upon exposure of the underlying conductor or semiconductor layer without the use of additional polishing stopper layers.

The underlying conductor layer or semiconductor layer itself acts as a polishing stopper. Thereby, manufacturing processes, such as a manufacturing process of a shallow groove structure, become practically easy.

Other objects and further advantages of the present invention will become apparent from the following detailed description based on the accompanying drawings.

3 shows the test piece used in the first embodiment of the present invention to investigate the performance of various slurries.

Referring to FIG. 3, the test piece includes a SiO ₂ film 12 deposited on a Si substrate 11 to a thickness of about 50 nm by a CVD process. The SiO ₂ film 12 has a plurality of contact holes 12a and 12b having internal diameters D ₁ and D ₂ , respectively, and the conductor layer 13 W having a thickness of about 50 nm on the SiO ₂ film 12 to fill the contact holes 12a and 12b. Is deposited. The conductor layer 13 is deposited by the CVD process, and recessed portions 13a are formed in the upper main surface thereof corresponding to the contact holes 12a and 12b. As already described with reference to FIGS. 2A and 2B, the W layer 13 is a bonding result for growing the W layer generated when the W layer 13 fills the contact hole 12a, and includes a gap 13b in each recess 13a. Because of the nature of the gap itself, gap 13b inevitably contains large amounts of crystal incompleteness or bonding.

In the experiment, the test piece of FIG. 3 was subjected to the polishing treatment performed by the apparatus 100 shown in FIG.

Referring to FIG. 4, the polishing apparatus 100 comprises a turntable 101 covered by a urethane cloth 102 supplied by Rodel-Nitta under the trade name SUBA 400.

The test piece of FIG. 3 is held by the polishing head 104 which is processed in the same direction as the rotational direction of the turntable 101, and polishing is carried out on the W layer 13 on the urethane cloth 102 which pushes the test piece against the turntable 101 at a pressure of 200 to 700 g / cm 2. Apply.

In the experiment, a slurry containing MnO ₂ as abrasive grains and H ₂ O as a solvent was used in cloth 102 as schematically indicated by 103, and the concentration of MnO ₂ abrasive grains was adjusted to about 20% by weight as an example. .

After polishing, over-etching was performed on the polishing surface and the cross section of the test piece was observed with an electron microscope to measure and evaluate the depth of recesses such as those shown in FIG. 2B.

The fifth turning as showing the polishing rate of the W layer 13 in comparison with the SiO ₂ layer provided on three separate specimens instead of the W layer 3, was shown the removal rate observed for the W layer 13 as heukwon, the SiO ₂ layer The observed polishing rate is indicated by the white circle.

Referring to FIG. 5, the polishing rate for the W layer actually exceeds the polishing rate for the SiO ₂ layer as long as the particle size of the MnO ₂ abrasive is less than about 10 μm. This allows MnO ₂ abrasive particles to act selectively on the W layer, while polishing stops immediately when the SiO ₂ layer is exposed. That is, the SiO ₂ layer acts as an abrasive purifier in polishing the W layer.

On the other hand, when the size of the MnO ₂ particles exceeds 10 μm, the polishing rate for the SiO ₂ layer exceeds the polishing rate for the W layer. Therefore, in order to polish the W layer while using the SiO ₂ layer as an etching stopper, in order to polish the W layer while using the MnO ₂ layer, it is necessary to adjust the size of the MnO ₂ abrasive grain to 10 μm or less. desirable.

Next, a first embodiment of the present invention for manufacturing a semiconductor device including a polishing step performed by such a MnO ₂ slurry will be described with reference to FIGS. 6A-J.

Referring to FIG. 6A, a MOS transistor is formed on a Si substrate 11 coated in a P-type corresponding to the active region 1A defined by the field oxide film 11a. More specifically, the MOS transistor includes an n ⁺ type diffusion region 11b formed on the surface of the active region 11A and another n ⁺ type diffusion region 11C formed on the surface of the active region 11A, and includes a diffusion region 11b and a diffusion region 11c. The diffusion region 11b and the diffusion region 11c are separated from each other by the channel region 11d of the MOS transistor. On the substrate 11, a gate electrode 12 is provided to cover the channel region 11d via a gate oxide film (not shown). Moreover, the gate electrode 12 has sidewall insulating films 12a and 12b on their opposite sidewalls. The diffusion regions 11b and 11c serve as sources and drains of the MOS transistors, respectively.

In the step of FIG. 6A, an interlayer insulating film 13 of SiO ₂ is typically deposited to a thickness of about 50 nm to fill the MOS transistor. As a result of the deposition of the interlayer insulating film 13, the diffusion regions 11b and 11c are covered with the SiO ₂ film 13 in addition to the gate electrode 12. As a result, the interlayer insulating film 13 shows protrusions and recesses in accordance with the above-described gate electrode 12 as shown in FIG. 5A.

Next, in the step of FIG. 6B, the surface of the insulating film 13 is uniformly polished by using a polishing device such as that shown in FIG. 4 to flatten the structure of FIG. Furthermore, in the step of FIG. 6C, the insulating film 13 is subjected to photolithography patterning, and a contact hole 13a is formed in the interlayer insulating film 13 to expose the surface of the diffusion region 11b. In the step of FIG. 6D, W, Al, Cu, or the like is exposed. The conductor layer of the metal or alloy is uniformly deposited on the structure of FIG. 6C by the CVD process.

As a result, the conductor layer 14 fills the contact hole 13a and the conductor layer 14 is in contact with the diffusion region 11b in the contact hole 13a described above. Since the conductor layer 14 fills the contact hole 13a as described above, the conductor layer 14 shows a recessed portion on the upper main surface thereof corresponding to the contact hole 13a.

Next, the conductor layer 14 is uniformly deposited using a slurry containing MnO ₂ particles and H ₂ O (pure water) to obtain the structure shown in FIG. 6E. In the structure of FIG. 6E, a flat surface is obtained corresponding to the upper major surface of the insulating layer 13 due to the polishing selectivity achieved when using MnO ₂ abrasive grains. More specifically, polishing selectively acts on the metal forming the conductor layer 14 and stops spontaneously for some time when the upper main surface of the insulating film 13 is exposed. As a result of this polishing, the conductive plug 14b is formed in contact with the diffusion region 11b, so that the conductive plug 14b fills the contact hole 13a. As a result of the planarization achieved by the polishing process, the conductive plug 14b has an upper main surface corresponding to the upper main surface of the insulating film 13.

Next, in the step of FIG. 6F, an insulating film 15 such as SiO ₂ is formed on the planarization structure of FIG. 6E by the photolithography patterning process, and grooves 15a are formed as shown in FIG. 6G, furthermore, 6h In the step of Fig., Another conductor layer 16, typically formed of a metal or alloy such as W, Al, Cu, etc., is deposited on the structure of Fig. 6g. As a result, the recessed portions 16a are formed on the conductor layer 16 as shown in FIG. 6H corresponding to the grooves 15a.

Further, in the step of FIG. 6i, the conductor layer 16 is polished to form a planarization structure, and the portion of the conductor layer 16 is formed, and the groove 15a is filled by the conductor pattern 16b forming the conductor layer 16. . After the structure shown in Fig. 6i is formed in this way, another insulating film 17 is formed as shown in Fig. 6j.

As a result, various wiring patterns can be further formed on the insulating film 17.

In the above-described process, since the polishing process used in the step of FIG. 6E does not use a fluid oxidant, the conductive plug 14b has no practical requirement. As already mentioned above, MnO ₂ forming abrasive particles acts as a solid oxidant to release oxygen upon polishing. The W layer 14 polished by the released oxygen is oxidized. Similar polishing processes can be applied to the steps of FIG. 6i.

In any of the steps of Figs. 6E and 6I, it is preferable to set the size of the abrasive grains of MnO ₂ to less than 10 mu m in accordance with that shown in Fig. 5.

After the polishing process of FIG. 6e or 6i, the MnO ₂ abrasive grains must be completely removed from the substrate by a cleaning process in order to prevent metal contamination of the apparatus.

In the present invention, experiments were conducted to dissolve the remaining MnO ₂ abrasive particles in various acids.

More specifically, the inventors of the present invention immersed the polishing test pieces previously described in the following solutions for 30 seconds, respectively, and washed them.

Samples obtained as a result of treatment in the above solutions (A)-(D) were denoted by A, B, C and D, respectively.

In Samples A, B, C and D, the following reactions occur.

Here, each reaction produces a water-soluble product such as MnCl ₂ , Mn (NO ₃ ) ₂ , MnSO ₄ and MnF ₂ .

For comparison, a reference test piece was prepared as sample E, but in sample E, the test piece was washed directly after polishing without acid treatment. Furthermore, another reference test piece was prepared as sample F, in which the test piece was polished by a substrate slurry using α-Al ₂ O ₃ (MSW-1000). In sample F, the test piece was washed directly after polishing without acid treatment.

Then, metal contamination was evaluated and all sample A-F was immersed in HF solution at 0.5% concentration level for 20 seconds before counting the residual particle count. The results are summarized in Table 1 below.

TABLE 1

As can be clearly seen in Table 1, contamination by Mn can be neglected for sample AD undergoing the washing process of the present invention. Moreover, the sample AD shows that the residual particle number is reduced compared to that of (sample F) in the conventional polishing process. It can also be seen that the Mn contamination for sample AD is reduced compared to sample E, which omits acid treatment. This clearly indicates that the above acid treatment dissolves the residual MnO ₂ particles.

As described above, the polishing step using MnO ₂ abrasive grains is not limited to the W layer, but can be applied to other metal layers such as Al, Cu, or alloys thereof.

7 shows a method of manufacturing a semiconductor device including a polishing step in the form of a flowchart.

Referring to FIG. 7, step S1 of forming a device structure on a substrate or wafer is performed, and then step S2 of depositing an insulating film to cover the device structure is performed.

The insulating film is a CVD deposited SiO ₂ film as shown in FIG. 6B, and an insulating film of another composition such as BSG, BPSG, or SOG may be used.

In step S3, the thus-deposited insulating film is patterned to form recesses therein, the recesses being contact holes or wiring grooves similar to the contact holes 13a in FIG. 6C, and a conductor layer corresponding to the conductor layer 14 is deposited and described above. The step S4 of embedding the main portion is performed. The conductor layer may be a W layer or a conductor material such as Cu or Al as in the previously described embodiment.

Next, in step S5, the conductor layer 14 is polished on the polishing cloth while using the abrasive grains of MnO ₂ dispersed in a solvent such as H ₂ O. In the present invention, in contrast to the conventional chemical mechanical polishing process, no fluid oxidant is added to the solvent.

As a result, there is no problem of erosion of the gap in the conductor layer filling the recess.

After polishing step S5, step S6 is performed in which the substrate thus polished is treated in an acid which dissolves residual MnO ₂ particles in an acid. In this acid treatment step, as described above, an oxidizing agent is added to acids such as HCl, H ₂ SO ₄ , HNO ₃ , and HF. As a result of this acid treatment, metal contamination of the substrate is removed, and residual particles are actually reduced.

After step S6, the structure obtained as a result of the above-described steps S1-S6 is characterized by a washed flattened upper main surface suitable for the construction of the following structure, so that other structures may be formed on the thus formed structure as necessary.

Moreover, the slurry containing MnO ₂ abrasive particles as disclosed in the present invention is not limited to the manufacture of semiconductor devices and can be applied to other general polishing treatments.

In the investigation of a slurry containing MnO ₂ as abrasive particles, the inventors and the like insulated that manganese oxides such as Mn ₂ O ₃ or Mn ₃ O ₄ were insulated at a rate comparable to the polishing rate achieved by conventional colloidal silica slurries. It was further found that the layer could be selectively polished. Moreover, polishing was found to stop spontaneously upon exposure of a conductor material such as W or Cu or a semiconductor material such as Si.

Table 2 below summarizes the results of experiments performed by the present inventors on the slurry containing Mn ₂ O ₃ particles, and Table 3 summarizes the conditions of the polishing experiments.

TABLE 2

TABLE 3

Therefore, in Method A of Table 2, Mn ₂ O ₃ particles having a 0.2 μm piece diameter were used with a concentration of abrasive grains of 10% by weight as shown in Table 3.

In Table 3, polishing was performed by a 24-inch turntable that was continuously covered by SUBA 400 abrasive and IC 1000 abrasive while rotating the turntable at 90 rpm and the head at 180 rpm. The polishing pressure, that is, the pushing pressure of the head, was set at 470 g / cm 2.

As can be clearly seen in Table 2, Mn ₂ O ₃ abrasive particles (method A) were used to obtain a polishing rate of 120 nm / min for the SiO ₂ layer, which was conventionally achieved by a colloidal silica slurry. Comparable to a polishing rate of 125 nm / min. When a slurry containing Mn ₂ O ₃ particles was applied to polishing a semiconductor layer or conductor such as W, Cu or Si, very small polishing rate was observed under the same conditions. For example, a polishing rate of 30 nm / min was observed for Si, a polishing rate of 25 nm / min for W, and a 20 nm / min polishing rate for Cu. The above results clearly indicate that the slurry containing Mn ₂ O ₃ particles effectively acts on insulating layers such as SiO ₂ layers, but polishing stops immediately upon exposure of the metal or semiconductor layer.

In the case of using a conventional colloidal silica abrasive for the same purpose, it can be seen from Table 2 that the slurry polishes the Si layer at a polishing rate of 20 nm / min, but this polishing rate is slightly higher than that of the SiO ₂ film. This means that the Si layer cannot be used as an etching stopper in the polishing step performed by a conventional colloidal silica abrasive. Moreover, even in the case of a conductor layer such as W or Cu, the selectivity of polishing is about 2: 1. Thus, as long as a conventional colloidal silica abrasive is used, it cannot be expected that these metal layers effectively act as polishing stoppers.

Furthermore, in Table 2, "method B" one, as, MnO ₂ abrasive in the environment to form a Mn ₂ O ₃ on the surface of the MnO ₂ particles from the environment to form a Mn ₂ O ₃ on the surface of the MnO ₂ particles as indicated as By using the particles, the same excellent polishing selectivity can be achieved.

As is well known, transition metals that change valence states such as Mn cause an oxidation-reduction reaction, and as a result of this oxidation-reduction reaction, the manganese oxide formed as a result of the oxidation reaction changes.

8 is a phase diagram showing the oxidation-reduction reaction of Mn in an aqueous solution.

Referring to FIG. 8, the vertical axis represents the redox potential E and the horizontal axis represents the pH. In FIG. 8, it can be seen that the E-pH field of FIG. 8 is divided into a plurality of regions by the phase boundary corresponding to the oxidation-reduction reaction of Mn. For example, MnO ₂ appears as an oxide of Mn when the oxidation-reduction potential E is in the range of 0.8 to 1 V and the pH is in the range of 6 to 7. On the other hand, in the region where the pH is high and the potential E is low, Mn ₂ O ₃ or Mn ₃ O ₄ appears as an oxide of Mn. In FIG. 8, the interfaces indicated by "0", "-2", "-4", and "-6" have Mn ²⁺ concentrations of lM / 1, 0.0 M / 1, 0.0001 M / l and 0.000001 M / l indicates the case.

Thus, in method B, the inventors used the MnO ₂ particles previously described in a solvent to adjust pH and oxidation-reduction potential E such that Mn ₂ O ₃ appears as an oxide of Mn. By using MnO ₂ abrasive particles under these conditions, Mn ₂ O ₃ covers the surface of MnO ₂ particles, and these MnO ₂ particles covered with a layer of Mn ₂ O _{3 have} a high SiO ₂ polishing rate as clearly shown in Table 2. Shows excellence On the other hand, the treated abrasive particles exhibit a significantly reduced polishing rate for conductors such as W or Cu or semiconductors such as Si. The redox reaction of the Mn aqueous solution is easily controlled. For example, the pH can be controlled by mixing an acid such as HCl or an alkali such as KOH, and the oxidation-reduction potential E can be controlled by mixing ozone water or by bubbling H ₂ . The oxidation-reduction potential increases when ozone water is added and decreases by bubbling H ₂ .

9A-C show a process of forming a shallow separating gutter structure on a Si substrate according to a second embodiment of the present invention.

Referring to FIG. 9A, the separating gutter 51A is formed about 400 nm deep on the surface of the Si substrate 51. Subsequently, by the step of FIG. 9B, the SiO ₂ film 54 shows the recessed portion 54A on its upper circumferential surface corresponding to the separating gutter 51A on the structure of FIG.

Next, in the step of FIG. 9C, the SiO ₂ film 54 is polished using Mn ₂ O ₃ particles as the abrasive with H ₂ O serving as a solvent. As a result, the SiO ₂ film 54 is efficiently polished until the upper main surface of the substrate 51 is exposed. That is, the Si substrate 51 itself acts as a polishing stopper, and in view of the results in Table 2, it is possible to ensure the selectivity of the polishing rate exceeding 4 times for the SiO ₂ film for the Si substrate 51.

According to the processes of FIGS. 9A-C, the conventional step number required to form a shallow gutter structure including deposition and to pattern the polishing stop layer can be reduced. Furthermore, the obtained structure of FIG. 9C has a completely flat upper main surface in which the upper main surface of the Si substrate 51 embedding the shallow trough 51A and the upper main surface of the SiO ₂ film 54 exactly coincide with each other.

In the polishing step of FIG. 9C, MnO ₂ can be used as the abrasive particles together with a solvent for controlling the oxidation-reduction potential and pH as in the case of the method B of Table 2.

Even in this process, effective polishing of the SiO ₂ film 51 and spontaneous stop of polishing on the upper circumferential surface of the substrate 51 can be obtained.

According to the latter process, it is possible to use the same slurry used for polishing conductors such as the W layer and the like without changing the slurry. When polishing the SiO ₂ film 51, only the composition of the solvent is adjusted. This greatly simplifies the manufacturing method of the semiconductor device. For example, by setting the oxidation-reduction potential E to OV and the pH to 12 or more, a layer of Mn ₂ O ₃ can be formed on the surface of the MnO ₂ particles.

After the polishing step, the structure of FIG. 9c was immersed in a washing solution in which HCl, H ₂ O ₂ and H ₂ O were mixed at a volume ratio of 1: 1: 48 for 1 minute, and then immersed in HF solution at 0.5% concentration level for 1 minute Wash. After washing, most of the elements (Na, K, Fe, Mn) show concentration levels smaller than 5x10 ¹⁰ atoms / cm 2. Furthermore, no defects or scratches were observed on the polished surface of the Si substrate 51 or the SiO ₂ film 54.

FIG. 10 shows measurement results of step heights formed on the substrate 51 in the structure of FIG. 9C. In FIG. 10, the horizontal axis represents the height of the step, and the vertical axis represents the number of occurrences of the height of the step. Ideally, the step height should be zero.

As shown in Table 2, when polishing was performed according to the conventional method using a colloidal silica abrasive, a substantial step with a step height exceeding 0.1 μm appeared on the surface of the Si substrate 51, and it was found that the step height actually changed. Can be.

On the other hand, when using the method A or the method B of the present invention, it can be seen that the step height shows a very small change of almost 0.00 mu m. This result indicates that an almost completely flat surface is realized on the surface of the substrate 51 including the SiO ₂ film filling the separator 51A.

In the polishing step of FIG. 9C, Mn ₃ O ₄ may be used instead of Mn ₂ O ₃ particles.

Furthermore, a mixture of Mn ₂ O ₃ and Mn ₃ O ₄ may be used for the polishing step of FIG. 9C. Furthermore, even when Mn ₂ O ₃ particles are used for the polishing process, the redox potential E and the pH of the solvent may be adjusted.

The present embodiment is also useful when forming a multilayer wiring structure.

In addition, the present invention is not limited to the embodiments described herein, and various changes and modifications may be made without departing from the scope of the invention.

Claims (20)

A slurry for polishing an insulating layer or a metal layer used in a semiconductor device, the slurry containing MnO ₂ as a main component of abrasive grains. The slurry of claim 1, wherein the abrasive particles are made of MnO ₂ . The slurry of claim 1, wherein the abrasive particles have a particle size of less than 10 μm. A polishing method for an insulating layer or a metal layer used in a semiconductor device, comprising: polishing a target object with a slurry containing MnO ₂ as a main component of abrasive particles. Forming an insulating layer on the substrate, forming a recess on the insulating layer, depositing a conductor layer on the insulating layer to fill the recess, and polishing the conductor layer until the insulating layer is exposed; And the polishing step is performed by a slurry containing MnO ₂ as a main component of abrasive grains. The method of manufacturing a semiconductor device according to claim 5, further comprising a washing step of washing the substrate layer with an acid and after the polishing step. The method of manufacturing a semiconductor device according to claim 6, wherein said washing step is performed in a mixture of said acid and an oxidizing agent. The method of claim 6, wherein the acid is selected from the group consisting of HCl, HNO ₃ , H ₂ SO _4, and HF. A slurry for polishing an insulating layer or a metal layer used in a semiconductor device, the slurry comprising abrasive grains containing manganese oxide as a main component. The slurry of claim 9, wherein the manganese oxide comprises Mn ₂ O ₃ , Mn ₃ O _4, and mixtures thereof. Oxidation particles composed of abrasive particles containing MnO ₂ as a main component and a solvent for dispersing the abrasive particles, wherein the solvent is formed to form at least one of Mn ₂ O ₃ and Mn ₃ O ₄ on the surface of the abrasive particles. Slurry with reduction potential and pH. A polishing method for polishing an insulating material for use in a semiconductor device, the polishing method comprising the step of polishing the insulating material with abrasive particles mainly composed of manganese oxide. The polishing method of claim 12, wherein the manganese oxide comprises Mn ₂ O ₃ and Mn ₃ O ₄ . The polishing method according to claim 12, wherein the polishing step is performed in a solvent having a pH and an oxidation-reduction potential set so that MnO ₂ is changed to Mn ₂ O ₃ or Mn ₃ O ₄ . Forming an insulating layer on the lower non-insulating layer, and selectively polishing the insulating layer with respect to the lower non-insulating layer by a slurry containing manganese oxide as abrasive particles. The manufacturing method of a semiconductor device according to claim 15 wherein said lower non-insulating layer is comprised of a metal layer. The manufacturing method of a semiconductor device according to claim 15 wherein said lower non-insulating layer is comprised of a semiconductor layer. The method of claim 15, wherein the manganese oxide comprises Mn ₂ O ₃ , Mn ₃ O _4, and mixtures thereof. The semiconductor device according to claim 15, wherein the manganese oxide is composed of MnO ₂ , and the polishing step is performed in a solvent having an oxidation-reduction potential and a pH such that MnO ₂ is changed to Mn ₂ O ₃ or Mn ₃ O ₄ . Manufacturing method. 16. The polishing method according to claim 15, wherein the lower non-insulating layer is a semiconductor substrate having a separation trough, and the forming of the insulating layer is performed so that the SiO ₂ layer forming the insulating layer fills the separation trough. Causes selective removal of the SiO ₂ layer from the surface of the semiconductor substrate, thereby spontaneously stopping upon exposure of the surface of the semiconductor substrate.