JPH09223784A - Semiconductor device and current control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce inter-wiring capacitance and wiring resistance in an integrated circuit. SOLUTION: The semiconductor device is provided with a first semiconductor region consisting of a channel region 34 and a photoelectric conversion region 36, and a gate electrode 26 provided above the channel region 34 through a gate oxide film 24. A second semiconductor region adjacent to the channel region 34 and a third semiconductor region adjacent to the photoelectric conversion region 36 are provided separately. The second and third semiconductor regions are used as a source region 16 and a drain region 18 of the same conductivity type, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element used for optical wiring and a current control method.

[0002]

2. Description of the Related Art In recent years, the degree of integration and miniaturization of semiconductor integrated circuits is remarkable. Along with this, the wiring density for electrically connecting the individual semiconductor devices has increased, and there has been a problem such as signal delay due to wiring capacitance and wiring resistance. In the sub-half-micron era, as scaling of silicon LSI progresses, reduction of these wiring loads
This is an essential item for improving the performance of.

In order to reduce such inter-wiring capacitance and wiring resistance, it has been conventionally considered to use a material having a small dielectric constant for the interlayer insulating film between the wirings (Reference 1: IEICE Technical Report, SDM94-168 (1994) pp.35-40). According to Reference 1,
The gate delay time decreases with miniaturization up to the design rule (DR) of 0.5 μm CMOS, but DR =
On the contrary, if the size is further reduced to less than 0.5 μm, the delay time increases. As for the power consumption, when DR = 0.8 μm, 53.7% of the power consumption of the LSI is consumed in the wiring portion, and when DR = 0.5 μm, 67.5%, DR =
At 0.35 μm, 70.5% to 77.5% is consumed. This is a result of an increase in inter-line capacitance due to an increase in wiring density and high density. As a measure against such a problem, a low dielectric constant material is used as an interlayer insulating film in the sub-half micron region of DR = 0.35 μm.

[0004]

SUMMARY OF THE INVENTION However, LSI
As a dielectric constant material that can be used in the process, there is no suitable material having a relative dielectric constant of 2 or less. Even with SiOF, which is currently regarded as a promising material with a low dielectric constant, the relative dielectric constant is 3 to
It can only be lowered to around 3.5. In addition, although researches have been conducted on organic materials, Teflon (relative dielectric constant 1.9), which is a relatively stable organic material, has poor heat resistance and poor adhesion to other materials, making it difficult to process. Yes, L
It cannot be used for SI processes.

In addition, "Reference 2: Jpn.J.Appl.Phys., Vol.3"
3 (1994) pp.6747-6755 ", it is possible to use 3 types of MOS transistors and bipolar transistors currently used.
In addition to terminal elements, the use of 4 terminal elements is UL in the 21st century
It will be necessary to realize the SI system. When a logic circuit is configured with such multi-input elements, the number of wirings that electrically connect the elements increases, so that the capacitance between wirings and the wiring resistance further increase, and the performance of the LSI is regulated.

As described above, there is a problem that the use of metal wiring becomes difficult as the miniaturization progresses. Therefore, the emergence of a semiconductor device that solves such problems has been conventionally desired.

[0007]

According to the semiconductor element of the present invention, there is provided a first semiconductor region composed of a channel region and a photoelectric conversion region, and a gate electrode is formed above the channel region with a gate oxide film interposed therebetween. A second semiconductor region is adjacent to the channel region, and a third semiconductor region is adjacent to the photoelectric conversion region, and the second or third semiconductor region has the same conductivity type. Is a source region or a drain region.

As described above, the semiconductor region between the source region and the drain region is provided with the channel region and the photoelectric conversion region, and the gate electrode is provided on the channel region through the gate oxide film. A four-terminal element capable of controlling the current flowing between the regions by an electric signal input to the gate electrode and an optical signal input to the photoelectric conversion region is configured. Since one input of this 4-terminal element is based on an optical signal, it is possible to reduce the metal wiring density.

As a preferred embodiment of the present invention, the first
The semiconductor region and the second and third semiconductor regions are semiconductor regions of different conductivity types.

As another preferred example of the present invention, the channel region is a semiconductor region having a conductivity type different from that of the second and third semiconductor regions, and the photoelectric conversion region is in contact with the channel region. And a third semiconductor region provided in contact with each other between the fourth semiconductor region and the third semiconductor region. And a fifth semiconductor region different from each other are included in the diode structure.

Since the photoelectric conversion region has the diode structure as described above, a high ON / OFF ratio can be obtained when this semiconductor element is used as a switching element.

Further, as another preferred embodiment of the present invention, the channel region is a semiconductor region having a conductivity type different from that of the second and third semiconductor regions, and the channel region and the third semiconductor region are provided with the conductivity type. It is characterized in that the photoelectric conversion region has a transistor structure in which three sixth, seventh and eighth semiconductor regions having different conductivity types are alternately arranged.

Since the photoelectric conversion region has a transistor structure as described above, a high ON / OFF ratio can be obtained when this semiconductor element is used as a switching element, and photoelectric conversion can be performed more efficiently. become.

Further, according to the semiconductor element of the present invention, there is provided a semiconductor element having two input means for electrical input and optical input on the current path formed by the semiconductor region provided between the drain region and the source region. The AND circuit is configured by controlling ON / OFF of the current flowing through the current path between the drain region and the source region by these two inputs.

As described above, a logical product circuit is constructed which can control the current flowing through the current path between the source region and the drain region by the electrical input and the optical input.
Since one input of this AND circuit is based on an optical signal, it is possible to reduce the metal wiring density.

According to the current control method of the present invention, in controlling the current flowing through the semiconductor element with two inputs, the first input is an electrical input and the second input is an optical input. An inversion layer is formed in the first semiconductor region of the first and second semiconductor regions continuously provided between the first potential point and the second potential point having a different potential from the first potential point, With two inputs, an electron-hole pair is formed in the second semiconductor region, and the inversion layer and the electron-hole pair cooperate to form a current flowing between the first and second potential points. It is characterized by

As described above, since the current flowing between the first and second potential points can be controlled by the electric input and the optical input, it is possible to construct an element using not only the electric input but also the optical input. The metal wiring density of the integrated circuit formed by this element can be reduced.

Further, according to the current control method of the present invention, a potential gradient is formed between both ends of the semiconductor region, an inversion layer is formed in this semiconductor region by an electric input, and an electron based on photoelectric conversion is generated by a light input. Is formed so that an electric current is passed through the semiconductor region.

By such a current control method, the current flowing in the semiconductor region can be controlled by the electric input and the optical input.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the drawings only schematically show the shapes, arrangement relationships, and sizes to the extent that the present invention can be understood, and therefore the present invention is not limited to these drawings.

[First Embodiment] FIG. 1 is a sectional view showing the structure of the first embodiment. The semiconductor device of this first configuration example is manufactured by the SOI technique and is manufactured by the Si substrate 1
0 and the SiO ₂ film 12 as a base, the upper surface of the SiO ₂ film 12 is formed. A p ⁻ layer 14 which is a Si layer having a conductivity type of p ⁻ is formed on the upper surface of the SiO ₂ film 12, and a source region 16 and a drain region 18 which are n ⁺ -Si semiconductor regions are separated from each other, and the p ⁻ It is formed adjacent to the side surface of layer 14.

The first semiconductor region is the p ⁻ layer 14, and this p
^-The layer 14 is divided into a channel region 34 and a photoelectric conversion region 36. A gate electrode 26 is formed on the upper surface of the channel region 34 of the p ⁻ layer 14 with a gate oxide film 24 interposed therebetween. In addition, the second semiconductor region is used as the channel region 34.
Is provided as a source region 16 of n ⁺ conductivity type, and the third semiconductor region is formed as a drain region 18 of n ⁺ conductivity type adjacent to the photoelectric conversion region 36.

The p ⁻ layer 14, the source region 16 and the drain region 18 are used as one semiconductor element, and these are isolated from each other by element isolation layers 20 and 22.

The surface of the structure described above on which the gate electrode 26 is formed is covered with a light-transmitting surface protective film 28. Then, the surface protective film 28 of the photoelectric conversion region 36
The upper surface of is used as a light receiving window 32, and the light shielding film 30 is formed on the upper surface of the remaining surface protective film 28. When light having energy enough to generate electron-hole pairs in the p ⁻ layer 14 is incident on the channel region 34, regardless of the voltage applied to the gate electrode 26, Since a current flows between the source / drain regions, a light shielding film 30 is provided to prevent the channel region 34 below the gate electrode 26 from being irradiated with light. This light-shielding film 3
The light receiving window 32 of 0 should have a wide area in order to increase the sensitivity to light, but it may be at least as wide as the wavelength of light. In short, it suffices that the photoelectric conversion region 36 has an element structure capable of inputting a light input.

Element isolation layers 20 and 22 and surface protective film 2
As 8, a SiO ₂ , SiOF, silicon nitride film or organic insulating film is used. Further, in this embodiment, the gate oxide film 24 is made of SiO ₂ and the gate electrode 2
6 is polysilicon. Further, TiN or the like is used as the light shielding film 30.

11 and 12 are cross-sectional views for briefly explaining an example of the manufacturing process of the semiconductor device of this configuration example. First, with the Si substrate 10 and the SiO ₂ layer 12 as a base, a Si layer 64 is formed on the upper surface of the SiO ₂ layer 12 to form a laminated body 62 of three layers ((A) of FIG. 11). Next, the SiO ₂ layer 5 is formed on the upper surface of the planned region to become the channel region 34 and the photoelectric conversion region 36 of the Si layer 64.
6 and the SiN layer 58 are formed in this order ((B) of FIG. 11). Using the SiO ₂ layer 56 and the SiN layer 58 as a mask 60, the exposed Si layer 64 is oxidized to form the element isolation layers 20 and 22 ((C) of FIG. 11). Next, the mask 60 is removed, and an impurity such as P or As is introduced into the exposed remaining region of the Si layer 64 by ion implantation to remove the source region 16 and the drain region 1.
8 is formed. Further, the p ⁻ layer 14 is formed in the intermediate region between these regions 16 and 18 by implanting B, for example ((D) of FIG. 11).

Next, a SiO ₂ layer to be the gate oxide film 24 and a polysilicon layer to be the gate electrode 26 are deposited on the upper surface of the region of the p ⁻ layer 14 to be the channel region 34 by, eg, CVD method. ((A) of FIG. 12). Then, SiO 2 is formed on the upper surface side of the structure formed by the above steps.
_Two layers are formed by a CVD method to form a surface protective film 28, and a light shielding film 3 having a light receiving window 32 formed by further forming a TiN layer on the upper surface of the surface protective film 28 and processing it.
0 is formed ((B) of FIG. 12).

FIG. 2 is a schematic structural diagram for explaining the operation of the semiconductor device of the present invention. This semiconductor device is shown in FIG.
Wired as shown in. In this example, the source region 16 is connected to the ground point, that is, the first potential point,
The drain region 18 is connected to the second potential point on the high potential side so that the voltage V ₂ can be applied between the source region 16 and the drain region 18. Further, the gate electrode 26 is configured so that an electric input as a first input can be input, and in the illustrated example, the gate electrode 26 is connected to the control signal source 70. Therefore, the control voltage V ₁ is applied between the gate electrode 26 and the Si substrate 10 with the gate electrode 26 on the high potential side. The voltage V ₁ applied to the gate electrode 26 induces an inversion layer 38 having a conductivity type of n in the region (that is, the channel region 34) in the p ⁻ layer 14 below the gate electrode 26. The inversion layer 38 is
It is mainly formed on the gate electrode side of the p ⁻ layer 14. Electrons flow into the inversion layer 38 from the source region 16 by the applied voltage V ₂ . However, in the semiconductor device of this configuration example, the inversion layer 38 is formed by penetrating the p ⁻ layer 14 which is the first semiconductor region from the source region (n ⁺ layer) 16 to the drain region (n ⁺ layer) 18. Instead, it is formed only in the region of the lower portion of the gate electrode 26. Therefore, since the photoelectric conversion region 36 exists in the p ⁻ layer 14 between the channel region 34 in which the inversion layer 38 is formed and the drain region 18, when the light is not incident on this region, the source region is formed. The electrons flowing out of 16 cannot reach the drain region 18, and no current flows between the first potential point and the second potential point, that is, the current path between the source and drain regions. Therefore, here, the photoelectric conversion region 36 acts as a kind of separation region.

By the way, it is assumed that an optical input as the second input is inputted to the photoelectric conversion region 36 through the light receiving window 32. When light having an energy higher than the band gap energy of Si (1.12 eV) is incident as this light input, electron-hole pairs are generated in the photoelectric conversion region 36 as shown in FIG. The charge between 38 and drain region 18 is allowed to move. Fig. 3, p ^-
It is the figure which showed the energy band of the layer 14 typically. The two lines a and b respectively show the energy state, the vertical direction of the figure represents the height of energy, and the energy increases upward. Further, the horizontal direction of the drawing shows the horizontal position of the p ⁻ layer 14 in the cross section of FIG. 1, and the low energy side is the drain region 14 and the high energy side is the inversion layer 38.

In FIG. 3, the region below the line a shows the valence band and the region above the line b shows the conduction band. The band gap is shown between the lines a and b, and the dotted line c shows the Fermi level. Black circles represent electrons and white circles represent holes. When light having energy hν higher than the band gap energy is incident on this system shown in FIG. 3, electron-hole pairs are generated. Due to the voltage applied between the drain region 18 and the source region 16, the generated electron-hole pairs have electrons drawn to the drain region 18 side and holes drawn to the inversion layer 38, that is, the source region 16 side, Therefore, charges can be moved, a current flows in the current path between the source and drain regions, and an output of this semiconductor element is generated (ON state).

When the voltage applied to the gate electrode 26 is large enough not to form the inversion layer 38, the inversion layer is not formed even if light of a predetermined energy is incident on the photoelectric conversion region 36, Further, since light does not enter the channel region below the gate electrode 26, no electron current flows in the current path between the source and drain (OFF).
Status). Therefore, in this case, the channel region 34 acts as a separation region.

In this case, only the drift current is generated by the holes of the electron-hole pairs generated in the photoelectric conversion region 36, and the current flowing is small because there is no contribution by the electron current. Therefore, the on / off ratio (ON / OFF) of this switching element depends on the increase due to the electron current.
By setting the threshold value so as to judge the (ratio), the semiconductor element of this configuration example functions as an AND logic circuit for the electric input and the optical input. As described above, when the source region 16 and the drain region 18 are in different potential states, an inversion layer 38 is formed in the channel region 34 by an electric input, and an electron-hole pair is formed in the photoelectric conversion region 36 by an optical input to invert. The layer 38 and the electron-hole pairs together form a current flow between the source region 16 and the drain region 18, and thus the current path between the first potential point and the second potential point.

According to the semiconductor element of the first configuration example described above, one element has two input means for inputting an electric signal and inputting an optical signal, and an AND logic circuit is provided for these inputs. Make up. Thus, since the input path for the optical signal is secured, a part of the signal path can be replaced with the signal path by light from the metal wiring. Therefore, it is possible to reduce the density of the metal wiring of the integrated circuit configured by using this semiconductor element, and it is possible to suppress the increase of the wiring capacitance and wiring resistance.

An example of usage of this semiconductor element will be described. FIG. 4 is a cross-sectional view showing the configuration of a circuit configured using the semiconductor device of the present invention. The semiconductor element 4 of the present invention is provided on one of the LSI chips or the circuit board 40a.
2 is placed. Timing signal sources for executing respective circuit operations are connected to the gate electrodes of these semiconductor elements 42. In addition, these semiconductor elements 4
LSI chip or circuit board 40a on which 2 is arranged
The light-emitting element 44 is arranged on the upper surface so as to face L
An SI chip or circuit board 40b is provided. Thus, the semiconductor element 42 is provided between the substrates 40a and 40b.
And the light emitting element 44 face each other. In order to control the light emission timing of these light emitting elements 44,
A signal synchronized with the aforementioned timing signal is input.
As the light emitting element 44, for example, a light emitting diode or a laser diode is used. In this way, by disposing the semiconductor element 42 and the light emitting element 44 on different substrates and facing each other, signals are exchanged between these substrates (upper and lower sides in the drawing).

In the integrated circuit using the semiconductor element 44 of this usage mode, N types of signals can be transmitted in the same space by preparing timing signals for the number N of signal transmission systems. Therefore, when there are a plurality of transmission systems, it is possible to easily secure a necessary signal path by controlling the electric signal and the optical signal with an appropriate timing signal. In this way, even if the number of signal paths is increased, the influence of the inter-wiring capacitance can be suppressed by replacing the long-distance wirings or the portions where the wirings intersect with each other with the optical signals.

[Second Embodiment] FIG. 5 is a sectional view showing the structure of the second embodiment. The second configuration example is a configuration example in which the photoelectric conversion region 36 described in the first embodiment is formed as a diode structure. In this second configuration example, the channel region 34 is a semiconductor region having a conductivity type different from the conductivity types of the source region 16 and the drain region 18 which are the second and third semiconductor regions. Then, a diode structure 66 formed by the fourth semiconductor region 48 and the fifth semiconductor region 46 is formed between the channel region 34 and the drain region 18 which is the third semiconductor region.
As a matter of course, the conductivity type of the fourth semiconductor region 48 in contact with the channel region 34 is different from that of the channel region 34, and the fifth semiconductor region 4 in contact with the drain region 18 is formed.
The conductivity type of 6 is different from that of the drain region 18. Thus, in the configuration example shown in FIG. 5, n ⁺ source region 16, the channel region 34 p ^- layer 14, n ⁺ layer 48 as the fourth semiconductor region, p as a fifth semiconductor region ^-
The layer 46 and the n ⁺ drain region 18 are in contact with each other in sequence.

Thus, p ⁻ layer 46 is provided adjacent to drain region 18, and n ⁺ layer 48 is in contact with each region between p ⁻ layer 46 and channel region 34.
Are formed, and these p ⁻ layer 46 and n ⁺ layer 48 are formed.
To form a diode structure 66. A light receiving window 32 is provided in the light shielding film 30 so that light is incident on the p ⁻ layer 46. The second configuration example is
As described in the first embodiment, it can be formed by an ordinary semiconductor microfabrication technique, and thus the description of the manufacturing process is omitted.

Next, the operation of this second configuration example will be described. FIG. 6 is a schematic structural diagram for explaining the operation of the semiconductor device having this configuration. The connection and voltage application are performed in the same manner as in the first configuration example, and thus the description thereof is omitted. When a voltage of a predetermined magnitude is applied as the first input to the gate electrode 26, the inversion layer 38 is formed mainly on the gate electrode side in the p ⁻ layer which is the channel region 34. At this time,
The source region 16 and the n ⁺ layer 48 are electrically connected by this inversion layer 38, and an electron path is formed. Therefore, the electrons flowing out of the source region 16 can reach the n ⁺ layer 48 through the inversion layer 38. However, these electrons cannot reach the drain region 18 because there is usually an energy barrier formed by the pn junction between the n ⁺ layer 48 and the p ⁻ layer 46.

FIGS. 7A, 7B and 7C are diagrams showing the energy states of the layers arranged between the channel region 34 and the drain region 18. The horizontal direction of the figure is
The position of each of these layers between the channel region 34 and the drain region 18 is shown. The high potential side (the side indicated by the symbol + in the figure) is the drain region 18, and the low potential side (the side indicated by the symbol − in the figure) is the channel region 34. Further, the vertical direction in the drawing represents the height of energy, and the upper side represents the high energy state.

First, the energy state of FIG. 7A is when the voltage is applied to the gate electrode 26 to form the inversion layer 38, and the photoelectric conversion region 36 receives light as the second input. Is the energy state when is not incident. Since there is an energy barrier between the n ⁺ layer 48 and the p ⁻ layer 46, electrons in the conduction band cannot move to the drain region 18 side beyond the barrier.

The energy state shown in FIG. 7B corresponds to the inversion layer 3
8 is formed, and light having a predetermined energy (energy higher than the band gap) is incident on the photoelectric conversion region 36. At this time, electron-hole pairs are generated in the p ⁻ layer 46, and the recombination process is performed in the energy barrier portion, so that the charge transfer between the channel region 34 and the drain region 18 becomes possible. Therefore, a current is formed in the current path between the source region 16 and the drain region 18, and the output of this semiconductor element is generated.

The energy state in FIG. 7C is the inversion layer 3
8 is not formed, but is the case where light having a predetermined energy is incident on the photoelectric conversion region 36. In such a case, even if an electron-hole pair is generated in the p ⁻ layer 46, the electron cannot move due to the energy barrier at the junction surface between the channel region 34 and the n ⁺ layer 48, and the positive electron cannot move. N ⁺ layer 48 and p ⁻ layer 4 for the holes
The source region 16 and the drain region 1 cannot move due to the energy barrier at the interface between the 6 and 6.
No current flows between eight.

According to the second configuration example described above, in addition to the effect of the first configuration example described above, the photoelectric conversion region 3 is provided.
Since 6 has a diode structure (photodiode structure) 66, when no voltage is applied to the gate electrode 26 and the inversion layer 38 is not formed, the photoelectric conversion region 36 is formed.
The hole current does not flow even when there is light irradiation. Therefore, the ON / OFF ratio of the switching element can be increased.

[Third Embodiment] FIG. 8 is a sectional view showing the structure of a semiconductor device according to the third embodiment. The third configuration example is a configuration in which the photoelectric conversion region has a transistor structure. In this example, the conductivity type of the channel region 34 is different from that of the second and third semiconductor regions 16 and 18. And the channel region 3
Three semiconductor regions, that is, the sixth, seventh and eighth semiconductor regions 52, 54 and 50, which are sequentially different between the drain region 18 which is the fourth semiconductor region and the third semiconductor region, are alternately arranged, and transistors are formed in these three semiconductor regions. The structure 68 is formed.

The photoelectric conversion region 36 of this configuration example is formed by alternately connecting three semiconductor regions having different conductivity types. First, the n ⁻ layer 50 as the eighth semiconductor region is provided adjacent to the drain region 18. Then, an n ⁺ layer 52 as a sixth semiconductor region is formed between the channel region 34 and the drain region 18 so as to be connected to the channel region 34. A p layer 54 serving as a seventh semiconductor region is formed between the n ⁻ layer 50 and the n ⁺ layer 52 in contact with the respective regions. Then, the light receiving window 32 is formed in the light shielding film 30 so that the light is incident on the p layer 54 and the n ⁻ layer 50.
Is provided. As described above, the photoelectric conversion region 36 in the third configuration example has a transistor structure, particularly a phototransistor structure. The n ⁺ layer 52 is the emitter, the p layer 54 is the base, the n ⁻ layer 50 and the drain region 18 are formed. Works as a collector.

Since the third example of the structure can be formed by the usual semiconductor fine processing technique as shown in the first embodiment, the description of the manufacturing process is omitted.

Next, the operation of the third configuration example will be described. FIG. 9 is a schematic structural diagram for explaining the operation of the semiconductor device having this configuration. The connection and the voltage application are performed in the same manner as in the first and second configuration examples, and thus the description thereof will be omitted.

When a predetermined voltage V ₁ is applied to the gate electrode 26 as the first input, the inversion layer 38 is formed in the region of the channel region 34 on the gate electrode 26 side. At this time, the source region 16 and the n ⁺ layer 52 are
Are electrically connected to each other to form an electron passage. Therefore, the electrons flowing out from the source region 16 can reach the n ⁺ layer 52 through the inversion layer 38. However, normally, between the n ⁺ layer 52 and the p layer 54,
These electrons cannot reach the drain region 18 because of the energy barrier resulting from the pn junction. Therefore, in this case, the semiconductor regions 14, 52, 54 and 50 are formed between the region 16 and the region 18 which are connected between the first potential point on the ground side and the second potential point on the high potential side. No output is taken because no electron flow through the created current path is formed.

FIGS. 10A, 10B and 10C show
FIG. 6 is a diagram showing energy states of respective layers arranged between the channel region 34 and the drain region 18. The horizontal direction in FIG. 10 represents the position of each of these layers between the channel region 34 and the drain region 18. The high potential side (the side indicated by the symbol + in the figure) is the drain region 18, and the low potential side (the side indicated by the symbol − in the figure is the channel region 34. Also, the vertical direction in the figure indicates the height of energy. Is represented.

The energy state of FIG. 10A is the case where a voltage is applied to the gate electrode 26 to form the inversion layer 38, and light as the second input is incident on the photoelectric conversion region 36. This is the energy state when not in use. Since there is an energy barrier between the n ⁺ layer 52 and the p layer 54 in this way, electrons in the conduction band cannot move over the energy barrier to the drain region 18 side. Therefore, no current flows between the source region 16 and the drain region 18.

In the energy state of FIG. 10B, the inversion layer 3 is changed by the voltage (first input) applied to the gate electrode 26.
8 is formed and light (second input) having a predetermined energy (energy larger than bandgap energy) is incident on the photoelectric conversion region 36. At this time, electron-hole pairs are generated in the semiconductor region extending from the p layer 54 to the n ⁻ layer 50, the recombination process is performed in the previous energy barrier portion, and charge transfer between the channel region 34 and the drain region 18 is performed. Will be possible. Therefore, a flow of electrons is formed through the current path between the source region 16 and the drain region 18, causing a current to flow and producing an output.

The energy state of FIG. 10C is the case where the inversion layer 38 is not formed, but is the case where light having a predetermined energy is incident on the photoelectric conversion region 36.
At this time, electron-hole pairs are generated in the semiconductor region extending from the p layer 54 to the n ⁻ layer 50, but electrons cannot move due to the energy barrier at the junction surface between the channel region 34 and the n ⁺ layer 52, N ⁺ layer 5 for holes
No current flows in the current path between the channel region 34 and the drain region 18 because it cannot move due to the energy barrier at the junction surface between the 2 and the p layer 54.

According to the third configuration example described above, in addition to the effects of the first and second configuration examples described above, the photoelectric conversion region 36 has a transistor structure (phototransistor structure), so that it is efficient. It converts photons into electrons and also amplifies the number of electrons. Therefore, the light intensity reaching the photoelectric conversion region 36 of the semiconductor element from the outside is weak, such as when the light emitting element must be arranged at a position far from the semiconductor element or when the light emitting intensity of the light emitting element is weak. Even in the case, the signal can be efficiently transmitted.

As described above, according to the semiconductor elements of the first, second and third configuration examples, it becomes possible to transmit signals in the integrated circuit not only by using the metal wiring but also by using the optical wiring. Thus, high integration of the device can be realized while minimizing the signal delay and the increase in power consumption. As described above, the wiring system including the metal wiring and the interlayer insulating film replaces the conventional semiconductor element that deteriorates the performance of the LSI, and by adopting the semiconductor element of the present embodiment, it is possible to configure the semiconductor element from these semiconductor elements. The performance of the LSI to be manufactured can be effectively exhibited without deterioration. In addition, in an integrated circuit using such a semiconductor element, it is possible to perform wiring that is strong against electrical crosstalk and noise.

Furthermore, the function of the logic circuit formed by the semiconductor device of this embodiment can be made different by changing the timing signal. As described above, signals are not exchanged by electric wires or optical fibers, but signals are transmitted by synchronizing the timing signals of the semiconductor element and the light emitting element of the present invention. By changing it, a logic circuit having a different function can be easily obtained.

In the first, second and third configuration examples, the example using the SOI substrate formed by the SOI technique is shown, but a semiconductor element having a thin film transistor (TFT) structure may be used. Further, the case where the conductivity type of the inversion layer 38 formed in the channel region is the n-type has been described.
Even if it is p-type, a semiconductor element having the same effect can be obtained by appropriately setting the conductivity type of another semiconductor region.
In particular, in the third configuration example, the transistor structure formed in the photoelectric conversion region 36 has the npn structure, but it may have the pnp structure.

In the above embodiment, Si-LS is used.
Although the configuration example of I has been shown, the invention is not limited to this.
Other semiconductor materials such as Ge, SiGe, GaAs,
It is also possible to apply to GaP, InP, and GaAlAs.

[0058]

According to the semiconductor element of the present invention, the semiconductor region between the source region and the drain region has a channel region and a photoelectric conversion region, and a gate electrode is provided on the channel region via a gate oxide film. This makes it possible to configure a semiconductor element in which the current flowing between the source region and the drain region can be controlled by the electrical signal input to the gate electrode and the optical signal input to the photoelectric conversion region. Therefore, since one input of this semiconductor element is an input by an optical signal, it is possible to reduce the metal wiring density in the integrated circuit, and thus L
It is possible to obtain a remarkable effect that it is possible to reduce the influence of the inter-wiring capacitance and the wiring resistance on the operation such as SI.

[Brief description of drawings]

FIG. 1 is a diagram showing a first configuration example.

FIG. 2 is a diagram for explaining the operation of the first configuration example.

FIG. 3 is a diagram for explaining the operation of the first configuration example.

FIG. 4 is a diagram showing a usage example of a semiconductor element.

FIG. 5 is a diagram showing a second configuration example.

FIG. 6 is a diagram for explaining the operation of the second configuration example.

7A to 7C are diagrams for explaining the operation of the second configuration example.

FIG. 8 is a diagram showing a third configuration example.

FIG. 9 is a diagram for explaining the operation of the third configuration example.

10A to 10C are diagrams for explaining the operation of the third configuration example.

11A to 11D are cross-sectional views showing the manufacturing process of the first configuration example.

12A and 12B are cross-sectional views showing the manufacturing process of the first configuration example following FIG.

[Explanation of symbols]

10: Si substrate 12: SiO ₂ layer 14: p ^- layer 16: Source region 18: Drain region 20, 22: Element isolation layer 24: Gate oxide film 26: Gate electrode 28: Surface protection film 30: Light-shielding film 32: Light reception Window 34: Channel region 36: Photoelectric conversion region 38: Inversion layer 40a, 40b: LSI chip or circuit board 42: Semiconductor device 44: Light emitting device 46: p ⁻ layer 48, 52: n ⁺ layer 50: n ⁻ layer 54: p layer 56: SiO ₂ layer 58: SiN layer 60: mask 62: laminated body 64: Si layer 66: diode structure 68: transistor structure 70: control signal source

Claims (7)

[Claims] 1. A first semiconductor region composed of a channel region and a photoelectric conversion region, a gate electrode provided above the channel region with a gate oxide film interposed, and a second semiconductor adjacent to the channel region. And a third semiconductor region adjacent to the photoelectric conversion region and spaced apart from each other, and the second or third semiconductor region is a source region or a drain region of the same conductivity type. Semiconductor device. 2. The semiconductor device according to claim 1, wherein the first semiconductor region and the second and third semiconductor regions are semiconductor regions of different conductivity types. 3. The semiconductor element according to claim 1, wherein the channel region is a semiconductor region having a conductivity type different from that of the second and third semiconductor regions, and the photoelectric conversion region is the channel region. A fourth semiconductor region provided in contact with the channel region and having a conductivity type different from that of the channel region, and a third semiconductor region provided in contact with each other between the fourth semiconductor region and the third semiconductor region are electrically conductive. A semiconductor device comprising a diode structure composed of a fifth semiconductor region of a different type. 4. The semiconductor device according to claim 1, wherein the channel region is a semiconductor region having a conductivity type different from the conductivity types of the second and third semiconductor regions, and the channel region and the third semiconductor region are separated from each other. A semiconductor device comprising the photoelectric conversion region having a transistor structure in which three sixth, seventh and eighth semiconductor regions having different conductivity types are alternately arranged. 5. A semiconductor device having two input means for electrical input and optical input on a current path composed of a semiconductor region provided between a drain region and a source region, wherein the drain region and the A semiconductor device comprising an AND circuit by controlling ON / OFF of a current flowing through the current path between the source regions. 6. When controlling a current flowing through a semiconductor element with two inputs, a first input is an electric input and a second input is an optical input, and the first input is a first potential point and the first potential. The first point is continuously provided between the second potential points having different potentials.
And an inversion layer is formed in the first semiconductor region of the second semiconductor region, and an electron-hole pair is formed in the second semiconductor region at the second input, and the inversion layer and the electron-hole pair are formed. And a current controlling method for forming a current flowing between the first and second potential points together. 7. A potential gradient is formed between both ends of the semiconductor region, an inversion layer is formed in the semiconductor region by an electric input, and electrons based on photoelectric conversion are formed by a light input, whereby the semiconductor region is formed. A method of controlling current, characterized by flowing an electric current.