JPH09223732A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable formation of fine and reliable connection holes to a wiring layer in a self-aligned manner while enabling reduction of an area necessary for the connection holes and wiring layer. SOLUTION: A polycide layer 15, an SiO2 film 24 and polycrystalline Si film 25 are sequentially deposited, processed into a gate electrode pattern, on which an SiO2 film 16 are then deposited. An opening 16a is formed so as to partially overlap a polycide layer 15 or the like, a side wall spacer composed of an SiO2 film 21 is formed on an inner wall of the opening 16a, thereby forming a connection hole 22. Therefore, at the time of forming the opening 16a, the polycrystalline Si film 25 acts as an etching stopper and the SiO2 film 24 isolates the polycide layer 15 from an polycrystalline Si film 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which a connection hole is formed in a wiring layer in a self-aligned manner.

[0002]

2. Description of the Related Art A self-aligned connection technique which eliminates the need for an alignment margin between a wiring layer and a connection hole by forming a connection hole in a wiring layer in a self-aligned manner has been developed with the miniaturization of semiconductor devices. Is becoming important. Further, it is also considered that the areas required for the connection hole and the wiring layer are reduced by planarly overlapping a part of the connection hole and the wiring layer.

FIG. 3 shows a conventional example of a method of manufacturing a semiconductor device having such a connection hole. In this conventional example, as shown in FIG. 3A, after a SiO ₂ film 12 as a gate oxide film is formed on the surface of a Si substrate 11, a polycrystalline Si film 13 and a WSi _x film 14 are sequentially formed. The polycide layer 15 is deposited to form a polycide layer 15, and the polycide layer 15 is processed into a pattern of a gate electrode.

After that, the SiO ₂ film 1 as an interlayer insulating film is formed.
6 is deposited by a CVD method, and a photoresist 17 having an opening 17a at a position where a connection hole is to be formed is formed into a SiO ₂ film 16
Form on top. Then, as shown in FIG. 3B, the SiO ₂ film 1 is formed by etching using the photoresist 17 as a mask.
After forming the opening 16a in 6, the photoresist 17 is removed.

Next, as shown in FIG. 3C, a SiO ₂ film 21 is deposited by the CVD method. Then, the SiO ₂ film 21
The entire surface of Si is etched back, and as shown in FIG.
A side wall spacer made of the O ₂ film 21 is formed in the opening 16a, and the connection hole 22 surrounded by the SiO ₂ film 21 is formed in self-alignment with the polycide layer 15. afterwards,
As shown in FIG. 3E, a wiring that connects to the Si substrate 11 through the connection hole 22 is formed of the polycrystalline Si film 23 containing impurities.

[0006]

However, in the above-mentioned conventional example, as is apparent from FIGS. 3D and 3E, the connection hole 22 and the polycide layer 15 are partially overlapped in a plane. Then, there is a portion where the SiO ₂ film 21 which is the sidewall spacer does not remain on the polycide layer 15, and there is a possibility that the polycide layer 15 and the polycrystalline Si film 23 are short-circuited at this portion, and the reliability of the semiconductor device is increased. Was falling.

[0007] By increasing the film thickness of the SiO ₂ film 21 is deposited by a CVD method, an SiO ₂ film 21 serving as the sidewall spacers
Is also widened, and the SiO ₂ film 21 can easily cover the polycide layer 15. However, if the SiO ₂ film 21 is deposited so thick as to fill the opening 16 a, the connection hole 22 cannot be formed in self-alignment with the polycide layer 15.

On the other hand, if the diameter of the opening 16a is increased, the opening 16a is not filled with the SiO ₂ film 21 even if the thick SiO ₂ film 21 is deposited. However, if the diameter of the opening 16a is increased, the diameter of the connection hole 22 is also increased.
A fine semiconductor device cannot be manufactured. That is,
In the above-mentioned conventional example, it is difficult to manufacture a fine and highly reliable semiconductor device.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein an insulating film is formed on a first wiring layer, and a material film having etching selectivity with respect to an interlayer insulating film is formed on the insulating film. The interlayer insulating film is formed on the material film, and the interlayer insulating film is formed on the material film.

The method of manufacturing a semiconductor device according to a second aspect is characterized in that an insulating material film having etching selectivity and insulating property with respect to the interlayer insulating film is used instead of the insulating film and the material film.

In the method for manufacturing a semiconductor device according to the first aspect, the insulating film is formed on the first wiring layer, and the material film having etching selectivity with respect to the interlayer insulating film is formed on the insulating film. The insulating film remains on the first wiring layer even when the openings formed in the interlayer insulating film at the positions where the holes are to be formed and the first wiring layer are partially overlapped with each other in plan view.

Therefore, a part of the connection hole and the first wiring layer can be planarly overlapped with each other, and the area required for the connection hole and the first wiring layer can be reduced. Regardless, even if the diameter of the opening is small and the width of the insulating side wall spacer is narrow, it is possible to secure the withstand voltage between the first wiring layer and the second wiring layer in the connection hole, and it is fine. Moreover, a highly reliable connection hole can be formed in a self-aligned manner with respect to the first wiring layer.

In the method of manufacturing a semiconductor device according to the second aspect, the insulating material film having etching selectivity and insulating property with respect to the interlayer insulating film is used instead of the insulating film and the material film. It requires less patterning steps.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to FIGS. In this embodiment, as shown in FIG. 1A, after a SiO ₂ film 12 as a gate oxide film is formed on the surface of a Si substrate 11, a polycrystalline Si film 13, a WSi _x film 14, and a SiO ₂ film 24 are formed. Then, the polycrystalline Si film 25 is sequentially deposited. The deposition of the polycrystalline Si film 25 is performed under the following conditions, for example.

Conditions for depositing polycrystalline Si film Apparatus: low pressure CVD apparatus Gas: SiH ₄ / He / N ₂ = 100/400/200
sccm pressure; 70 Pa temperature; 610 ° C.

Then, a photoresist 26 having a gate electrode pattern is formed on the polycrystalline Si film 25, and the photoresist 26 is used as a mask to form the polycrystalline Si film 25, Si.
The polycide layer 15 composed of the O ₂ film 24, the polycrystalline Si film 13, and the WSi _x film 14 is dry-etched under the following conditions.

Etching conditions for polycrystalline Si film Equipment; ECR etching equipment Gas; Cl ₂ / O ₂ = 10/5 sccm Pressure; 0.1 Pa High frequency output; 50 W Microwave output; 350 W

SiO ₂ film etching conditions Apparatus; ECR etching apparatus Gas; Cl ₂ / O ₂ / SF ₆ = 5/2/50 sccm Pressure; 0.1 Pa High frequency output; 150 W Microwave output; 350 W

Polycide layer etching conditions Equipment; ECR etching equipment Gas; Cl ₂ / O ₂ = 10/5 sccm Pressure; 0.1 Pa High frequency output; 50 W Microwave output; 350 W

Next, as shown in FIG. 1B, the photoresist 26 is removed, and the SiO ₂ film 16 as an interlayer insulating film is removed.
After being deposited under the following conditions, a photoresist 17 having an opening 17a at a position where a connection hole is to be formed is formed on the SiO ₂ film 16. The openings 17a partially overlap with the polycide layer 15 and the like in plan view.

Conditions for depositing SiO ₂ film Device: atmospheric pressure CVD device Gas: SiH ₄ / O ₂ / N ₂ = 100/500/100
0sccm temperature; 410 ° C

Next, as shown in FIG. 1C, the polycrystalline Si film 2 is formed so that the photoresist 17 can be used as a mask and the polycrystalline Si film 25 can be used as an etching stopper.
5, the photoresist 17 is removed after the opening 16a is formed in the SiO ₂ film 16 by etching under the condition that a large etching selection ratio can be secured, for example, the following condition.

SiO ₂ film etching conditions Device: Single-wafer type magnetron RIE device Gas; CHF ₃ / O ₂ = 50/50 sccm Pressure; 5.3 Pa High frequency output; 1600 W Susceptor temperature; 20 ° C.

Next, as shown in FIG. 2A, a SiO ₂ film 21 is deposited under the following conditions. Conditions for depositing SiO ₂ film Apparatus; low pressure CVD apparatus Gas; TEOS / N ₂ = 50/5 sccm Pressure; 80 Pa temperature; 720 ° C.

Next, the entire surface of the SiO ₂ film 21 is etched back under the following conditions to form a side wall spacer made of the SiO ₂ film 21 in the opening 16a as shown in FIG. 2B.
The contact hole 22 surrounded by the SiO ₂ film 21 is formed in self-alignment with the polycide layer 15.

Etchback conditions for SiO ₂ film Device: Single-wafer type magnetron RIE device Gas: CHF ₃ / O ₂ = 40/10 sccm Pressure: 2.7 Pa High frequency output; 1600 W Susceptor temperature; 20 ° C.

Next, as shown in FIG. 2C, a polycrystalline Si film 23 containing impurities is deposited under the following conditions, the polycrystalline Si film 23 is patterned, and via the connection hole 22. Wirings connected to the Si substrate 11 are formed.

Conditions for depositing polycrystalline Si film Apparatus: low pressure CVD apparatus Gas: SiH ₄ / PH ₃ / He = 500/25 / 30s
ccm pressure; 70 Pa temperature; 610 ° C.

In this embodiment as described above, since the SiO ₂ film 24 is formed on the polycide layer 15, the structure shown in FIG.
As is clear from (b) and (c), part of the contact hole 22 and the polycide layer 15 are planarly overlapped with each other, and the SiO ₂ film 21 serving as the sidewall spacer remains on the polycrystalline Si film 25. Even if there is a portion that does not exist, it is possible to prevent a short circuit between the polycide layer 15 and the polycrystalline Si film 23 in this portion.

Therefore, it is not necessary to increase the film thickness when depositing the SiO ₂ film 21 for forming the sidewall spacer by the CVD method, and the opening 16a cannot be filled with the SiO ₂ film 21. Thus, the connection hole 22 can be formed in self-alignment with the polycide layer 15. Therefore, SRAM and DRAM and ASICs equipped with these
As described above, it is possible to favorably manufacture a semiconductor device that requires particularly miniaturization.

In the above embodiment, the SiO ₂ film 1 is used.
Although the polycrystalline Si film 25 is used as an etching stopper when the opening 16a is formed in 6, the amorphous Si film or the cypos film which is a semi-insulating polycrystalline Si film having a large oxygen content is used. A film having a high Si composition ratio, a silicide film such as a tungsten silicide film or a titanium silicide film, a metal film such as a tungsten film, or the like may be used instead of the polycrystalline Si film 25.

In the above embodiment, the SiO ₂ film 24 as the insulating film and the polycrystalline Si film 2 as the stopper layer are used.
However, if there is an insulating film that can serve as a stopper layer in a single layer, this insulating film may be used instead of the SiO ₂ film 24 and the polycrystalline Si film 25.

In the above-described embodiment, the invention of the present application is applied to the manufacture of the semiconductor device having the connection hole 22 for connecting the polycrystalline Si film 25 which is the wiring and the Si substrate 11. The invention of the present application can be applied to the manufacture of a semiconductor device having a connection hole for connecting wirings.

[0034]

According to the method of manufacturing a semiconductor device of the first aspect,
Although the area required for the connection hole and the wiring layer can be reduced, a fine and highly reliable connection hole can be formed in a self-aligned manner with respect to the wiring layer. A highly reliable semiconductor device can be manufactured.

In the method of manufacturing a semiconductor device according to the second aspect of the present invention, since the film deposition process and the patterning process can be reduced, a fine and highly reliable semiconductor device can be manufactured at low cost.

[Brief description of drawings]

FIG. 1 is a side sectional view sequentially showing a first half of an embodiment of the present invention.

FIG. 2 is a side sectional view sequentially showing the latter half of one embodiment.

FIG. 3 is a side sectional view sequentially showing one conventional example of the invention of the present application.

[Explanation of symbols]

11 Si substrate 15 Polycide layer 1
6 SiO ₂ film 16a Opening 21 SiO ₂ film 2
2 Connection hole 23 Polycrystalline Si film 24 SiO ₂ film 2
5 Polycrystalline Si film

Claims (2)

[Claims] 1. A connection for connecting between a first wiring layer and a conductive region lower than the first wiring layer and a second wiring layer higher than the first wiring layer. After forming an opening in the interlayer insulating film at the position where the hole is to be formed, an insulating sidewall spacer is formed in the opening to form the connection hole in a self-aligned manner with respect to the first wiring layer. In the method for manufacturing a semiconductor device, an insulating film is formed on the first wiring layer, and a material film having etching selectivity with respect to the interlayer insulating film is formed on the insulating film. A method of manufacturing a semiconductor device, comprising forming the interlayer insulating film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an insulating material film having etching selectivity and insulating property with respect to the interlayer insulating film is used instead of the insulating film and the material film. .