JPH09223071A - Address conversion control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the address conversion processing speed by performing the requested address conversion processing via the fetching of a page describer and by controlling an address conversion mechanism when a TLB(translation lookaside buffer) has a mishit. SOLUTION: An associative TLB 19 consists of a directory part 2, a matching detection part 3, a 1st selection circuit 4, a data A part 5, a data B part 6 and a data C part 7. Then, an address conversion mechanism is added to convert a logical address into the physical address. If the TLB 19 is indexed by an optional logical address and has a mishit, when the segment number included in a logical address registered in the TLB 19 matches with the segment number included in the optional logical address, a page describer corresponding to the matched segment number is fetched and the optional logical address is converted into the physical address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation control circuit, and more particularly to an address translation control circuit that controls an address translation mechanism when an address translation buffer misses.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram showing a conventional address translation control circuit. In the figure, in an address conversion control circuit in an information processing apparatus adopting a virtual memory system, a TLB (address conversion buffer; hereinafter referred to as TLB) 54 that holds a pair of a logical address and a physical address that have been once converted in address. An address translation control memory circuit 64 that controls address translation when the TLB 54 misses, a logical address register 51 that holds the logical address of the first request, and a logical address of the next request in the logical address register 51. A logical address slip register 52 that holds the logical address of the first request when it is held, and TL at the logical address
A TLB hit search circuit 57 for indexing B54 and searching for a TLB hit, a TLB miss hit flag means 58 for indicating a TLB miss, and a logical address comparison circuit for performing a match comparison between the logical address of the first request and the logical address of the next request. 56, and a match detection circuit 66 for performing a match comparison between the segment number in the logical address of the first request and the segment number of the logical address of the next request,
Next request TLB miss hit flag means 59 indicating that the logical address of the first request and the logical address of the next request are different pages and that the first request and the next request both have a TLB miss hit, and the logical address of the first request And a logical address of the next request are in the same segment, a match flag 67 indicating that the first request and the next request both have a TLB miss, a running flag 62 indicating that the address conversion process is in progress, and an address conversion An address register 63 for holding the address of the control storage circuit 64, a start address holding register 61 for holding the start address of the address conversion control storage circuit 64 for the next request during the address conversion processing for the first request, and the address conversion control storage circuit 64 instructions An address translation control unit 68 for performing an address translation process, and a segment descriptor holding register 69 for holding the segment descriptor referred to in the translation process during the address translation process when the match flag 67 is lit. ing.

Next, the operation of the present example thus constructed will be described with reference to FIG. 4 which shows the general concept of the address conversion processing.

When the logical address of the first request is set in the logical address register 51, the TLB 54 is indexed at the next timing, and when the TLB hit search circuit 57 results in a TLB mishit, the TLB mishit flag means 58 of the TLB mishit flag means 58. When the flag is turned on, the logical address of the first request is set in the logical address slip buffer 52, and the logical address of the second request is set in the logical address register 51. At the next timing, the activation flag 62 of the address translation control memory circuit is turned on, and the control of the address translation process is entrusted to the address translation control memory circuit 64, so that the address translation control unit 68.
It is performed in.

Whether or not the second request hits the TLB 54 is indexed during the address conversion process of the first request. Here, it is assumed that the logical address of the second request has a TLB mishit, is in the same segment as the logical address of the first request, and is in a different page.

That is, the TLB hit search circuit 57 searches for a TLB mishit at the logical address of the second request, and the segment number indicates that it is the same segment as the logical address for the first request. The coincidence detection circuit 66 searches and the logical address comparison circuit 5 indicates that the pages are not on the same page.
Search by 6. Next request T at the next timing
The LB miss hit flag means 59 is turned on, and the coincidence flag 67 indicating the coincidence of the segment numbers is turned on.

As shown in FIG. 4, the address conversion processing is performed in the segment table 43 by the segment table start address 42 and the segment number in the logical address 41 which are set when the process is rolled into the processor (CPU). The corresponding segment descriptor is read, the corresponding page descriptor in the desired page table 44 is read by this segment descriptor and the page number in the logical address 41, and the corresponding page descriptor in the read page descriptor is read. Out-of-page physical address field and logical address 4
The physical address 45 is generated from the offset value within 1.

Since the match flag 67 is lit during the address translation process, the fetched segment descriptor is set in the segment descriptor holding register in the translation process. Further, the index address of the address conversion control storage circuit 64 in the next step from which the segment descriptor is fetched is set in the startup address holding register 61 as the activation address of the address conversion control storage circuit by the second request.

When the address conversion process for the first request is completed, the flag of the next request TLB mishit flag means 59 is turned on, so the in-operation flag 62 of the address conversion control storage circuit is not cleared and the second request TLB is not cleared. The address conversion processing for the request is started by the address conversion control storage circuit 64. At this time, since the match flag 67 is turned on, the value of the start address holding register 61 is set in the address register 63 holding the start address of the address translation control storage circuit 64.

Therefore, the second address translation is performed by fetching the page descriptor using the segment descriptor held in the segment descriptor holding register 69.

[0011]

In the conventional address translation control circuit described above, subsequent requests are issued only when the logical addresses of two consecutive requests are TLB misses and access is made to different pages in the same segment. The address conversion process of can be performed by page descriptor fetch, and cannot be performed by page descriptor fetch in other cases. That is, the conventional address conversion control circuit can hold only the logical addresses of two consecutive requests, and performs the matching comparison of the segment numbers in the two logical addresses and the matching comparison of the out-of-page logical addresses. , Can hold only one segment descriptor.

An object of the present invention is, when a TLB is indexed by a logical address of a request, it is a TLB miss, but the segment number in the logical address registered in the TLB and the segment number in the logical address of the request. If and are matched, the address translation control circuit for accelerating the address translation process is provided by enabling the address translation process of this request to be performed by the page descriptor fetch.

[0013]

According to the address translation control circuit of the present invention, when a TLB is indexed by a logical address of a request, it is a TLB mishit but a segment number in the logical address registered in the TLB. And the segment number in the logical address of the request match, the address conversion processing of this request is performed by page descriptor fetch.

That is, the address translation control circuit of the present invention is an address translation control circuit of an address translation mechanism which has an associative address translation buffer and translates a logical address into a physical address. If the segment number in the logical address registered in the address translation buffer and the segment number in the arbitrary logical address match when the index is a miss hit, the page description corresponding to the segment number It is configured to fetch a child and perform an address conversion process on the arbitrary logical address.

Further, in the address translation control circuit of the present invention, the address translation buffer includes a directory section for storing a plurality of out-of-page logical addresses including a segment number and a page number in the logical address, each of which has an entry therein. , The out-of-page logical address in an arbitrary request and the out-of-page logical address registered in the directory section are compared and transmitted, and the TLB entry address is transmitted, and the segment number in the arbitrary request and the directory section are registered. A match detection circuit for performing a match comparison with the corresponding segment number and sending a segment comparison signal, and the segment detection circuit according to the TLB hit signal and the segment hit signal generated from the TLB entry address and the segment comparison signal, respectively. Segment entry address or TLB and the other bits one arbitrary bit as "1" to "0" when the plurality of bits of bets comparison signal is "1"
A selection circuit for selecting one of the entry addresses and sending it as a data read entry address, and data for storing the out-of-page physical address and segment descriptor information referred to in the address conversion process for each entry and reading it according to the data read entry address And a part.

The address translation control circuit of the present invention is
A directory part for storing a plurality of out-of-page logical addresses including a segment number and a page number in the logical address by providing an entry for each, an out-of-page logical address in an arbitrary request and an out-of-page registered in the directory part And a coincidence detection circuit for transmitting a TLB entry address by comparing and comparing with a logical address and transmitting a segment comparison signal by comparing and comparing the segment number in the arbitrary request with the segment number registered in the directory section. A selection circuit for selecting either a TLB entry address or a segment entry address according to a selection signal and transmitting it as a data read entry address; An address conversion buffer having a data section for storing child information and reading it according to the data read entry address, and a TLB hit signal with reference to the TLB entry address and a segment hit signal with reference to the segment comparison signal. An entry for generating a hit signal generating circuit and a segment entry address that refers to the segment comparison signal and sets one bit to "1" and the other bits to "0" when a plurality of bits are "1" An address editing circuit, a selection signal generation circuit which inputs the TLB hit signal and the segment hit signal and sends a selection signal to the selection circuit, and controls the segment descriptor information by controlling the TLB hit signal and the segment hit signal. Address conversion that performs address conversion processing by referencing Configured to have a mechanism.

According to the address translation control circuit of the present invention,
The match detection circuit compares, for each entry, the segment number in the out-of-page logical address of a request and the segment number in the out-of-page logical address registered in each entry of the TLB, and the out-of-page logic of a certain request. The address and the out-of-page logical address registered in each entry of the TLB are matched and compared for each entry, and the address translation mechanism uses the result of the above two matching comparisons to determine which of the two address translation processing start points is to be used. Either is selected and address conversion processing is performed. Also, the segment descriptor information referenced in the address conversion process is registered in the data section for each entry of the TLB.

Therefore, when the TLB is indexed by the logical address of a request, it is a TLB mishit, but if the segment number in the logical address registered in the TLB and the segment number in the request logical address match. For example, the address conversion process of this request can be performed by the page descriptor fetch, and the address conversion process can be speeded up.

[0019]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings.

1 and 2 are block diagrams showing an embodiment of the present invention. In the figure, the logical address register 1 holds the logical address 101 generated by the logical address generation circuit, and stores the segment number and page number in the logical address outside the page logical address 1
02, and the offset value in the logical address is output as the in-page logical address 103.

The directory section 2 is one of the constituent elements of the TLB 19 and comprises a plurality of entries, and stores the out-of-page logical address 102 which is the output of the logical address register 1. Further, the data stored in each entry is output as the directory output data 104. In this embodiment, the number of TLB entries is n.

The coincidence detection circuit 3 is one of the components of the TLB 19, and receives the out-of-page logical address 102 output from the logical address register 1 and the directory output data 104 output from each entry of the directory section 2. Then, all the fields of the out-of-page logical address are compared and compared, and the result is output as the TLB entry address 105. Further, the segment numbers in the out-of-page logical address are compared and compared, and the result is output as the segment comparison signal 107. TLB entry address 10
5 and the segment comparison signal 107 are both n bits.

Details of the directory unit 2 and the match detection circuit 3 are shown in FIG. In the figure, the match detection circuit 3 inputs the segment number 102a and the page number 102b from the logical address register 1 and performs a match comparison for each entry of the directory section 2. Then, the segment comparison signal 107
(0) to 107 (n-1) are transmitted. Further, the page number coincidence comparison and the segment number coincidence comparison are ANDed, and the result is transmitted as TLB entry addresses 105 (0) to 105 (n-1).

The first selection circuit 4, which is one of the components of the TLB 19, inputs the TLB entry address 105 which is the output of the match detection circuit 3 and the segment entry address 114 which is the output of the entry address register 12, The selection signal 113 output from the selection signal generation circuit 14
Is selected and output as the data section read entry address 106. The data section read entry address 106 has n bits, and its data format is all bits “0” value, or only 1 bit is “1” value and the remaining (n−1) bits are “0” value.

The data A section 5 is one of the constituent elements of the TLB 19 and is composed of a plurality of entries, and stores the out-of-page physical address whose address is translated by the address translation mechanism 17. The physical address outside the page is included in the data part registration data 123 and output by the address translation mechanism 17.
Further, the data in the entry designated by the data section read entry address 106 which is the output of the first selection circuit 4 is output as the out-of-page physical address 115.

The data B section 6 is one of the constituent elements of the TLB 19 and comprises a plurality of entries, and stores the access key contained in the segment descriptor referred to in the address translation process by the address translation mechanism 17. The access key is
The address conversion mechanism 17 outputs the data included in the data registration data 123. Further, the data in the entry designated by the data section read entry address 106 which is the output of the first selection circuit 4 is set as the segment descriptor information 11
Output as 6.

The data C section 7 is one of the components of the TLB 19 and is composed of a plurality of entries, and stores fields other than the access key included in the segment descriptor referred to in the address conversion process by the address conversion mechanism 17. To do.
The fields other than the access key include the page table start address, the page table maximum size, and the like.
It is included in 3 and output. Also, the data in the entry designated by the data section read entry address 106 which is the output of the first selection circuit 4 is output as the segment descriptor information 117.

The hit signal generation circuit 8 is a match detection circuit 3
All bits of the TLB entry address 105, which is the output of the above, are ORed, and the result is output as the TLB hit signal 108. Further, all bits of the segment comparison signal 107 output from the coincidence detection circuit 3 are ORed, and the result is output as a segment hit signal 109.

The entry address editing circuit 9 inputs the segment comparison signal 107 which is the output of the match detection circuit 3. The segment comparison signal 107 has n bits, and its data format is all bits “0” value, one certain bit is “1” value, and the remaining (n−1) bits are “0” value, multiple bits “1”. There are three possible values. In this circuit, this data is invalid when all bits are "0" values, so an arbitrary value is output as the segment entry address 110. When only one bit has a value of "1" and the remaining (n-1) bits have a value of "0", this data is directly output as the segment entry address 110. In the case of a plurality of bits “1”, only one of the bits is edited as a “1” value and the remaining (n−1) bits are edited as a “0” value, and the segment entry address 110 is output.

The TLB hit register 10 sets the TLB hit signal 108 which is the output of the hit signal generation circuit 8 and outputs it as the TLB hit signal 111.

The segment hit register 11 outputs the segment hit signal 10 output from the hit signal generation circuit 8.
9 is set and it is output as the segment hit signal 112.

The entry address register 12 sets the segment entry address 110, which is the output of the entry address editing circuit, and outputs it as the segment entry address 114.

The physical address register 13 has the out-of-page physical address 115 read from the data A section 5 and the offset value 103 output from the logical address register 1.
And the physical address 118 is output.

The selection signal generation circuit 14 inputs the TLB hit signal 111 which is the output of the TLB hit register 10 and the segment hit signal 112 which is the output of the segment hit register 11, and (TLB hit signal: segment hit signal) = When (0: 1), the value “1” is output as the selection signal 113.

The pipe control circuit 15 inputs the TLB hit signal 108 which is the output of the hit signal generation circuit 8, and when this signal has a value of "0", puts the pipe above the address conversion control circuit into a hold state. .

The segment descriptor register 16 outputs the segment descriptor information 116 output from the data B section 6 and the output from the data C section 7 when the selection signal 113 output from the selection signal generation circuit 14 has a value of "1". And the segment descriptor information 117
19 is output.

The address translation mechanism 17 executes the address translation process shown in FIG. At that time, when the TLB hit signal 108 and the segment hit signal 109 which are the outputs of the hit signal generation circuit 8 are input and (TLB hit signal: segment hit signal) = (0: 0), it is the first address conversion processing. This is performed by referring to the segment table in FIG. When (TLB hit signal: segment hit signal) = (0: 1), the address conversion process is performed by referring to the page table in FIG. In the address translation process, the segment table and the page table are referenced, but since each table exists in the main memory, the address translation table index address 122 is output when each table is referenced. In addition, the address-converted out-of-page physical address and the segment descriptor information referenced in the address conversion process are stored in the data section registration data 12
Output as 3.

The second selection circuit 18 receives the TLB hit signal 111 output from the TLB hit register 10 and outputs the physical address 11 output from the physical address register 13.
8 or the address translation table index address 122 output from the address translation mechanism 17, and sends the result as a memory access physical address 124 to the main storage device or a cache holding a copy of the main storage. To do.

Next, the operation of the above address translation control device will be described.

First, at the 1T, the logical address 101 for the first request generated by the logical address generation circuit is held in the logical address register 1.

At the 2T, logical address register 1
TL at out-of-page logical address 102 held in
Index B19. Here, the out-of-page logical address 10
Assume 2 is a TLB miss and a segment miss.

In the match detection circuit 3, the out-of-page logical address 102 for the first request and the directory output data 1 which is the output of each entry of the directory section 2 are output.
04 is input, all fields of the out-of-page logical address are compared and compared, and the result is output to the TLB entry address 105. Further, the segment numbers in the out-of-page logical address are compared and compared, and the result is output to the segment comparison signal 107.

Here, based on the above assumption, the result of matching comparison of the out-of-page logical address with respect to the first request is TL.
It is the all-bit “0” value of the B entry address 105 and all-bit “0” value of the segment comparison signal 107.

In the hit signal generation circuit 8, all bits of the TLB entry address 105 which is the output of the match detection circuit 3 are ORed, and the result "0" value (indicating TLB mishit) is given to the TLB hit signal 108. Output to.
Also, all bits of the segment comparison signal 107 output from the coincidence detection circuit 3 are ORed, and the result is “0”.
The value (indicating a segment mishit) is output to the segment hit signal 109.

In the pipe control circuit 15, the TLB hit signal 108 which is the output of the hit signal generation circuit 8 is input,
Since this signal has a value of "0", the pipe above the address conversion control circuit is placed in the hold state. As a result, the logical address for the first request remains held in the logical address register 1.

In the address conversion mechanism 17, the TLB hit signal 108 and the segment hit signal 109, which are the outputs of the hit signal generation circuit 8, are input and (TLB hit signal:
Since the segment hit signal) = (0: 0), the address conversion process is started so as to execute the address conversion from the segment table reference in FIG.

In the TLB hit register 10, the value "0" of the TLB hit signal 108 output from the hit signal generation circuit 8 is set.

In the segment hit register 11, the segment hit signal 1 output from the hit signal generation circuit 8 is output.
A "0" value of 09 is set.

At the 3T, the selection signal generation circuit 14
Inputs the TLB hit signal 111, which is the output of the TLB hit register 10, and the segment hit signal 112, which is the output of the segment hit register 11, and outputs (TLB
Since the hit signal: segment hit signal) = (0: 0), the value “0” is output to the selection signal 113.

Further, the address translation mechanism 17 starts the address translation process. The operation of this address conversion processing will be described with reference to FIG. First, when the process is rolled into the processor (CPU), the segment table start address 42 set in the address translation mechanism and the segment number in the logical address 41 held in the logical address register 1 The corresponding segment descriptor in 43 is read. The segment descriptor includes information such as the page table start address, page table maximum size, and access key. The corresponding page descriptor in the desired page table 44 is read by the page table start address in the segment descriptor and the page number in the logical address 41. The page descriptor includes information such as an out-of-page physical address, and a physical address 45 is generated from this out-of-page physical address and an offset value in the logical address 41.

Thereafter, the generated out-of-page physical address and the segment descriptor information referred to in the address conversion process are output as the data part registration data 123.

At the xTth time, in the directory section 2,
The out-of-page logical address 102 is registered in the entry designated by the replace circuit of the TLB, the out-of-page physical address in the data part registration data 123 is registered in the same entry in the data A section 5, and the in-data B section 6 An access key, which is a part of the segment descriptor information in the data section registration data 123, is registered in the same entry, and the data section registration data 123 is registered in the same entry in the data C section 7.
Information (page table top address, page table maximum size, etc.) other than the access key, which is a part of the segment descriptor information in the above, is registered, and the address conversion process ends.

At the (x + 1) Tth time, the TLB is indexed again by the out-of-page logical address 102 for the first request held in the logical address register 1.

In the match detection circuit 3, the out-of-page logical address 102 for the first request and the directory output data 1 which is the output of each entry of the directory section 2 are output.
Enter 04 and compare and compare all fields of the out-of-page logical address. As a result, the value "1" indicating a match for only one entry and the value "0" indicating a mismatch for the other entries are TLB entry addresses. Output to 105.
Further, the segment numbers in the out-of-page logical address are compared and compared, and as a result, a "1" value indicating a match for only one entry and a "0" value indicating a mismatch for the other entries are output to the segment comparison signal 107. To do.

In the hit signal generation circuit 8, all bits of the TLB entry address 105 output from the match detection circuit 3 are ORed, and the result "1" value (indicating TLB hit) is used as the TLB hit signal 108. Output. In addition, the segment comparison signal 1 output from the coincidence detection circuit 3
All bits of 07 are ORed, and the resulting "1" value (indicating segment hit) is set as the segment hit signal 1
09 is output.

In the first selection circuit 4, the selection signal generation circuit 1
4 is the output of the selection signal 113, the TLB entry address 105 output from the match detection circuit 3 is "0".
Is selected and output as the data section read entry address 106.

The data A section 5 outputs the data in the entry designated by the data section read entry address 106 to the out-of-page physical address 115 and the physical address register 13 together with the offset value 103 output from the logical address register 1. Hold on.

The data B section 6 outputs the data in the entry designated by the data section read entry address 106 to the segment descriptor information 116. This information is an access key and is sent to the access right check circuit.

In the pipe control circuit 15, the TLB hit signal 108 which is the output of the hit signal generation circuit 8 is input,
Since this signal has a value of "1", the hold state of the pipe above the address translation control circuit is released. As a result, the logical address for the next request generated by the logical address generation circuit is held in the logical address register 1.

In the TLB hit register 10, the "1" value of the TLB hit signal 108 output from the hit signal generation circuit 8 is set.

In the segment hit register 11, the segment hit signal 1 output from the hit signal generation circuit 8 is output.
A "1" value of 09 is set.

At the (x + 2) T th, the selection signal generation circuit 14 outputs the TL which is the output of the TLB hit register 10.
Input the B hit signal 111 and the segment hit signal 112 which is the output of the segment hit register 11,
(TLB hit signal: segment hit signal) = (1:
Therefore, the value "0" is output as the selection signal 113.

Since the TLB hit signal 111, which is the output of the TLB hit register 10, has the value "1", the second selection circuit 18 selects the physical address 118, which is the output of the physical address register 13, and the memory access physical address 1
As 24, it is sent to the main storage device 3 or a cache holding a copy of the main storage.

The TLB is indexed at the out-of-page logical address 102 for the next request held in the logical address register 1.

Here, the out-of-page logical address 102 is
Assume TLB miss and segment hit. That is, the logical address for the next request is the same segment as the logical address for the first request and is a different page reference.

In the match detection circuit 3, the out-of-page logical address 102 for the next request and the directory output data 104 which is the output of each entry of the directory section 2 are output.
Is input, all fields of the logical address outside the page are compared and compared, and the result is TLB entry address 10
5 is output. Further, the segment numbers in the out-of-page logical address are compared and compared, and the result is output to the segment comparison signal 107.

Based on the above assumption, the TLB entry address 105 is a value "0" for all bits, and the segment comparison signal 107 indicates the out-of-page logical address of the first request in the match comparison result of the out-of-page logical address for the next request. Only the bit corresponding to the entry in which is registered has a value of "1", and the other bits have a value of "0".

In the hit signal generation circuit 8, all bits of the TLB entry address 105 output from the match detection circuit 3 are ORed, and the result "0" value (indicating a TLB mishit) is output to the TLB hit signal 108. Output to.
Further, all bits of the segment comparison signal 107 output from the coincidence detection circuit 3 are ORed, and the result is “1”.
The value (indicating a segment hit) is output to the segment hit signal 109.

In the entry address editing circuit 9, the segment comparison signal 107 which is the output of the match detection circuit 3 is input. Since this data has a value of "1" for only one bit and the value of "0" for the remaining (n-1) bits, it is output as it is as the segment entry address 110.

In the pipe control circuit 15, the TLB hit signal 108 which is the output of the hit signal generation circuit 8 is input,
Since this signal has a value of "0", the pipe above the address conversion control circuit is placed in the hold state. As a result, the logical address for the next request remains held in the logical address register 1.

In the address conversion mechanism 17, the TLB hit signal 108 and the segment hit signal 109 which are the outputs of the hit signal generation circuit 8 are input, and (TLB hit signal:
Since the segment hit signal) = (0: 1), it is activated to execute the address conversion by referring to the page table in FIG. 4 during the address conversion process.

In the TLB hit register 10, the value "0" of the TLB hit signal 108 output from the hit signal generation circuit 8 is set.

In the segment hit register 11, the segment hit signal 1 output from the hit signal generation circuit 8 is output.
A "1" value of 09 is set.

At the (x + 3) th T, the selection signal generation circuit 14 outputs the TL which is the output of the TLB hit register 10.
Input the B hit signal 111 and the segment hit signal 112 which is the output of the segment hit register 11,
(TLB hit signal: segment hit signal) = (0:
Therefore, the value “1” is output as the selection signal 113.

In the first selection circuit 4, the selection signal generation circuit 1
Since the selection signal 113 which is the output of No. 4 has the value "1", the segment entry address 114 which is the output of the entry address register 12 is selected and output as the data section read entry address 106.

The data B section 6 outputs the data in the entry designated by the data section read entry address 106 to the segment descriptor information 116.

The data C section 7 outputs the data in the entry designated by the data section read entry address 106 to the segment descriptor information 117. The segment descriptor information 116 and the segment descriptor information 117 are the segment descriptor information referred to in the address conversion process using the logical address for the first request.

In the segment descriptor register 16, the selection signal 113 output from the selection signal generation circuit 14 is "1".
Because of the value, the segment descriptor information 116 output from the data B unit 6 and the segment descriptor information 117 output from the data unit 7 are held.

The address translation mechanism 17 starts the address translation process. The operation of this address conversion processing will be described with reference to FIG. The segment descriptor 119 is read from the segment descriptor register 16. The segment descriptor includes information such as the page table start address, page table maximum size, and access key. The corresponding page descriptor in the desired page table 44 is read by the page table start address in the segment descriptor and the page number in the logical address 41. The page descriptor includes information such as an out-of-page physical address and the like, and a physical address is generated from the out-of-page physical address and the offset value in the logical address 41.

The subsequent operation is the same as the operation for the first request.

[0081]

According to the address translation control circuit of the present invention, when the TLB is indexed by the logical address of a request,
Although it is a TLB miss, if the segment number in the logical address registered in the TLB and the segment number in the logical address of the request match, the address translation process of this request is performed by page descriptor fetch. Is. This can speed up the address conversion process.

That is, the comparison between the segment number in the out-of-page logical address of a request and the segment number in the out-of-page logical address registered in each entry of the TLB for each entry, and the out-of-page logical address of a certain request And an out-of-page logical address recorded in each entry of the TLB are compared for each entry, and either one of the two address conversion processing start points is selected according to the result of the above two comparisons. Address conversion processing. Further, the segment descriptor information referred to in the address conversion process is registered for each entry of the TLB. Therefore, the address conversion process can be executed at high speed.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention (continued).

FIG. 3 is an explanatory diagram showing details of a match detection circuit.

FIG. 4 is an explanatory diagram showing an example of address conversion processing.

FIG. 5 is a block diagram showing a conventional address translation control circuit.

[Explanation of symbols]

1 Logical Address Register 2 Directory Section 3 Match Detection Circuit 4 First Selection Circuit 5 Data A Section 6 Data B Section 7 Data C Section 8 Hit Signal Generation Circuit 9 Entry Address Editing Circuit 10 TLB Hit Register 11 Segment Hit Register 12 Entry Address Register 13 physical address register 14 selection signal generation circuit 15 pipe control circuit 16 segment descriptor register 17 address conversion mechanism 18 second selection circuit 19 TLB 43 segment table 44 page table 101 logical address 102 out-of-page logical address 103 in-page logical address 104 directory Output data 105 TLB entry address 106 Data section read entry address 107 Segment comparison signal 108, 111 TLB hit signal 109, 112 segment hit signal 110, 114 segment entry address 113 selection signal 115 out-of-page physical address 116 segment descriptor information (access key) 117 segment descriptor information (information other than access key) 118 physical address 119 segment descriptor information 122 address conversion Table index address 123 Data registration data 124 Memory access physical address

Claims (3)

[Claims] 1. An address translation control circuit having an associative address translation buffer for translating a logical address into a physical address, wherein the address translation buffer is indexed by an arbitrary logical address, resulting in a mishit. When the segment number in the logical address registered in the address translation buffer and the segment number in the arbitrary logical address match, the page descriptor corresponding to the segment number is fetched and the arbitrary logical address is fetched. Address conversion control circuit characterized by performing address conversion processing on. 2. The address translation control circuit according to claim 1, wherein the address translation buffer stores a plurality of out-of-page logical addresses including a segment number and a page number in the logical address by providing an entry for each of them. Section and the out-of-page logical address in the arbitrary request and the out-of-page logical address registered in the directory section are compared and transmitted, and the TLB entry address is transmitted, and the segment number in the arbitrary request and the directory section A match detection circuit that compares and compares the registered segment number and sends a segment comparison signal, and the segment segment according to the TLB hit signal and the segment hit signal generated from the TLB entry address and the segment comparison signal, respectively. Segment entry address or TLB in which any one bit is set to "1" and other bits are set to "0" when a plurality of bits of the comparison signal are "1"
A selection circuit for selecting one of the entry addresses and sending it as a data read entry address, and data for storing the out-of-page physical address and segment descriptor information referred to in the address conversion process for each entry and reading it according to the data read entry address And an address translation control circuit. 3. A directory section for storing a plurality of out-of-page logical addresses including a segment number and a page number in the logical address by providing an entry for each of them, and the out-of-page logical address in an arbitrary request and registered in the directory section. The TLB entry address is sent out by comparing and comparing the stored out-of-page logical address, and the segment number in the arbitrary request and the segment number registered in the directory part are compared and sent out and a segment comparison signal is sent out. A match detection circuit for selecting the TLB entry address or the segment entry address according to the selection signal and transmitting the selected data as a data read entry address; and an out-of-page physical address referred to in the address translation process for each entry. An address conversion buffer having a data section for storing segment descriptor information and reading it according to the data read entry address, and a TLB hit signal with reference to the TLB entry address and a segment hit with reference to the segment comparison signal. A hit signal generation circuit that generates a signal, and a segment entry address that refers to the segment comparison signal and sets any one bit to "1" and other bits to "0" when multiple bits are "1" An entry address editing circuit, a selection signal generation circuit for inputting the TLB hit signal and the segment hit signal and sending a selection signal to the selection circuit, and the segment descriptor controlled by the TLB hit signal and the segment hit signal Address conversion processing by referring to information An address translation control circuit having an address translation mechanism for performing the address translation.