JPH09219812A - Camera device and timing generation circuit for camera device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simplify and lighten circuit constitution capable of sharing a counter loading value even for the camera device of a different clock frequency by supplying preset values for equalizing the final output points of time of respective electronic shutter pulses to a shutter counter. SOLUTION: A step counter 46 outputs the several kinds of frequency division clocks Sfd whose generation intervals are varied stepwise in a vertical fly-back period as the electronic shutter pulses Ps based on the counting of a reference clock generation part 41. Also, in a preset value generation circuit 61, the preset values Dp1-4 for equalizing the final output points of time of the respective electronic shutter pulses Ps are generated for the reference clocks Pc1-4 of respectively different frequencies and supplied to the step counter 46. Thus, the counter loading value for deciding a shutter speed is shared for the camera devices of plural modes provided with the different clock frequencies and the circuit constitution is simplified and lightened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a camera device having an electronic shutter function suitable for use in, for example, a video camera, an electronic still camera or the like, and a timing generation circuit thereof.

[0002]

2. Description of the Related Art Recently, in a camera device such as a video camera or an electronic still camera in which a solid-state image pickup device using a CCD is incorporated in a signal charge transfer section, an electronic shutter speed is controlled for the purpose of controlling an exposure period. Means (hereinafter,
It is known simply as an electronic iris).

This electronic iris detects the level of an image pickup signal output from an image sensor, compares the detected voltage with a reference voltage, and when the detected voltage is higher than the reference voltage, the electronic shutter speed is high. In other words, when the detection voltage is lower than the reference voltage, the electronic shutter speed is controlled so that the time interval (exposure period) between the final output time of the electronic shutter pulse and the charge reading time is shortened. Control is performed so that the exposure period becomes longer, that is, the exposure period becomes longer.

An important point in the performance of the electronic iris is the smoothness of control. To realize this,
In the high shutter speed range, a finer shutter speed change than 1H increments synchronized with the horizontal synchronizing signal is required.

Normally, the timing of applying the electronic shutter pulse to the solid-state image pickup device is required not to affect the reproduced image. Therefore, in the case of 1H steps, it is limited to the horizontal blanking period and 1H or less. It is during the vertical blanking period.

In the step of 1H or less during the vertical blanking period, the reference clock output from the crystal unit is usually divided by the shutter step generation circuit of the timing generation circuit, and the divided clock is divided into electronic shutter pulses. I am trying to output as.

In particular, the frequency division ratio is designed to be changed in each shutter speed region so that the rate of change of the shutter speed becomes substantially equal during the vertical blanking period.

Specifically, a general shutter step in an electronic iris system will be described with reference to FIG.

In FIG. 5, the period indicated by A is the effective video period, and the period indicated by B is the vertical blanking period. Then, in each of the shutter steps (the time when the electronic shutter pulse is output), the period C from the final output time of the electronic shutter pulse selected by the electronic iris to the output time of the read pulse is the shutter speed (exposure period). Equivalent to.

In the effective video period A, the output timing of the shutter pulse applied to the solid-state image pickup device is limited to the horizontal blanking period, so the 1H cycle is the finest step, but during the vertical blanking period, reproduction is performed. Since it does not affect the image, it divides the reference clock to generate finer steps.

Further, the frequency division ratio of the reference clock is changed stepwise in order to keep the rate of change from the low speed shutter area to the high speed shutter area as constant as possible even during the vertical blanking period. The example of FIG. 5 shows an example in which the frequency is divided into 8 steps / 4 divisions / 2 divisions from the low speed shutter area toward the high speed shutter area.

In this electronic iris system, the number of output electronic shutter pulses is determined based on the difference between the detection voltage of the image pickup signal and the reference voltage, and the number of output electronic shutter pulses is counted. It is given as the load value of the counter.

Next, a conventional shutter step generation circuit will be described with reference to FIG. As shown in the figure, this shutter step generation circuit is configured to include a V counter 101, an H counter 102, a step counter 103, and a switching circuit 104.

The V counter 101 counts the input of the horizontal synchronizing signal HD based on the input of the vertical synchronizing signal VD, falls at the start of the vertical blanking period, and rises at the end of the vertical blanking period. It is a circuit that generates the line pulse signal Svb.

The H counter 102 counts the input of the reference clock Pc based on the input of the horizontal synchronizing signal HD, generates one pulse signal Sh which rises during the horizontal blanking period, and uses the pulse signal Sh as an electronic shutter. It is a circuit that outputs as a pulse Ps.

The step counter 103 counts the input of the reference clock Pc based on the trailing edge of the vertical retrace pulse signal Svb from the V counter 101, and stages several kinds of divided clocks Sfd based on the counted value. Circuit for generating the divided clock Sfd as an electronic shutter pulse Ps. Here, an example is shown in which the divided-by-8 clock is output in the low-speed shutter area, the divided-by-4 clock is output in the medium-speed shutter area, and the divided-by-2 clock is output in the high-speed shutter area.

The switching circuit 104, based on the output from the V counter 101, outputs a pulse signal Sh (electronic shutter pulse) from the H counter 102 and several kinds of divided clocks Sfd (electronic shutter pulse) from the step counter 103. Is a circuit for selectively switching between and output. Specifically, during a period during which the vertical retrace pulse signal Svb output from the V counter 101 is at a high level, a horizontal retrace period from the H counter 102 is performed. The output electronic shutter pulse Ps is selected, and the vertical retrace pulse signal Sv is selected.
While b is at a low level, several kinds of divided clocks S output during the vertical retrace period from the step counter 103 are output.
It is configured to select fd.

That is, the output terminal φout of the switching circuit 104 outputs the electronic shutter pulse Ps synchronized with the horizontal blanking period from the H counter 102 during the effective video period A, and the step during the vertical blanking period. Several kinds of frequency-divided clocks Sfd from the counter 103 are output as the electronic shutter pulse Ps.

[0019]

By the way, in recent video cameras, at the time of designing, an image sensor having a different number of pixels is attached to the set side in accordance with the usage pattern (usage environment) of the camera.

Normally, when the number of pixels of the image sensor is different, the frequency of the reference clock which is the reference for signal processing also changes. For example, the reference clock frequency of the 250,000 pixel CCD image sensor is 9.5 MHz, and the reference clock frequency of the 380,000 pixel CCD image sensor is 14.
0 MHz.

In this case, in order to reduce the size and weight,
In terms of signal processing, it is necessary to share the common parts as much as possible to configure the circuit. Therefore, in the above-described camera device, a reference clock generator that generates a reference clock is installed only in the type of frequency corresponding to the number of pixels of the image sensor to which the reference clock generator is attached. The circuit corresponding to the type is selectively switched and used, and almost the same circuit of the signal processing system is used.

However, when the shutter step circuit for generating the electronic shutter pulse Ps is the same circuit for a plurality of reference clocks having different clock frequencies, the same load of the counter for counting the output number of the electronic shutter pulse Ps is used. There is a problem that the shutter speed corresponding to the value is different.

That is, when the load value of the counter is constant, the shutter speed becomes slower at a certain reference clock and becomes faster at another reference clock, and the same object is taken every time the image sensor is replaced. There is a problem in that the image pickup characteristics for the are different.

Specifically, referring to FIG. 7,
For example, in the 250,000-pixel image sensor, when the fastest shutter speed is selected, the final output time of the electronic shutter pulse Ps is ta time as shown in FIG.
Next, for example, when a 380,000-pixel image sensor is mounted and the same highest shutter speed is selected, the reference clock used has a clock frequency of 14 MHz, and the reference used by the 250,000-pixel image sensor is The clock frequency is higher than the clock frequency of 9.5 MHz.

From this, the generation interval of the electronic shutter pulse Ps in the 380,000 pixel image sensor becomes shorter than that in the case of the 250,000 pixel image sensor, and when the electronic shutter pulse Ps is generated with the same load value, FIG. As shown in the figure, the final output time of the electronic shutter pulse Ps in the 380,000-pixel image sensor arrives at the time tb, which is earlier than in the case of the 250,000-pixel image sensor, instead of the above-mentioned ta. There arises a problem that the shutter speed (for example, 1/100000) cannot be obtained.

This problem is negligible in the low shutter speed range, but it becomes more noticeable especially at higher shutter speeds, and there is a non-negligible difference in terms of the shutter speed ratio for each reference clock. It will be.

Therefore, in order to obtain the same shutter speed for the same subject with a plurality of reference clocks, it is necessary to make the load values uniform for each of the plurality of reference clocks. Specifically, the load value is calculated for each of multiple reference clocks based on the difference between the detection voltage of the image pickup signal output from the image sensor and the reference voltage, and the load value is calculated for each reference clock in the newly installed memory. The process of storing the value is required. In this case, the load value corresponding to the reference clock to be used is read to generate the electronic shutter pulse.

In the case of the above method, a process of calculating a load value for each of a plurality of reference clocks in real time from the difference between the detected voltage and the reference voltage based on, for example, a conversion parameter stored in a conversion table, and each of the calculated values. Since the process of writing the load value to the memory and the process of reading the load value corresponding to the reference clock used from the memory must be performed, and further, the series of these processes must be performed at high speed, the electronic iris There is a concern that the system algorithm will become complicated and the circuit configuration will inevitably increase in size.

As another method, the same load value may be used, and instead, a plurality of shutter step circuits may be arranged in accordance with a plurality of reference clocks.
This is contrary to the proposition of commonality of circuits, and there is a problem that the circuit configuration and structure become large.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a camera device in which a plurality of modes having different clock frequencies are mixed.
Provided is a camera device in which a circuit system for generating an electronic shutter pulse and a counter load value for determining a shutter speed can be shared by one type each, which can promote simplification of a circuit configuration and reduction in size and weight of the device itself. To do.

Another object of the present invention is to allow a camera device in which a plurality of modes having different clock frequencies coexist to share one counter load value for determining the shutter speed. It is an object of the present invention to provide a timing generation circuit for a camera device, which can realize simplification of the algorithm of the iris system and simplification of the circuit configuration.

[0032]

A camera device according to the present invention converts a signal charge of an amount corresponding to the amount of light incident from a subject during an exposure period, outputs the signal charge as an image pickup signal, and outputs the signal from the outside. A solid-state image sensor having an electronic shutter function for sweeping away accumulated charges based on the supply of an electronic shutter pulse, and an electronic shutter pulse that is the start point of the exposure period according to the level of an image signal output from the solid-state image sensor And a timing generation circuit for timing-controlling the final output time of the electronic shutter, in which the generation interval is changed stepwise in the vertical blanking period based on the count of the reference clock. The electronic shutter pulse generation circuit that outputs a pulse and the final output time of the electronic shutter pulse are set to a plurality of reference clocks with different frequencies. For each generates a preset value which is equal, constitutes provided the preset value generating circuit for supplying to the electronic shutter pulse generating circuit as a preset count.

As a result, first, the solid-state image pickup device converts the light incident from the subject during the exposure period into a signal charge of an amount corresponding to the amount of light and outputs it as an image pickup signal. In the periods other than the exposure period, the accumulated charges are swept away based on the supply of the electronic shutter pulse from the outside.

The exposure period is controlled by the timing generation circuit. Specifically, in the timing generation circuit, the exposure is performed according to the level of the image pickup signal output from the solid-state image pickup device. The exposure period is determined by timing-controlling the final output time of the electronic shutter pulse, which is the start time of the period.

The electronic shutter pulse is generated by the electronic shutter pulse generating circuit in the timing generating circuit.
It is created and output based on the count of the reference clock.
In particular, in the vertical blanking period, since there is no restriction that the output must be performed during the horizontal blanking period, the electronic shutter pulse generation circuit generates an electronic shutter pulse whose generation interval is variable stepwise. And output.

Since the final output time of the electronic shutter pulse depends on the clock frequency of the reference clock, when a plurality of reference clocks having different clock frequencies are selectively used, the electronic shutter is output for each reference clock. The final output time of the pulse is different.

However, in the present invention, the preset value generating circuit generates the preset value such that the final output time of the electronic shutter pulse is the same for a plurality of reference clocks having different frequencies, and the electronic shutter pulse generating circuit generates the preset value. It is supplied as a preset count value.

Therefore, the electronic shutter pulse generation circuit starts counting from the preset count value supplied from the preset value generation circuit in the vertical blanking period, and counts the sequentially input reference clocks. As a result, in the electronic shutter pulse generation circuit, for example, when the divided clock is output when the count value is “1”, when the preset count value is not set, the first electronic shutter pulse is generated at the start of the vertical blanking period. When the preset count value is supplied, the preset count value is j and the frequency division ratio is n.
The first electronic shutter pulse is output when j + 1 is counted.

That is, the timing at which the first electronic shutter pulse is output after the vertical blanking period is started can be arbitrarily shifted, and the final output time of the electronic shutter pulse can be arbitrarily shifted. Therefore,
By generating a plurality of preset values corresponding to a plurality of reference clocks and supplying a preset value according to the reference clock to be used as a preset count value to the electronic shutter pulse generation circuit, It is possible to make the final output times the same.

As described above, in the camera device according to the present invention, even for a camera device in which a plurality of modes having different clock frequencies are mixed, a circuit system for generating an electronic shutter pulse and a counter load for determining a shutter speed are provided. The values can be shared by one type, and the simplification of the circuit configuration and the reduction in size and weight of the device itself can be promoted.

Next, the timing generating circuit for a camera device according to the present invention converts into a signal charge of an amount corresponding to the amount of light incident from the subject during the exposure period and outputs it as an image pickup signal, and from the outside. The final output time of the electronic shutter pulse, which is the start time of the exposure period according to the level of the image pickup signal output from the solid-state image pickup device having the electronic shutter function for sweeping away the accumulated charge based on the supply of the electronic shutter pulse In a timing generation circuit for a camera device for timing control of an electronic shutter pulse generation circuit that outputs an electronic shutter pulse whose generation interval is stepwise changed in a vertical blanking period based on the count of a reference clock, and the electronic shutter pulse generation circuit. Set the preset values so that the final output time of the shutter pulse is the same for multiple reference clocks with different frequencies. Form, is constructed by providing the preset value generating circuit for supplying to the electronic shutter pulse generating circuit as a preset count.

Thus, first, the electronic shutter pulse generation circuit generates and outputs an electronic shutter pulse whose generation interval is variable stepwise based on the count of the reference clock in the vertical blanking period. In this case, since the final output time of the electronic shutter pulse depends on the clock frequency of the reference clock, when selectively using a plurality of reference clocks having different clock frequencies, the final output of the electronic shutter pulse is performed for each reference clock. The output time will be different.

However, according to the present invention, the preset value generating circuit generates the preset value such that the final output time of the electronic shutter pulse is the same for the plurality of reference clocks having different frequencies, and the electronic shutter pulse generating circuit generates the preset value. It is supplied as a preset count value.

Therefore, the electronic shutter pulse generation circuit starts counting from the preset count value supplied from the preset value generation circuit in the vertical blanking period, and counts the sequentially input reference clock. As a result, in the electronic shutter pulse generation circuit, for example, when the divided clock is output when the count value is “1”, when the preset count value is not set, the first electronic shutter pulse is generated at the start of the vertical blanking period. When the preset count value is supplied, the preset count value is j and the frequency division ratio is n.
The first electronic shutter pulse is output when j + 1 is counted.

That is, the timing at which the first electronic shutter pulse is output after the vertical blanking period is started can be arbitrarily shifted, and the final output time of the electronic shutter pulse can be arbitrarily shifted. Therefore,
By generating a plurality of preset values corresponding to a plurality of reference clocks and supplying a preset value according to the reference clock to be used as a preset count value to the electronic shutter pulse generation circuit, It is possible to make the final output times the same.

As described above, in the camera device timing generation circuit according to the present invention, even for a camera device in which a plurality of modes having different clock frequencies are mixed, only one type of counter load value for determining the shutter speed is used. It can be shared, and simplification of the algorithm of the electronic iris system and simplification of the circuit configuration can be realized.

[0047]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment example in which the camera device according to the present invention is applied to a compatible video camera capable of selectively mounting image sensors having different numbers of pixels (hereinafter, simply referred to as an embodiment Will be described with reference to FIGS. 1 to 4.

The camera device according to this embodiment is shown in FIG.
As shown in FIG. 2, a lens unit 1 and an optical filter 2 for suppressing false signals having a frequency component corresponding to the spatial frequency of a color filter array formed in an image sensor,
An image sensor 3 having an electronic shutter function, which converts light from a subject incident through the lens unit 1 and the optical filter 2 into a signal charge of an amount corresponding to the light amount and outputs the signal charge as an image pickup signal, and the image sensor. A broadband luminance signal is created from the image pickup signal S output from the device 3, the multiplexed color signals are separated, and the luminance signal and the color signal are passed through a color encoder to be combined into a standard NTSC color signal Sv, for example. A video signal processing circuit 4 for outputting the same, an electronic iris circuit 5 for controlling an electronic shutter speed for the purpose of controlling the exposure period, and an identification detecting section 6 for detecting the type of the image sensor 3 attached to the camera body.
And a system controller 7 for controlling various circuits.

The identification detection unit 6 has, for example, two identification terminals (not shown) for identifying the type of the image sensor attached to the set side, and these terminals are attached to the image sensor attached to the set side at the time of designing. It is designed to be selectively connected to a ground or a power source according to the type of the.

Specifically, for example, when an image sensor of 250,000 pixels is attached to the set side, the two identification terminals are grounded, so that the identification detection section 6 logically outputs "00". When the identification signal Si is output and the 380,000-pixel image sensor is attached to the set side, one identification terminal is grounded, and the other identification terminal is connected to the power supply. Outputs the identification signal Si of "01" logically.

When an image sensor of 180,000 pixels is attached to the set side, the other identification terminal is grounded and one identification terminal is connected to the power supply, whereby the identification detection section 6 receives a logic signal. When the image sensor of 360,000 pixels is attached to the set side, the above-mentioned two identification terminals are connected to the power source, so that the identification detection unit 6 logically outputs the identification signal of “10”. "1
The identification signal of "1" is output.

The identification signal Si from the identification detector 6 is
It is supplied to the system controller 7 (see FIG. 1) that controls this camera device. The system controller 7 outputs a control signal corresponding to the attribute of the identification signal Si to the video signal processing circuit 4 and the electronic iris circuit 5 based on the attribute (logical value) of the identification signal Si from the identification detection unit 6. .

The electronic iris circuit 5 detects the magnitude of, for example, the luminance signal Sy from the video signal processing circuit 4, and a detection circuit 21 for temporally integrating, and an output voltage (that is, the output voltage from the detection circuit 21. The timing generation circuit 22 that determines the shutter speed based on the detected voltage) Vy and outputs the number of electronic shutter pulses Ps corresponding to the determined shutter speed, and the electronic shutter pulse Ps output from the timing generation circuit 22. And a drive circuit 23 that generates a substrate application signal Ss by superimposing it on the substrate potential Vs and outputs it to the image sensor 3.

The timing generation circuit 22 compares the detection voltage Vy from the detection circuit 21 with the reference voltage Vr and outputs the difference Sa between them, and the difference signal Sa from the comparison circuit 31. Based on the level, a load value conversion circuit 33 that converts the output value of the electronic shutter pulse Ps into a load value Ld that is stored in a load value counter 43 of a shutter step circuit 32, which will be described later, and a load value Ld for the number indicated by the load value Ld , And a shutter step circuit 32 that outputs an electronic shutter pulse Ps.

The shutter step circuit 32, as shown in FIG. 2, generates a vertical synchronizing signal VD and a horizontal synchronizing signal HD based on a reference clock generating section 41 and an input of the reference clock Pc from the reference clock generating section 41. A synchronizing signal generating circuit 42 to be generated and a load value counter 4 described later.
3, a V counter 44, an H counter 45, a step counter 46, and a switching circuit 47.

The reference clock generator 41 has the reference clocks P having different oscillation frequencies (clock frequencies).
A plurality of (four in the present embodiment) reference clock generators 48a to 48d configured to generate c1 to Pc4, for example, a crystal oscillator, and a system controller among these four reference clock generators 48a to 48d. 7 (Fig. 1
A reference clock generator is selected based on the content of the control signal Sc1 from the reference signal generator) and the switching circuit 49 outputs the reference clock from the selected reference clock generator to various circuit groups. ing.

In the following description, the reference clock generator 41
The reference clocks selected and output in step S1 are referred to as reference clocks Pc for convenience. When the reference clocks are individually referred to, they are referred to as a first reference clock Pc1, a second reference clock Pc2 ... Enter.

The load value counter 43 counts the electronic shutter pulse Ps based on the input of the vertical synchronizing signal VD from the synchronizing signal generating circuit 42, and stores the stored load value Ld for each counting of the electronic shutter pulse Ps. It is a circuit that updates -1 and is configured to output the count stop pulse signal Se when the load value Ld becomes "0".

The V counter 44 has a synchronizing signal generating circuit 42.
Counting the input of the horizontal synchronizing signal HD from the synchronizing signal generating circuit 42 based on the input of the vertical synchronizing signal VD from
It is a circuit that generates a vertical blanking pulse signal Svb that falls at the start of the vertical blanking period and rises at the end of the vertical blanking period.

The H counter 45 has a synchronizing signal generating circuit 42.
On the basis of the input of the horizontal synchronizing signal HD from the reference clock generator 41, the input of the selected reference clock Pc from the reference clock generating unit 41 is counted, and one pulse signal Sh rising during the horizontal blanking period is generated to generate the pulse. The circuit outputs the signal Sh as an electronic shutter pulse Ps. This H counter 4
5 stops counting based on the input of the counting stop pulse signal Se from the load value counter 43.

The step counter 46 counts the input of the selected reference clock Pc from the reference clock generator 41 based on the fall of the vertical retrace pulse signal Svb from the V counter 44, and the counted value is obtained. It is a circuit that generates several kinds of frequency-divided clocks Sfd stepwise on the basis of these and outputs these frequency-divided clocks Sfd as electronic shutter pulses Ps. Here, as shown in FIG. 3, an example in which the divide-by-8 clock Sfd1 is output in the low-speed shutter area, the divide-by-4 clock Sfd2 is output in the medium-speed shutter area, and the divide-by-2 clock Sfd3 is output in the high-speed shutter area. Indicates.

Specifically, as shown in FIG. 4, the step counter circuit 46 counts the reference clock Pc based on the input of the vertical retrace pulse signal Svb, and divides the reference clock Pc by eight. Based on the input of the counting start pulse signal Sd1 from the first counter 51 which outputs Sfd1 and the first control counter 54, which will be described later, the reference clock Pc is counted and the quarter clock Sfd2 of the reference clock Pc is divided. A counting start pulse signal Sd2 from a second counter 52 that outputs and a second control counter 55 that will be described later.
3rd counter 53 which counts the reference clock Pc based on the input of 1 and outputs the frequency-divided clock Sfd3 of the reference clock Pc.

The first counter 51 has a counting range of "1" to "8", and the counting is performed so as to return to "1" after "8". Then, each time the count value becomes "1", one frequency-divided clock Sfd1
Is output. Therefore, normally, the first counter 51 outputs one divided-by-eight clock Sfd1 at the time when the vertical retrace pulse signal Svb falls, and thereafter, one is generated every time eight reference clocks Pc are counted. The divide-by-8 clock Sfd1 is output.

The second counter 52 has a counting range of "1" to "4", and the counting is performed so as to return to "1" after "4". Then, each time the count value becomes "1", one divided-by-4 clock Sfd2
Is output. Therefore, from this second counter 52,
When the counting start pulse signal Sd1 from the first control counter 54 is input, one divide-by-4 clock Sfd2 is output, and thereafter, every time four reference clocks Pc are counted, one divide-by-4 clock Sfd2 is output. Will be output.

The third counter 53 has a counting range of "1" to "2", and the counting is performed so as to return to "1" after "2". Then, each time the count value becomes "1", one divided-by-2 clock Sfd3
Is output. Therefore, from this third counter 53,
When the counting start pulse signal Sd2 from the second control counter 55 is input, one divided-by-2 clock Sfd3 is output, and thereafter, every time two reference clocks Pc are counted, one divided-by-2 clock Sfd3 is output. Will be output.

Further, the step counter circuit 46 is
In addition to the counter group, the frequency-divided clock Sfd1 output from the first counter 51 is counted to register R
When it becomes the same as the predetermined count value stored in 1,
A first control counter 54 that outputs a count stop pulse signal Se1 to the first counter 51 and a count start pulse signal Sd1 to the second counter 52, and a second counter 5
When the frequency-divided clock Sfd2 output from 2 is counted and becomes equal to the predetermined count value stored in the register R2, the count stop pulse signal Se2 is sent to the second counter 52.
To output a count start pulse signal S to the third counter 53.
It has a second control counter 55 that outputs d2.

Therefore, the first counter 51 starts counting the reference clock Pc based on the input of the vertical retrace pulse signal Svb from the V counter 44, and the first control counter 54 or the load value counter 43 starts counting. The frequency-divided clock Sfd1 of the reference clock Pc is output until the counting stop pulse signal Se1 or Se is input.

The second counter 52 starts counting the reference clock Pc based on the input of the count start pulse signal Sd1 from the first control counter 54, and the second control counter 55 or the load value counter 43 Until the counting stop pulse signal Se2 or Se is input, the quarter clock Sfd2 of the reference clock Pc is output.

The third counter 53 starts counting the reference clock Pc based on the input of the count start pulse signal Sd2 from the second control counter 55, and the second control counter 55 or the load value counter 43 The halved clock Sfd3 of the reference clock Pc is output until the counting stop pulse signal Se2 or Se is input.

The switching circuit 47 shown in FIG. 2 selectively switches the pulse signal Sh from the H counter 45 and several kinds of divided clocks Sfd from the step counter 46 based on the output from the V counter 44. This is a circuit that outputs as an electronic shutter pulse Ps.

Specifically, this switching circuit 47
Is an analog switch having, for example, an FET, and is connected to the output side of the step counter 46.
Fixed contact 47a, a second fixed contact 47b connected to the output side of the H counter 45, and a movable contact 47 connected to the output terminal φout side of the shutter step circuit 32.
c. The movable contact 47c is used for the V counter 44.
When the vertical retrace pulse signal Svb output from is at a low level, it is electrically connected to the first fixed contact 47a, and when the vertical retrace pulse signal Svb is at a high level, it is electrically connected to the second fixed contact 47b. Switch to be connected.

That is, while the vertical retrace pulse signal Svb output from the V counter 44 is at a high level, the pulse signal Sh output during the horizontal retrace period from the H counter 45 is selected and the vertical retrace pulse signal Svb is selected. During the period when the line pulse signal Svb is at the low level, it is configured to select several kinds of divided clocks Sfd output during the vertical retrace period from the step counter 46 and output them as the electronic shutter pulse Ps. .

Therefore, from the output terminal φout of the switching circuit 47, the pulse signal Sh synchronized with the horizontal blanking period from the H counter 45 is output as the electronic shutter pulse Ps in the effective video period and in the vertical blanking period. Means that several kinds of frequency-divided clocks Sfd from the step counter 46 are output as electronic shutter pulses Ps.

When the fastest shutter speed is selected in the 250,000 pixel image sensor 3A, for example, as shown in FIG. 3, the electronic shutter pulse Ps is set.
However, if the 380,000-pixel image sensor 3B is mounted and the fastest shutter speed is selected, the clock frequency of the second reference clock Pc2 used is The clock frequency is 14 MHz, and the clock frequency of the first reference clock Pc1 used in the 250,000-pixel image sensor 3A is 9.5 MHz.
It has a higher frequency than

From this, the pulse width of the electronic shutter pulse Ps in the 380,000 pixel image sensor 3B is 25.
When the electronic shutter pulse Ps is generated with the same load value Ld as in the case of the 10-megapixel image sensor 3A,
As shown in FIG. 7, the final output time of the electronic shutter pulse Ps at the 380,000-pixel image sensor 3A arrives at the time tb, which is earlier than in the case of the 250,000-pixel image sensor 3A, instead of at the ta. There is a problem that a desired high shutter speed (for example, 1/100000) cannot be obtained.

Here, for example, the exposure period determined by the fastest shutter speed of the 250,000 pixel image sensor 3A is Ta.
When the exposure period determined by the fastest shutter speed of the 380,000-pixel image sensor 3B is Tb, the shutter speed error rate n of both is expressed by the following relational expression.

[0077]

[Equation 1]

Therefore, with respect to the other image sensors 3B to 3D except the reference image sensor (for example, the 250,000 pixel image sensor 3A), the final output time of the electronic shutter pulse Ps at the fastest shutter speed becomes the reference. With respect to the image sensor 3A, the shutter speed error rate n increases as the time difference increases, and the exposure period for the same shutter speed varies among the image sensors 3A to 3D.

Generally, the absolute accuracy of the shutter speed of the electronic iris system is required in the high-speed shutter area within the vertical blanking period, and when step counting is performed with a plurality of reference clocks Pc1 to Pc4 each having a different clock frequency. The point is how far the absolute values of the fastest shutter speeds set in the electronic iris system are aligned with respect to the reference clocks Pc1 to Pc4.

Therefore, in the present embodiment, for example, the final output time t of the electronic shutter pulse Ps at the fastest shutter speed in the 250,000 pixel image sensor 3A.
For the other image sensors 3B to 3D with a as a reference, by shifting (delaying) the whole of several kinds of divided clocks Sfd (that is, the electronic shutter pulse Ps) output within the vertical blanking period, The final output time of the other image sensors 3B to 3D at the highest shutter speed is set to match the 250,000 pixel image sensor 3A.

That is, in FIG. 3, assuming that the time point ta is the shutter step corresponding to the fastest shutter speed (the final output time point of the electronic shutter pulse Ps) in FIG.
A certain reference clock (for example, the first reference clock Pc1)
Electronic shutter pulse Ps obtained by counting
Of the final output time ta of another reference clock (for example, the second reference clock
One of the modes has a preset value so that the final output time point tb of the electronic shutter pulse Ps obtained by counting the reference clock Pc2) of 1) coincides at the time point ta.

As a result, wrinkling due to different clock frequencies can be brought to the low-speed shutter area with relatively moderate accuracy, that is, the beginning of the vertical blanking period, and the absolute accuracy of the shutter speed in the electronic iris system can be substantially reduced. Can be improved.

Therefore, in the shutter step circuit 32 according to the present embodiment, even when the load value Ld is the same, the final output time of the electronic shutter pulse Ps, particularly the vertical blanking period, is obtained at the plurality of reference clocks Pc. A preset value generation circuit 61 (see FIGS. 2 and 4) that generates a preset value for making the final output time points the same in the high-speed shutter area is provided.

That is, the shutter step circuit 32
Is the reference clock P in the first counter 51 shown in FIG.
The frequency-divided clock Sfd1 of c is generated, and the frequency-divided clock Sfd1 is used as the electronic shutter pulse Ps in the low-speed shutter region.
However, this first counter 51
Instead of starting the counting operation in step 1 from the initial value "1", start from a predetermined preset value other than the initial value,
By shifting the output time of the electronic shutter pulse Ps that is first output after entering the vertical blanking period, the final output time of the electronic shutter pulse Ps at the fastest shutter speed can be made to coincide with each other in each of the reference clocks Pc1 to Pc4. Becomes

The configuration of the preset value generation circuit 61 according to the present embodiment will be specifically described. The preset value generation circuit 61 has four types of reference clocks Pc1 to Pc4 used, as shown in FIG. Four registers R11 to R14 (or ROM: hereinafter simply referred to as registers) corresponding to (each having a different clock frequency), and a control signal Sc2 from the system controller 7 among these four registers R11 to R14. A switching circuit 62 for selectively selecting one register on the basis of the above is provided.

When the electronic shutter pulse Ps is generated by the corresponding reference clocks Pc1 to Pc4 in the four registers R11 to R14, the electronic shutter pulse Ps at the fastest shutter speed (eg, 1/100000) is generated. Of the reference clocks Pc1 to Pc
4, the matching preset values Dp1 to Dp4 are registered.

The preset values Dp1 to Dp4 registered in the four registers R11 to R14 are the reference clock frequency, the fastest shutter speed in this camera device,
It is possible to easily determine each clock frequency of each of the reference clocks Pc1 to Pc4 and the frequency division steps of the several types of frequency division clocks Sfd generated by the step counter as parameters. When the clock frequency of the reference clock Pc1 for the 250,000 pixel image sensor 3A is used as the reference, the first frequency corresponding to the clock frequency
An initial value "1" is registered as a preset value Dp1 in the register R11, etc.

In the following description, the preset value selected and output by the preset value generating circuit 61 will be referred to as a preset value Dp for convenience, and if each preset value is individually referred to, the first preset value will be described. Preset value Dp1,
The second preset value Dp2 ...

Next, the camera device according to this embodiment,
In particular, the processing operation in the timing generation circuit 22 will be described.

First, the processing operation in the case where the 250,000 pixel image sensor 3A is attached to the set will be described.
The image sensor 3A includes identification pins 11a and 11
Since b is not provided, the identification detection unit 6 outputs the identification signal Si having the logical value “00” and supplies it to the system controller 7.

The system controller 7 includes the identification detector 6
Based on the input of the identification signal Si from the control signal S, the control signal S has a content for selecting the first reference clock generator 48a for the switching circuit 49 of the reference clock generation unit 41.
c1 is output, and the control signal Sc2 having the content for selecting the first register R11 or the like is output to the switching circuit 62 of the preset value generation circuit 61.

The reference clock generator 41 receives the first control signal Sc1 from the system controller 7 based on the input of the control signal Sc1.
And outputs the first reference clock Pc1 having a clock frequency of 9.5 MHz through the switching circuit 49.

The preset value generating circuit 61 receives the control signal Sc2 from the system controller 7, and
The first register R11 or the like in which the initial value "1" is registered as the preset value is selected, and the preset value Dp1 is set to the first value of the step counter 46 through the switching circuit 62.
To the counter 51. The first counter 51 holds the preset value Dp1 output from the preset value generation circuit 61.

The level of the luminance signal Sy output from the video signal processing circuit 4 is low, and the output voltage (detection voltage) Vy from the detection circuit 21 is the reference voltage V in the comparison circuit 31.
If it is slightly higher than r, or equal to or lower than the reference voltage Vr, a low shutter speed (for example, when the final output time of the electronic shutter pulse Ps is within the effective video period, (In the case of a low-speed shutter area or a medium-speed shutter area within the vertical blanking period)
Is output from the load value conversion circuit 33, the level of the luminance signal Sy is very high, and the detection voltage Vy is
Is significantly higher than the reference voltage Vr, the load value Ld indicating the high shutter speed (for example, when the final output time of the electronic shutter pulse Ps is in the high speed shutter area within the vertical blanking period) is converted into the load value. It is output from the circuit 33.

The load value Ld from the load value conversion circuit 33 is stored in the load value counter 43 of the shutter step circuit 32. The load value counter 43 starts counting the electronic shutter pulses Ps based on the input of the vertical synchronizing signal VD output from the synchronizing signal generating circuit 42.

On the other hand, V of the shutter step circuit 32 is
The counter 44 counts the horizontal synchronizing signal HD based on the input of the vertical synchronizing signal VD from the synchronizing signal generating circuit 42,
A vertical blanking pulse signal S which becomes a low level during the vertical blanking period
Output vb. The vertical retrace pulse signal Svb is supplied to the switching circuit 47 and the step counter 46. Further, the H counter 45 receives the horizontal synchronizing signal HD from the synchronizing signal generating circuit 42 and selects the first reference clock Dp1 selected from the reference clock generating unit 41.
Is counted, and one pulse signal Sh is generated and output during the horizontal blanking period. The pulse signal Sh is supplied to the second fixed contact 47b of the switching circuit 47.

The switching circuit 47 switches the movable contact 47c to the second fixed contact 47b side while the vertical blanking pulse signal Svb is at a high level, that is, during the effective image period, and the vertical blanking pulse signal Svb is low. The duration of the level,
That is, in the vertical blanking period, the movable contact 47c is switched to the first fixed contact 47a side.

Therefore, during the effective video period, H
The pulse signal Sh output from the counter 45 and synchronized with the horizontal blanking period is output as the electronic shutter pulse Ps through the switching circuit 47.

The load value Ld stored in the load value counter 43 corresponds to a low shutter speed, and the final output time of the electronic shutter pulse Ps arrives at a certain time within the effective video period. Switching circuit 47 to indicate the shutter speed of
At the stage where the pulse signal Sh from the H counter 45 is output from the output terminal φout of the electronic shutter pulse Ps as the electronic shutter pulse Ps, the count stop pulse signal Se is output from the load value counter 43. In the middle, the counting by the H counter 45 is stopped, and the exposure period is started from the final output time point of the electronic shutter pulse Ps immediately before the stop.

On the other hand, when the shutter speed indicated by the load value Ld is within the vertical blanking period, the pulse signal Sh synchronized with the horizontal blanking period from the H counter 45 becomes the electronic shutter pulse Ps during the effective video period. At the time of the output and the subsequent vertical blanking period, the movable contact 47c of the switching circuit 47 is switched to the first fixed contact 47a side, and this time, several kinds of divided clocks output from the step counter 46 are output. Sfd is the electronic shutter pulse P
will be output as s.

In the step counter 46, the first counter 51 starts counting the first reference clock Pc1 when the vertical blanking period is started. Is already the preset value generation circuit 6
Since the first preset value Dp1 from 1 is held, the counting is started from the preset value Dp1. Now, since the target is the 250,000-pixel image sensor 3A, the initial value "1" is set in the first counter 51.
Is held. Therefore, one frequency-divided clock Sfd1 is output when the vertical blanking period starts, and thereafter, the frequency-divided clock Sfd1 is output each time eight first reference clocks Pc1 are counted. The divide-by-8 clock Sfd1 output from the first counter 51 is used in the switching circuit 47.
Is output as an electronic shutter pulse Ps.

At this time, the first control counter 54 outputs the divide-by-8 clock S output from the first counter 51.
fd1 is counted, and when the count value reaches the predetermined count value stored in the register R1, the count stop pulse signal Se1 is output to the first counter 51 and the second counter 52 is counted. The start pulse signal Sd1 is output.
The first counter 51 stops the counting operation of the first reference clock Pc1 based on the input of the count stop pulse signal Se1 from the first control counter 54.

When the counting operation of the first counter 51 is completed, the counting operation of the second counter 52 is started this time. The second counter 52 starts counting the first reference clock Pc1 based on the input of the count start pulse signal Sd1 from the first control counter 54,
The divided clock Sfd2 of the reference clock Pc1 is output. This divided-by-4 clock Sfd2 is used in the switching circuit 4
It is output as an electronic shutter pulse Ps through 7.

At this time, the second control counter 55 outputs the divided-by-4 clock S output from the second counter 52.
fd2 is counted, and when the count value reaches the predetermined count value stored in the register R2, the count stop pulse signal Se2 is output to the second counter 52 and the third counter 53 is counted. The start pulse signal Sd2 is output.
The second counter 52 stops the counting operation of the first reference clock Sc1 based on the input of the count stop pulse signal Se2 from the second control counter 55.

When the counting operation of the second counter 52 is completed, the counting operation of the third counter 53 is started this time. The third counter 53 starts counting the first reference clock Sc1 based on the input of the count start pulse signal Sd2 from the second control counter 55,
The divided clock Sfd3 of the reference clock Sc1 is output. This divided-by-2 clock Sfd3 is supplied to the switching circuit 4
It is output as an electronic shutter pulse Ps through 7.

When the count stop pulse signal Se output from the load value counter 43 is input to the third counter 55 when the count of the load value Ld in the load value counter 43 is completed, The counting by the third counter 55 is stopped.

Here, when the shutter speed indicated by the load value Ld is within the low speed shutter area in the vertical blanking period, the load value counter 43 outputs the value at the stage where the first counter 51 is counting. Since the counting stop pulse signal Se is output, the final output time of the electronic shutter pulse Ps is reached at the stage when the divide-by-8 clock Sfd1 from the first counter 51 is being output as the electronic shutter pulse Ps, and from the final output time. The exposure period will start.

When the shutter speed indicated by the load value Ld is within the medium-speed shutter area of the vertical blanking period, the load value counter 43 outputs the value while the second counter 52 is counting. Since the counting stop pulse signal Se is output, after the predetermined number of divided-by-8 clocks Sfd1 are output from the first counter 51, the divided-by-4 clock Sfd2 from the second counter 52 is used as the electronic shutter pulse. The final output time of the electronic shutter pulse Ps is reached at the stage of being output as Ps, and the exposure period is started from the final output time.

When the shutter speed indicated by the load value Ld is within the high-speed shutter area during the vertical retrace line period, the load value counter 43 counts when the third counter 53 is counting. Since the stop pulse signal Se is output, after the predetermined number of divided-by-4 clocks Sfd2 are output from the second counter 52, the divided-by-2 clock Sfd3 from the third counter 53 is changed to the electronic shutter pulse Ps. Is output, the final output time of the electronic shutter pulse Ps is reached, and the exposure period is started from the final output time.

Next, for example, when the 380,000-pixel image sensor 3B is mounted on the set side, the identification detection unit 6 outputs the identification signal Si indicating the logical value "01".
From the system controller 7, the reference clock generator 4
The control signal Sc1 having the content for selecting the second reference clock Pc2 is output to the first switching circuit 49,
The control signal Sc2 having the content for selecting the second preset value Dp2 is output to the switching circuit 62 of the preset value generation circuit 61.

As a result, H of the shutter step circuit 32
The counter 45 and the step counter 46 are supplied with the second reference clock Pc2, and the first counter 51 of the step counter 46 is supplied with the second preset value Dp2.

When the shutter speed indicated by the load value Ld is within the effective video period, the H counter 45 is used as in the case of the 250,000 pixel image sensor 3A.
From the pulse signal Sh synchronized with the horizontal blanking period
Is output as the electronic shutter pulse Ps, the count in the load value counter 43 is completed,
The final output time of the electronic shutter pulse Ps will come within the effective video period.

On the other hand, when the shutter speed indicated by the load value Ld is within the vertical blanking period, unlike the case of the 250,000-pixel image sensor 3A, the first counter 51 has a second value different from the initial value. Since the counting is started from the preset value Dp2 of, the first divided-by-8 clock Sfd1 is not output at the start of the vertical blanking period, and the counting is started from the second preset value Dp2. The first frequency-divided clock Sfd1 is first output when the clock returns from "8" to "1". For example, when the second preset value Dp2 is, for example, "3", the first counter 51 starts counting from "3", and then the second reference clock Pc2 is set to 6
At the time of counting the number, the first divided-by-8 clock Sfd1 is output.

As a result, the several kinds of frequency-divided clocks Sfd sequentially output from the step counter 46 are the six second reference clocks P from the start of the vertical blanking period.
It is output at a timing delayed by a time corresponding to c2. In this case, the clock frequency of the second reference clock Pc2 is equal to the reference first reference clock Pc.
Since the clock frequency is higher than the clock frequency of 1 and its pulse width is short, the first output divided-by-8 clock Sfd1 is delayed by a time corresponding to, for example, six second reference clocks Pc2. As shown in FIG. 3, the final output time point tb of the electronic shutter pulse Ps at the fastest shutter speed almost coincides with the case of the 250,000 pixel image sensor 3A (time point ta).

In other words, the 250,000 pixel image sensor 3
The exposure period Ta when the fastest shutter speed is selected in A and the exposure period Tb when the fastest shutter speed is selected in the 380,000-pixel image sensor 3B are substantially the same period. The error rate n is very small.

This is the same not only when the 180,000-pixel image sensor 3C is mounted on the set side, but also when the 360,000-pixel image sensor 3D is mounted. When the 180,000-pixel image sensor 3C is mounted, From the connection state of the identification terminals in the identification detection unit 6 (connection at the time of design),
Since the identification signal Si having the logical value “10” is output from the identification detection unit 6, the third reference clock Pc3 is output from the reference clock generation unit 41, and the first counter 51 of the step counter 46 is The selected third preset value Dp3 from the preset value generation circuit 61 is supplied.

Similarly, when the 360,000-pixel image sensor 3D is attached to the set side, the logical value "1" is output from the identification detection section 6 based on the connection state of the identification terminal in the identification detection section 6.
Since the identification signal Si of "1" is output, the reference clock generation unit 41 outputs the fourth reference clock Pc4,
The selected fourth preset value Dp4 from the preset value generation circuit 61 is supplied to the first counter 51 of the step counter 46.

Even when these 18-sided pixel image sensor 3C and 360,000-pixel image sensor 3D are mounted, the final output time of both electronic shutter pulses at the fastest shutter speed is 250,000-pixel image sensor 3A. Will almost match.

As described above, in the camera apparatus according to the present embodiment, the step counter 46 that outputs several kinds of frequency-divided clocks Sfd as the electronic shutter pulse Ps in the vertical blanking period, particularly the first frequency-divided clock Sfd1. First (clock in this embodiment divided by 8) for generating and outputting
Since the preset value Dp corresponding to the reference clock Pc to be used is supplied to the counter 51 of No. 1 and the counting is started from the preset value Dp, the reference clock serving as the reference among the plurality of reference clocks Pc1 to Pc4. Pc1
Several kinds of frequency-divided clocks Sfd generated based on the reference clocks other than are all delayed in time according to the reference clocks, and the final output time of the electronic shutter pulse Ps at the fastest shutter speed. Can be substantially matched in each of the reference clocks Pc1 to Pc4.

As a result, even for a camera device in which a plurality of modes having different clock frequencies coexist, the circuit system for generating the electronic shutter pulse Ps and the load value Ld for determining the shutter speed should be shared by one type each. Therefore, simplification of the circuit configuration and reduction in size and weight of the device itself can be promoted.

Moreover, as described above, the load value Ld is set to 1
Since it can be shared by types, the algorithm of the electronic iris system can be simplified.

In the above embodiment, several kinds of divided clocks Sfd are divided by 8 divided clocks / 4 divided clocks /
As a step of each divided clock in FIG. 3, first, four divided clocks Sfd1 are used.
Although the example in which four four-division clocks Sfd2 are output after that and seven seven-division clocks Sfd3 are output after that, various types of the divided clocks Sfd can be selected from various divided clocks. Various steps can be adopted as the steps of each divided clock.

Further, the configuration of the identification detecting section 6 is such that two identification terminals selectively connected to the power supply or the ground are designed at the time of designing in accordance with the type of the image sensor attached to the set side. Although the type of the image sensor 3 mounted on the set side, that is, the reference clock Pc to be used is identified based on the connection state of the identification terminal, other operations (not shown here) are installed in the camera device. Of the various operation keys on the panel, a code generation circuit that converts key input data input based on the operation of the mode selection key into an identification code is connected to the system controller 7, and the identification code from the code generation circuit is connected to the system controller. 7 to supply control signals Sc1 and Sc2 from the system controller 7 according to the contents of the identification code. It may be allowed to force.

[0124]

As described above, according to the camera device of the present invention, it is converted into the signal charge of the amount corresponding to the amount of the light incident from the subject during the exposure period and is output as the image pickup signal, and Based on the supply of electronic shutter pulses from the outside,
A solid-state image sensor having an electronic shutter function for sweeping away accumulated charges, and timing for timing control of the final output time point of the electronic shutter pulse, which is the start time point of the exposure period, according to the level of the image pickup signal output from the solid-state image sensor In a camera device comprising a generation circuit, the timing generation circuit, based on the count of the reference clock,
An electronic shutter pulse generation circuit that outputs an electronic shutter pulse whose generation interval is variable stepwise in the vertical blanking period, and the final output time point of the electronic shutter pulse are the same for a plurality of reference clocks with different frequencies. Since a preset value generation circuit that generates a preset value and supplies the electronic shutter pulse generation circuit as a preset count value is provided, even for a camera device in which a plurality of modes having different clock frequencies are mixed,
The circuit system for generating the electronic shutter pulse and the counter load value for determining the shutter speed can be shared by one type respectively, and the simplification of the circuit configuration and the reduction in size and weight of the apparatus itself can be promoted.

Further, according to the timing generating circuit for the camera device of the present invention, based on the counting of the reference clock,
An electronic shutter pulse generation circuit that outputs an electronic shutter pulse whose generation interval is variable stepwise in the vertical blanking period, and the final output time point of the electronic shutter pulse are the same for a plurality of reference clocks with different frequencies. Since a preset value generation circuit that generates a preset value and supplies it to the electronic shutter pulse generation circuit as a preset count value is provided, the shutter is released even for a camera device in which a plurality of modes having different clock frequencies are mixed. 1 for the counter load value that determines the speed
The electronic iris system can be shared by types, and simplification of the algorithm of the electronic iris system and simplification of the circuit configuration can be realized.

[Brief description of drawings]

FIG. 1 is an example of an embodiment in which a camera device according to the present invention is applied to a compatible video camera in which image sensors having different numbers of pixels can be selectively mounted (hereinafter, simply referred to as a camera device according to the embodiment). FIG.

FIG. 2 is a circuit diagram showing a configuration of a shutter step circuit which is one of the constituent elements of the timing generation circuit in the camera device according to the present embodiment.

FIG. 3 is a diagram illustrating a first camera device according to the present embodiment.
3 is a timing chart showing an output form of an electronic shutter pulse based on the reference clock of FIG. 3 and an output form of an electronic shutter pulse based on a second reference clock.

FIG. 4 is a circuit diagram showing a configuration of a step counter incorporated in a shutter step circuit.

FIG. 5 is a timing chart showing a general shutter step timing in the electronic iris system.

FIG. 6 is a circuit diagram showing a configuration of a shutter step circuit in a timing generation circuit according to a conventional example.

FIG. 7 is a timing chart showing an output form of an electronic shutter pulse based on a certain reference clock and an output form of an electronic shutter pulse based on another reference clock in the timing generation circuit according to the conventional example.

[Explanation of symbols]

1 Zoom Lens Unit, 2 Optical Filter, 3 Image Sensor, 4 Video Signal Processing Circuit, 5 Electronic Iris Circuit, 6 Identification Detection Unit, 7 System Controller, 11
a and 11b Identification pin, 12a and 12b Identification terminal, 21 Detection circuit, 22 Timing generation circuit, 23
Drive circuit, 31 comparison circuit, 32 shutter step circuit, 33 load value conversion circuit, 41 reference clock generation unit, 42 synchronization signal generation circuit, 43 load value counter, 44 V counter, 45 H counter, 46 step counter, 47 switching circuit , 51 first counter, 52 second counter, 53 third counter, 54 first control counter, 55 second control counter, 61 preset value generation circuit

Claims (10)

[Claims] 1. An accumulated charge is converted into a signal charge of an amount corresponding to the amount of light incident from a subject during an exposure period and output as an image pickup signal, and the accumulated charge is supplied based on supply of an electronic shutter pulse from the outside. A solid-state image sensor having an electronic shutter function for sweeping away; a timing generation circuit for timing-controlling the final output time point of the electronic shutter pulse, which is the start time point of the exposure period, according to the level of the image pickup signal output from the solid-state image sensor In the camera device including the above, the timing generation circuit includes an electronic shutter pulse generation circuit that outputs an electronic shutter pulse whose generation interval is stepwise changed in a vertical blanking period based on a count of a reference clock, A preset value that makes the final output time of the electronic shutter pulse equal for multiple reference clocks with different frequencies. And a preset value generation circuit for generating the value as a preset count value and supplying the electronic shutter pulse generation circuit with the preset value as a preset count value. 2. The electronic shutter pulse generation circuit, a counter for counting an input reference clock, and stepwise generates several kinds of frequency-divided clocks based on the count value of the counter, and the electronic shutter pulse generation circuit. 2. The camera device according to claim 1, further comprising: a divided clock generation circuit for outputting as. 3. The preset value generating circuit is activated when a highest shutter speed is required, and a preset value holding means for holding a preset value according to the type of a reference clock used, and a solid-state image sensor incorporated therein. An identification detecting section for detecting the type of a reference clock for driving the reference value; and a preset value extracting section for extracting a preset value corresponding to the decoding result from the preset value holding section based on the detection result from the identification detecting section. The camera device according to claim 1, further comprising: 4. The camera according to claim 3, wherein the identification detection unit has a type identification terminal of the solid-state imaging device, and deciphers the type of the reference clock based on the connection state. apparatus. 5. The identification detection section has a code generation circuit for generating an identification code of the solid-state image pickup device based on a key input from a type setting key of an operation panel, and the identification circuit from the code generation circuit. Based on the identification code
4. The camera device according to claim 3, wherein the type of the reference clock is detected. 6. The accumulated charge is converted into a signal charge of an amount corresponding to the amount of light incident from a subject during an exposure period and output as an image pickup signal, and the accumulated charge is supplied based on the supply of an electronic shutter pulse from the outside. A timing generation circuit for a camera device that controls the timing of the final output time of the electronic shutter pulse, which is the start time of the exposure period, according to the level of the imaging signal output from the solid-state imaging device having the electronic shutter function for sweeping An electronic shutter pulse generation circuit that outputs an electronic shutter pulse whose generation interval is variable stepwise in the vertical blanking period based on the clock count, and a final output time point of the electronic shutter pulse is a plurality of different frequencies. Generates the same preset value for each reference clock and presets it in the electronic shutter pulse generation circuit Camera device for a timing generation circuit and having a preset value generating circuit for supplying a numerical value. 7. The electronic shutter pulse generation circuit, a counter for counting an input reference clock, and stepwise generates several kinds of divided clocks based on the count value of the counter, and the electronic shutter pulse generation circuit. 7. The timing generation circuit for a camera device according to claim 6, further comprising: a divided clock generation circuit for outputting as. 8. The preset value generation circuit is activated when the fastest shutter speed is required, and a preset value holding means for holding a preset value according to the type of reference clock used, and a solid-state image sensor incorporated therein. An identification detecting section for detecting the type of a reference clock for driving the reference value; and a preset value extracting section for extracting a preset value corresponding to the decoding result from the preset value holding section based on the detection result from the identification detecting section. The timing generation circuit for a camera device according to claim 6, further comprising: 9. The camera according to claim 8, wherein the identification detection unit has a type identification terminal of the solid-state imaging device, and deciphers the type of the reference clock based on a connection state thereof. Timing generator for equipment. 10. The identification detection unit includes a code generation circuit that generates an identification code of the solid-state image pickup device based on a key input from a type setting key of an operation panel, and the identification signal from the code generation circuit. Based on the identification code
9. The timing generating circuit for a camera device according to claim 8, wherein the type of the reference clock is detected.