JP2001285705A - Timing signal generator and generation method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To set setting data for generating the various kinds of timing signals at high speed. SOLUTION: A timing pulse generation circuit 112 is provided with data setting circuits A 114, B 116 and C 118 for respectively outputting the plural setting data for generating the timing signals and the setting data are set to the timing pulse generation circuit 112 at the time of activating a camera and at timings corresponding to respective operation modes. The timing pulse generation circuit 112 generates the timing signals corresponding to the set data, supplies the generated timing signals to a solid-state image pickup device 100 and a processing circuit 106 and makes them perform operations corresponding to the timing signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing signal generator for generating a plurality of types of timing signals and a method for generating the same, for example, a drive control signal for driving a solid-state imaging device and a signal processing circuit. The present invention relates to a timing signal used, a timing signal generator for generating a timing signal such as a control signal for periodically controlling each circuit, and a method for generating the timing signal.

[0002]

2. Description of the Related Art In recent years, an image pickup apparatus which processes an image signal corresponding to a scene image received by a solid-state image pickup device, records the processed image signal on an information recording medium, or transmits the processed image signal to another device. It has been known. Such a device includes a control circuit that organically controls each functional unit such as an imaging unit, a signal processing unit, and a recording processing unit, and further generates a timing signal that defines a timing of operation of each unit. ,
A so-called timing generator is provided.

As such a signal generator, for example, Japanese Unexamined Patent Publication No. 10-257398 discloses a "solid-state image pickup device drive timing signal generator" capable of setting an output pulse φ in a programmable manner. The signal generator includes a plurality of frequency dividers for dividing the clock, a selector for dividing the frequency and selecting the clock according to the selected data, a counter for counting the selected clock, and decoding the output clock of the counter. A decoder for decoding according to the value, and control means for setting the selected data and the decoded value. As described in paragraph 0017, the selected data and the decoded value are set via the serial port. Was something.

[0004]

As described above, since the data setting for the signal generator is performed by the serial setting means, it takes a lot of time to set the data.
Due to the set time, there is a problem that the operation of the entire system including the signal generator is slowed down.

[0005] Recently, various solid-state imaging devices have been developed and employed in digital cameras. Such cameras have a variety of photographing functions. For example, the timing for driving the image sensor differs between when a still image is obtained and when a moving image is obtained. In addition, the image sensor may be driven so that pixels are thinned out and read. Therefore, timing signals corresponding to these driving methods are required. The image signal obtained by the image sensor is subjected to various kinds of signal processing, such as analog signal processing for an analog signal, digital conversion processing, and digital signal processing for calculating digital data of each pixel. In various kinds of signal processing, various timing signals for defining the processing timing need to be supplied to each unit.

Therefore, in order to cope with such multi-functionality, a large amount of data for defining various timings must be set in the signal generator, and the amount of information increases, and the setting time increases. Is also long. As a result, in a system equipped with a signal generator capable of setting data, for example, a time for performing data setting is required. For example, a startup time after power-on consumes much time for data setting, There is a problem that the performance of the entire system is deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a timing signal generator capable of setting a plurality of setting data, which is a source of various timing signals, at a high speed, and a method of generating the timing signal. .

[0008]

According to the present invention, there is provided a timing signal generating apparatus for generating a timing signal according to setting information.
First and second setting means for outputting first and second setting information for generating a timing signal, respectively;
The first setting information output from the first setting means is input, and the generating means generates a first timing signal according to the first setting information, and the second setting information output from the second setting means.
And control means for defining the timing of setting the setting information in the generation means, the generation means receiving the second setting information transferred at the timing specified by the control means,
A second timing signal according to the second setting information is generated.

According to another aspect of the present invention, there is provided a timing signal generator for generating a timing signal in accordance with setting information, comprising: a first and a second signal generator for generating a timing signal; Setting means for outputting setting information; generating means for generating and outputting a timing signal for driving an imaging means for generating a pixel signal corresponding to an optical image; and timing for setting second setting information in the generating means. Control means for defining, and transfer means for transferring the first and second setting information to the generation means, the transfer means for transferring the timing signal to the imaging means; Generating means generates a first timing signal corresponding to the first setting information output from the setting means, and generates the first timing signal at a timing specified by the control means. Generating a second timing signal corresponding to the second setting information transmission, the first and second generated
Is supplied to the imaging means connected via the transfer means.

Further, in order to solve the above-mentioned problem, the present invention relates to a timing signal generating method for generating a timing signal according to setting information, wherein the method comprises the steps of: providing first setting information for generating a timing signal; The first to output
Setting step, a second setting step of outputting second setting information for generating a timing signal, and a first setting step of receiving the first setting information output in the first setting step. Generating a first timing signal according to the information, receiving the second setting information output in the second setting step, and generating a timing signal according to the second setting information;
And an output step of outputting the timing signal generated in the generation step, wherein the first setting step outputs the first setting information when the system using the timing signal is activated.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a timing signal generator according to the present invention. In the following description, parts not directly related to the present invention are not shown and described, and reference numerals of signals are represented by reference numerals of connection lines in which the signals appear.

Referring to FIG. 1, a main part of a digital camera is shown. This camera includes a timing signal 102 for driving a solid-state imaging device 100 including a CCD image sensor or a CMOS image sensor, and a pixel output from the imaging device 100. signal
And a timing pulse generator 110 for generating a timing signal 108 for defining the processing timing in the processing circuit 106 for processing 104. The timing pulse generation device 110 includes a timing pulse generation circuit 112 for periodically generating a timing signal according to the setting data, and a plurality of setting data for setting the timing, waveform and repetition pattern of the timing signal in the generation circuit 112. , Data setting circuits 114, 116, 118,... The timing pulse generation circuit 112 includes data setting circuits 114, 116, 11
8 is generated in response to a control signal 132 supplied from the control circuit 130. The connection line 134 conceptually shown is connected to each part of the camera, and the control circuit 130 has a function of controlling the operation mode of the camera and a function of determining the timing of setting the setting data to the generation circuit 112. .

The data setting circuit A 114 in the present embodiment
Generates a plurality of setting data for generating a plurality of timing signals according to a shooting mode for shooting a moving image
The data setting circuit B 116 supplies a plurality of setting data to the generating circuit 112 for generating a plurality of timing signals corresponding to a shooting mode for shooting a still image. Further, the data setting circuit C 118 supplies a plurality of setting data for generating various timing signals required in a reproduction mode for reproducing image information recorded by the camera to the generation circuit 112.

In the present embodiment, the timing signal 102 includes a shift pulse for shifting the charge generated in the light receiving portion of the image pickup device 100 to the transfer path, a charge transfer pulse for driving the vertical and horizontal charge transfer paths, and a transfer path. Various timing waveforms such as a sweep signal for sweeping out the electric charges, a readout signal for reading out the transferred electric charges as an electric signal, and a feedthrough clamp pulse and a signal output clamp pulse for correlated double sampling of the readout pixel signal. Signal. The timing signal changes to a timing waveform of a different pattern according to the shooting mode, so that the imaging device 100 outputs a pixel signal corresponding to moving image shooting and still image shooting to its output 104. For example, when a still image is captured, an electronic shutter function or the like that generates an electric charge with an exposure time corresponding to an exposure value that is set for automatic exposure is realized by these drive signals.

The output 104 of the solid-state imaging device 100 is
6, the processing circuit 106 processes the pixel signal appearing at the input 104 at a timing according to the timing signal 108, and outputs the compression-coded image data to the output 120. The processing circuit 106 includes a clamp circuit that clamps a predetermined level of the pixel signal, a conversion circuit that converts the pixel signal into a digital value at a timing according to the pixel clock, and a color circuit of the pixel signal according to the color filter array of the image sensor. It includes a color separation circuit for separating components, a YC conversion circuit for generating YC data represented by luminance and color difference from pixel values of each color component, and a compression encoding circuit for compression encoding the YC data. The timing signal 108 includes timing signals such as a clamp pulse, a pixel clock, a color separation pulse, and a sample and hold signal for performing these processes, and a control signal for controlling the timing of the encoding process. In the embodiment, the plurality of signal output lines are indicated by one connection line 102 and 108 for simplification of the drawing.

An output 120 of the processing circuit 106 is connected to an output device such as a display device (not shown) or a recording / reproducing device for recording image data on an information recording medium, and the image data is displayed in a desired output form. , Recorded and transmitted. The image data recorded on the information recording medium is read out by the processing circuit 106 in the reproduction mode, subjected to decompression and decoding processing by the processing circuit 106, and stored in the image memory. Thereafter, a moving image or a still image is displayed on the display device in accordance with the output setting of the image information, and is transferred to a desired device. At this time, in the timing pulse generation device 110, the setting data is supplied from the data setting circuit C 118 to the generation circuit 112, so that the generation circuit 112 generates a timing signal for defining various processing timings for image reproduction. For example, the timing pulse generator 110 in the reproduction mode generates a timing signal necessary for the decompression decoding processing, a timing signal for performing image memory storage control when zooming an image, and the like.

As described above, the present embodiment has a plurality of data setting circuits for supplying setting data necessary for generating timing signals having different functions to the timing pulse generating circuit 112. Data can be set in accordance with the setting, and a plurality of various timing signals having different functions can be generated.

Therefore, when the power of the camera or the like is turned on, for example, when the camera is started with priority given to the imaging function, setting data for generating a drive signal and a timing signal for displaying a captured image on a monitor are provided. The generating device
By setting it within 110, it is possible to supply a minimum necessary timing signal to the camera after power-on, quickly start up the camera, check the video displayed on the monitor, and perform framing. Further, when a mode operation for capturing a still image without displaying the captured image on the monitor can be set, when the camera is started, a timing signal 102 and a timing signal for performing a still image capturing in response to a shutter release are provided. Setting data for generating the signal 108 can be set in the generating device 110, and the time from when the power is turned on to when the image can be captured can be shortened. When the image data is captured and processed in the image data stored in the image memory of the processing circuit 106, setting data for generating necessary timing pulses and control signals is further set by the generating device 110, so that the image data is stored in the image memory. The image can be processed according to the timing signal and recorded on an information recording medium or the like.

In the above, the configuration having a plurality of data setting circuits for respectively outputting setting data having different functions has been described. Further, an embodiment in which various timing signals are generated by a plurality of data setting methods will be described below. Referring to FIG. 2, there is shown a timing signal generator 200 according to the present embodiment.

The timing signal generator 200 includes a timing pulse generating circuit 210 for generating a timing signal corresponding to input setting data, and a serial setting circuit for supplying setting data for generating a timing signal to the generating circuit 210. The serial setting circuit 220 serially transfers the setting data to the generation circuit 210 via the three connection lines 222.

Further, the timing signal generator 200 includes a data setting switching circuit 230 for switching timing signal data built in the timing pulse generation circuit 210, and has a function of switching timing signals in accordance with switching control of the switching circuit 230. Have. The data setting switching circuit 230 in the present embodiment changes the potential of the input terminal 232 by a switch for selecting whether or not the input terminal 232 is grounded to the reference potential, and generates a timing signal generated by the generation circuit 210. Switch. The function may be selected by pulling up the input terminal 232 to a predetermined value, for example, a power supply voltage.

Further, the timing signal generator 200 includes:
Further, a bus line setting circuit 240 is provided, and the bus line setting circuit 240 transfers the setting data to the generation circuit 210 via the parallel bus 250. The bus line setting circuit 240
Data setting can be performed faster than data setting by the serial setting circuit 220. For example, a large amount of setting data representing a basic pattern of a timing signal is generated by the generation circuit 210.
Output to In the case of this embodiment, the setting data is such setting data that the timing is not changed during a series of operations of the camera and the like. The output of the bus line setting circuit 240 is connected to the timing signal generation circuit 210 via the bus 250.

Conversely, when performing serial setting, a small amount of setting data is set in a short time. Thus, the timing signal can be changed during the operation of a system such as a camera on which the timing pulse signal generation device 200 is mounted, and the operation according to the changed timing signal can be performed. As described above, in the present embodiment, the timing change during the system operation is performed by the setting data change processing by the serial setting circuit 220, and the bus line setting circuit 240 converts the setting data of the timing pulse signal that does not change the timing during the system operation. It is configured to transfer at high speed. Therefore, when the system such as a camera is started, data setting using the parallel bus is performed, and when the operation mode of the system is changed, data setting using the serial line is performed to perform an operation according to the mode change. A timing signal for performing is obtained. Further, such a parallel setting and a serial setting are performed by a control circuit for controlling a system such as a camera on which the apparatus 200 is mounted.
The control can be performed by the control circuit 260 via control lines 262 and 264, and the control circuit 260 can control the setting timing.

Next, another embodiment will be described with reference to FIG. The camera 300 in the present embodiment includes a solid-state imaging device 310 having an imaging element, a processing circuit 320 for processing an output signal of the solid-state imaging device 310, and various timing signals supplied to the solid-state imaging device 310 and the processing circuit 320. A timing pulse generator 330 includes a timing pulse generator 330 and a setting data output circuit that supplies setting data for generating a timing signal to the generator 332. 334, and the timing pulse generator 330 generates various timing signals under the control of the control circuit 370.

The solid-state imaging device 310 and the processing circuit 320
Each of the solid-state imaging devices 10 in the embodiment shown in FIG.
0 and the same configuration as the processing circuit 106, and has the following characteristic functional configuration. The imaging device 310 in the present embodiment is basically a timing pulse generation circuit.
The image sensor and the correlated double sampling circuit are driven in response to a drive signal such as a timing pulse appearing at the input 350 to which the output of 332 is connected. When the input enable signal (low active) output from the setting data output circuit 334 is supplied to the input 352, the solid-state imaging device 310 activates the input 350 and performs an operation according to the drive signal 350. On the other hand, when the input enable signal 352 is inactive (high level), the signal supplied to the input 350 is invalidated, and the operation of the image pickup device and each circuit is controlled to a frozen state.

On the other hand, the timing pulse generation circuit 332 for generating such a drive signal includes a setting data output circuit 334.
A transfer direction switching signal (DIR) is input to an input 354 to which the solid-state imaging device is connected.
When driving 310, the generated drive signal is output from output 350. When the transfer direction switching signal 354 indicates “input”, the timing pulse generation circuit 332 inputs a signal appearing at the input 350 without generating a drive signal. At this time, the setting data output circuit 334 outputs setting data for generating a timing signal to the output 350, so that the setting data is input to the generation circuit 332. As described above, the timing pulse generation circuit 332 in the present embodiment
Has an input / output switching circuit for changing an output terminal for outputting a drive signal to an input terminal for inputting setting data in accordance with a switching signal 354.

Setting data output circuit for outputting setting data
334 may have the same configuration as the data setting circuits 114 to 118 shown in FIG. 1 and the serial setting circuit 220 shown in FIG. 2, and has the following functional configuration. As shown in FIG. 4, at the timing of driving the solid-state imaging device 310, the setting data output circuit 334 in the present embodiment outputs a transfer direction switching signal instructing "output" to the output 354, and outputs the setting data output circuit. The output 350 of 334 is controlled to a high impedance state (Hi-Z). When supplying the setting data to the generation circuit 332, the setting data output circuit 334 invalidates the input enable signal 352, that is, sets the input enable signal 352 to a high level, and controls the operation of the solid-state imaging device 310 to a frozen state. Next, the setting data output circuit 334 outputs a transfer direction switching signal 354 indicating “input” to the generation circuit 332 to control the information transfer direction of the connection line 350 and output
The high impedance state of 0 is released, and the setting data is output to the output 350. When a plurality of setting data are input to the timing pulse generation circuit 332, various timing pulses are generated based on the setting data.

In this embodiment, the connection line 35 connecting the timing pulse generation circuit 332 and the solid-state imaging device 310 is provided.
0 is used as a drive signal and setting data so that it can be transferred.In addition, the setting data output circuit is connected using a connection line 360 that supplies various timing signals output from the generation circuit 332 to the processing circuit 320. The setting data output from 334 may be supplied to the generation circuit 332. Further, a plurality of such setting data output circuits 334 may be provided.

As described above, in this embodiment, the setting data can be transferred to the timing pulse generation circuit 332 by using the output line from which the timing signal is output, and the data can be set. As a result, the number of connection lines and terminals only for data setting can be reduced.

Next, in the embodiment shown in FIG. 5, the configuration of a camera in which an output bus 502 of an analog-to-digital converter (ADC) 500 for converting an analog signal into a digital value is also used for data setting. It is an example. This camera is
A pixel signal output from the solid-state imaging device 504 is processed by an analog processing circuit 506, and the processed image signal is converted to an ADC 50.
In this configuration, the data is converted into digital image data at 0 and output to the bus 502. Solid-state imaging device 504, analog processing circuit
506 and the ADC 500
8 is driven in response to various supplied timing signals.

The output bus 502 of the ADC 500 is connected to a switch circuit 510. When outputting image data to the digital signal processing circuit 512, the switch circuit 510
The bus 502 and the bus 516 are connected according to the switching signal (DIR) 514 input to the input 514. As a result, ADC 500
The converted image data is input to the digital signal processing circuit 512 via the switch circuit 510.

The digital processing circuit 512 is an image processing circuit for processing image data appearing at the input 516, and outputs the processed image data to the output 518. The digital processing circuit 512 in this embodiment is a timing pulse generator.
And a setting circuit 520 for outputting setting data to be supplied to 508.

The setting circuit 520 has a plurality of setting data for generating various timing pulses, and when setting data in the timing pulse generating circuit 508, outputs a switching signal 514 as shown in FIG. When the switching signal 514 is supplied, the switch circuit 510 disconnects the bus 502 and connects the bus 516 and the bus 522. As a result, the timing pulse generation circuit 508 and the digital signal processing circuit 51
2 is connected, and the setting data stored and held in the setting circuit 520 is supplied to the timing pulse generation circuit 508 via the switch circuit 510.

In this embodiment, as indicated by reference numeral 530, the analog processing circuit 506, the ADC 500, the timing pulse generation circuit 508, and the switch circuit 510 are mounted in, for example, a single chip or a multi-chip Module integrated 530
It is formed as. In this case, the solid-state imaging device 504 may be configured to be included in a package or a module.
Therefore, the integrated device 530 and the digital signal processing circuit
The connection between 512 is via a bus 516, the setting data from the setting circuit 520 can be transferred using this bus 516, and a connection line 514 for transferring a switching signal for switching the data transfer is connected to the integrated device 530. By connecting, a system configuration with less mounting wiring can be obtained. Further, in this embodiment, since the setting data in the parallel format can be supplied to the timing pulse generation circuit 508, a larger amount of setting data can be transferred than in the case of the serial transfer.

A control circuit 540 for controlling each section supplies a control signal 542 for defining the operation of the camera to each section, and outputs setting data from the setting circuit 520 at a timing according to the operation of the camera. .

Note that the setting circuit 520 in this embodiment is
Although the configuration included in the signal processing circuit 512 is not limited thereto, the setting circuit 520 may include other circuits connected to the bus 516,
For example, it may be mounted as one function of the control circuit 540.

In this embodiment, as in the other embodiments, a large amount of data is set immediately after the power of the camera is turned on, and then, when the operation of the camera is switched,
The setting data required for that is stored in the timing pulse generator 50.
Can be set to 8. For example, as shown in FIG. 7, a large amount of setting data 700 is set in the timing pulse generation circuit 508 at high speed. Thereafter, in accordance with the operation state of the camera, for example, when the operation mode is changed by the control circuit 540 and necessary setting data is generated, the desired setting data 702 is generated when the operation is switched. Transfer to 508. Since the data to be set at this time requires a smaller amount of data than when the power is turned on, the data may be set to a low speed by using a serial transfer method in accordance with the situation. Therefore, in each of the above embodiments, it is not necessary to transfer all the setting data to the generation circuit 508 at the beginning of power-on, and the amount of setting data to be transferred at startup can be reduced accordingly. This is especially necessary if you want to shoot immediately after turning on the power, just transfer the setting data to generate the timing signal required for imaging,
Since the start-up time of the camera is shortened, a shooting opportunity can be utilized. Regarding the timing signal required in accordance with the subsequent signal processing or the mode change, the corresponding setting data can be set in the generation circuit 508 later.

Next, an example of a configuration for setting the setting data for generating the timing pulse at a high speed or a low speed will be described with reference to FIG. FIG. 8 shows an imaging unit 800 that images a scene and outputs image data corresponding to the scene image.
And a signal processing circuit 802 for processing the image data. An image of the processing result is displayed on a monitor of an LCD 804, and the image data is compressed and coded on an information recording medium such as a memory card 806 to be recorded. The camera is shown.

The camera according to the present embodiment includes a timing generator (TG) 810 that generates a timing signal for driving the imaging unit 800.
Various timing signals are generated based on setting data transferred at high speed from a control circuit (CPU) 820 via a serial bus 830. The serial bus 830 connects the imaging unit 800, the signal processing circuit 802, the timing generator 810, and the control circuit 820. The circuit supplied with the selection signal from the control circuit 820 inputs the data transferred via the serial bus 830.

The control circuit 820 in this embodiment has a high-speed transfer mode for outputting setting data defining the timing, waveform and repetition pattern of the timing signal generated by the timing generator 810 to the serial bus 830 at high speed. The control circuit 820 supplies a selection signal to the timing generator 810 to which the setting data is transferred and sets the high-speed transfer mode at the time of startup after the power is turned on, and outputs the setting data to the output 830. In this high-speed transfer mode, the control circuit 820 sends a selection signal to the imaging unit 800,
It has a function of outputting setting data representing a voltage value for supplying an analog voltage to analog circuits such as the CCD 840 and the CDS / GCA 846 provided to the output 830.
This setting data is stored in the timing generator 810
May be supplied to the image capturing unit 800. The control circuit 820
Has a low-speed transfer mode in which a control signal for controlling the timing generator 810 and other circuits is output to the serial bus 830 at a low speed when the camera is activated and shifts to a normal operation mode. The control circuit 820 sets operation modes such as a shooting mode and a playback mode of the camera, sets setting data corresponding to the operation mode in the timing generator 810,
Each unit performs an imaging process, a signal process, and a recording / reproducing process according to the set operation mode based on a timing signal generated by the timing generator 810.

The image pickup device (CCD) 840 of the image pickup section 800 has an input 84
The two-dimensional image sensor is driven in response to a control voltage such as a timing pulse and a bias supplied to 2 and 844, and outputs to the CDS / GCA 846 a pixel signal corresponding to an optical image formed on the imaging surface. . CDS / GCA 846
Is the timing pulse input to input 848 and the input 85
In response to the control voltage applied to 0, the output signal of the CCD 840 is correlated double-sampled, and the sampled pixel signal is variably amplified. The output of the CDS / GCA 846 is connected to the ADC 852, and the pixel signal input to the ADC 852 is converted to digital value image data by the ADC 852. The ADC 852 outputs the converted digital image data to an output 854 to which the signal processing circuit 802 is connected.

The digital-to-analog conversion circuit (DAC) 856 is
This is a conversion circuit that inputs setting data transferred via the serial bus 830 and generates an analog voltage corresponding to the data at its output. The DAC 856 is a conversion circuit that inputs setting data input via the serial bus 830 and generates an analog voltage corresponding to the data at its output. DA
The first output of C 856 is connected to amplifier 858 and amplifier 85
8 amplifies the applied voltage at a predetermined amplification factor. The output 844 of the amplifier 858 is connected to the CCD 840,
OFD voltage (overflow drain voltage) and PG to 40
Various control voltages such as voltage (precharge drain bias voltage) are applied. The output 850 of DAC 856 is CD
The DAC 856 is connected to the S-GCA 846, and applies a control voltage corresponding to the setting data to the CDS-GCA 846.

The signal processing circuit 802 includes a control signal from the control circuit 820 input to the input 860 and the serial bus 830.
In response to a timing signal input via
4 is a digital signal processing circuit for processing the input image data into image data of a predetermined format. The signal processing circuit 802 has a function of inputting a timing signal and a control signal appearing on the serial bus 830 when a selection signal is supplied from the control circuit 820, in addition to the functional configuration of the signal processing circuit 512 shown in FIG. . The signal processing circuit 802 includes a control unit 820
The control signal generated in step (1) is input to the input 860, and in the operation mode corresponding to the control signal, the image data is arithmetically processed using the memory 870 to create display data and recording data. The display data processed by the signal processing circuit 802 is output to a liquid crystal display (LCD) 804 connected to its output 864.
And an image corresponding to the display data is displayed on the panel. The recording data processed by the signal processing circuit 802 is stored in a memory card connected to its output 866.
The data is output to 806 and is written in the predetermined recording area.

The timing generator 810 includes a control circuit
820 and a timing signal generation circuit that generates a timing signal corresponding to the setting data given from the signal processing circuit 802, and outputs the generated timing signal to the output 842 and
Output to 848. The timing generator 810
Generates a timing signal such as a pixel clock required by the signal processing circuit 802, and supplies the generated timing signal to the signal processing circuit 802 via the serial bus 830. The timing generator 810 in this embodiment is
When the camera is started, the setting data is transferred in a high-speed transfer mode, the setting data is stored, and a timing signal having a timing and a waveform corresponding to the input data is generated. Further, the timing generator 810 stores the setting data transferred and supplied in the low-speed transfer mode when the operation mode of the camera specified by the control circuit 820 is switched, and outputs a timing signal corresponding to the changed operation mode. Generated based on newly input setting data. As described above, information is transferred on the serial bus 830 in at least two types of modes, the high-speed transfer mode and the low-speed transfer mode. Note that the information transfer speed in the low-speed transfer mode is preferably adjusted to the transfer speed of the circuit whose information receiving capability of the transfer destination circuit is the slowest as compared with the other circuits.

FIG. 9 shows an example of the internal configuration of the timing generator 810. The generator 810 includes a serial interface circuit 900 for connecting a serial bus 830, and a selection signal for selecting the generator 810 is supplied from a control circuit 820. And setting data appearing on the serial bus 830, and store information corresponding to the setting data in the memory 902.
And to the register 904.

The memory 902 stores a waveform for generating a timing signal of the contents of the setting data and timing information indicating the timing, and the register 904 stores, for example, information indicating a repetition pattern of the timing signal.
These pieces of information are supplied to a pulse generation circuit 906. The pulse generation circuit 906 counts the supplied timing information and repetition pattern by a counter, and generates a signal pulse corresponding to the count timing. The timing generator 810 outputs the timing signal thus generated to the imaging unit.
800 and the signal processing circuit 802. Also memory
902 stores analog voltage values used in the imaging unit 800, and data representing these voltage values is transmitted from the serial interface circuit 900 via the serial bus 830 to the imaging unit 80.
Given to 0. As a result, in the imaging section 800, the control voltage value is set, and the drive voltage is applied to the analog driven CCD 840 and CDS / GCA 846.

The mechanism for generating such a timing pulse may employ, for example, the configuration described in the specification of Japanese Patent Application No. 11-83514 filed by the present applicant. More specifically, for example, a horizontal counter that is reset in synchronization with a horizontal synchronization signal and counts a reference clock, and pattern data used to generate each timing pulse, are provided at the beginning of one horizontal scanning period. A storage circuit that stores data indicating a timing pulse for one cycle to be generated and pattern data indicating the number of repetitions of the timing pulse in one horizontal scanning period, and stores pattern data corresponding to a required timing pulse from the storage circuit. A configuration may be provided that includes a setting circuit that reads and sets this pattern data in a horizontal register, and a timing pulse generation circuit that generates and outputs a timing pulse based on the count value of the horizontal counter and the pattern data set in the horizontal register. .

As described above, in each of the above embodiments,
In a system such as a camera on which a timing pulse is mounted, setting data, which is original data for generating a timing signal, can be set at high speed at a specific small number of timings such as when the power is turned on. The setting time is shortened, and a large amount of data can be set. At this time, the setting data may be information indicating a timing signal that does not change the timing of the system. Further, when it is necessary to change the timing of the system, the setting data can be further transferred to the timing pulse generation circuit and set when the operation mode of the system is switched according to the control from the control circuit. In this case, a smaller amount of setting data is required than when the system is started. Further, when the bus for transferring the setting data is shared with, for example, the bus for transferring the image data, the size of the system in which the timing pulse generation circuit is mounted can be reduced.

The setting data set in the timing pulse generation circuit and the timing generator as described above is as follows.
Since it can be set as desired according to its function and necessity, the minimum setting data can be set at the time of starting the system, so that the starting time is shortened and the complicated timing is reduced. The timing signal to be represented can be set. The setting data is not limited to the operation mode switching of a system such as a camera, and can be set during a blanking period when a moving image signal of a continuous frame is processed by a signal processing circuit. In addition, the timing signal generation circuit can set the exposure time in the image sensor, the timing of performing ineffective pixel processing, and the like. Further, such setting timing can be defined by a control circuit that controls the system.

When a first bus for transferring the setting data at a high speed and a second bus for transferring the setting data at a low speed are provided, the setting data is transferred at a high speed in accordance with the set contents. , Other setting data can be transferred to another circuit at low speed. Therefore, when the power is turned on, the setting data can be set at a high speed, and other circuits can be controlled using the second bus.

[0051]

As described above, according to the present invention, by setting a plurality of setting data for setting data for generating a timing signal and setting the data, it is possible to shorten the data setting time particularly at the time of starting the system. At this time, by selecting a setting data transfer path, high-speed data setting can be performed, and the startup time can be further reduced. In addition, since any one of the plurality of setting units can perform data setting at a predetermined timing defined by the control unit, there is no need to set such setting data at the time of startup, and the system The data setting can be performed at an arbitrary timing in accordance with the above operation.

Therefore, the setting data can be set at a high speed at the time of startup and the setting data can be set at a low speed during the operation of the system by using a plurality of setting means. In addition, the setting data corresponding to various operation patterns of the system can be appropriately set in a time-dispersed manner.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment conceptually showing a configuration example of a timing signal generator to which the present invention is applied.

FIG. 2 is a block diagram showing another configuration example of the timing signal generator.

FIG. 3 is a block diagram showing another configuration example of the timing signal generator.

FIG. 4 is a timing chart showing an operation in the embodiment shown in FIG.

FIG. 5 is a block diagram showing another configuration example of the timing signal generator.

6 is a timing chart showing an operation in the embodiment shown in FIG.

FIG. 7 is a timing chart showing an example of data setting timing in the embodiment shown in FIG.

FIG. 8 is a block diagram illustrating a configuration example of a digital camera including a timing signal generation device.

FIG. 9 is a block diagram showing a configuration example of a timing generator in the embodiment shown in FIG. 8;

[Explanation of symbols]

 100 solid-state imaging device 106 processing circuit 110 timing pulse generator 112 timing pulse generator 114 data setting circuit A 116 data setting circuit B 118 data setting circuit C

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Claims (19)

[Claims] 1. A timing signal generating device for generating a timing signal according to setting information, wherein the device outputs first and second setting information for generating the timing signal, respectively. Setting means, first setting information output from the first setting means is input, generating means for generating a first timing signal according to the first setting information, and output from the second setting means And control means for defining timing for setting the second setting information to be generated in the generating means, wherein the generating means receives the second setting information transferred at the timing specified by the control means. And generating a second timing signal according to the second setting information. 2. The apparatus according to claim 1, wherein the first setting unit sets the first setting information in the generation unit when a system in which the device is mounted is started. Timing signal generator. 3. The apparatus according to claim 1, wherein said apparatus transfers a first setting information to said generating means at a high speed.
And a second transfer unit that transfers the second setting information to the generation unit at a lower speed than the first transfer unit, wherein the first setting unit includes the first setting unit. Information on the first
The second setting means outputs the second setting information to the second setting information via the second setting information.
Output to the generation means via the transfer means, wherein the generation means generates a timing signal corresponding to the first or second setting information transferred via the first and second transfer means. A timing signal generator characterized by the above-mentioned. 4. The apparatus according to claim 3, wherein said first transfer unit is a parallel bus connected to said generation unit, and said first setting unit is connected to said first bus by said first bus. A timing signal generator for outputting setting information. 5. The timing signal generating device according to claim 4, wherein said first transfer means is connected to an output bus of a conversion means for converting an analog signal into a digital value. 6. The apparatus according to claim 3, wherein said second transfer means is a serial bus, and said second setting means outputs said second setting information to said serial bus. A timing signal generator characterized by the above-mentioned. 7. The apparatus according to claim 1, wherein the first setting means outputs first setting information representing a first timing signal which does not change the operation of a system in which the apparatus is mounted. A timing signal generator. 8. The apparatus according to claim 1, wherein said second setting means outputs second setting information indicating a second timing signal for changing the operation of a system in which the apparatus is mounted. A timing signal generator. 9. A timing signal generating device for generating a timing signal according to setting information, the device comprising: setting means for outputting first and second setting information for generating the timing signal; Generating means for generating and outputting a timing signal for driving an imaging means for generating a pixel signal according to the following; control means for defining timing for setting the second setting information in the generating means; Transfer means for transferring the second setting information to the generating means, the transfer means transferring the timing signal to the imaging means, the setting means controls an information transfer direction in the transfer means, The generation means generates a first timing signal according to first setting information output from the setting means, and generates a first timing signal defined by the control means. Generates a second timing signal corresponding to the second setting information transferred in the step (a), and supplies the generated first and second timing signals to the imaging unit connected via the transfer unit. A timing signal generator characterized by the above-mentioned. 10. The apparatus according to claim 9, wherein the setting unit sets the output of the setting unit to high when the generation unit supplies the first and second timing signals to the imaging unit. A timing signal generator, wherein the timing signal is controlled to an impedance state. 11. The apparatus according to claim 9, wherein the setting means outputs a switching signal for switching an output of the generating means to an input when outputting the first and second setting information. A timing signal generator. 12. The timing signal generating apparatus according to claim 11, wherein said setting means controls said imaging means to be in a freeze state when outputting said first and second setting information. apparatus. 13. The timing signal generating apparatus according to claim 9, wherein said setting means sets said first setting information in said generating means at the time of starting up a system in which said apparatus is mounted. apparatus. 14. The apparatus according to claim 9, wherein said setting means outputs first setting information representing a first timing signal which does not change the operation of a system in which the apparatus is mounted. A timing signal generator characterized by the above-mentioned. 15. The apparatus according to claim 9, wherein the setting means outputs second setting information indicating a second timing signal for changing the operation of a system in which the apparatus is mounted. A timing signal generator characterized by the above-mentioned. 16. A timing signal generating method for generating a timing signal according to setting information, comprising: a first setting step of outputting first setting information for generating the timing signal; A second setting step of outputting second setting information for generating a signal; and a first setting information corresponding to the first setting information in response to the first setting information output in the first setting step. Generating a timing signal according to the second setting information, and generating a timing signal according to the second setting information in response to the second setting information output in the second setting step; An output step of outputting a timing signal, wherein the first setting step outputs the first setting information when starting up a system using the timing signal. 17. The method according to claim 16, wherein the first setting step outputs first setting information representing a first timing signal that does not change the operation of the system halfway. Timing signal generation method. 18. The method according to claim 16, wherein the second setting step outputs second setting information representing a second timing signal for changing the operation of the system halfway. Timing signal generation method. 19. The method according to claim 16, wherein the first setting step outputs the first setting information at a high speed, and the second setting step outputs the second setting information. A timing signal generating method, comprising outputting at a lower speed than the first setting information.