JPH09219731A - Digital modulating signal detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable the oscillation frequency of an oscillator to be automatically fixed to a prescribed frequency so as to obtain an oscillating signal with non- adjustment and high certainty by means of an inexpensive LC resonance circuit by providing a PLL circuit. SOLUTION: A digital modulating signal detection circuit is provided with the PLL circuit 39 which compares phases of the oscillation frequency of the oscillator 16 an the reference frequency of the reference oscillator 28 at the phase comparator 27 and executes feedback as against the oscillator 16 so as to permit the phase difference to be zero and a frequency dividing data setting circuit 40 which sets frequency dividing data for deciding the frequency division ratio of a programmable divider 25 in the PLL circuit 39. The frequency dividing data setting circuit 40 and an A/D converter 41 for setting the frequency dividing data are made to be an ingegrated circuit by one chip together with the PLL circuit 39.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital modulation signal detection circuit, which is particularly used in a receiver such as a digital satellite broadcast and has a QPSK (Quadrature Phase Shift Keying).
Digital modulation signals such as I (In phase) signal and Q (Quadr
(ature phase) signal and a detection circuit for separating the signal.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a basic configuration of a digital satellite broadcast receiver. In FIG. 6, the radio waves sent from the satellites are collected by the antenna 61, and LNB (Low N
After being converted to a first intermediate frequency (1 to 2 GHz band) by an oise block 62, it is introduced into the tuner block 63. In the tuner block 63, the first intermediate frequency is amplified by the variable gain amplifier (AGC) 631, and the mixer 632.
Is input to The mixer 632 is further provided with a local oscillation signal corresponding to the desired reception channel from the oscillator 633.

The oscillator 633 is a PLL (Phase Locked Lo
op) Circuit 634 controls the frequency of the local oscillator signal. The PLL circuit 634 has a crystal oscillator 64.
The tuner block 63 uses the oscillation frequency of
The frequency division ratio can be controlled by a microcomputer or the like (not shown) external to the. The mixer 632 outputs the frequency difference between the first intermediate frequency and the local oscillation signal as the second intermediate frequency (for example, 480 MHz). This second intermediate frequency is amplified by the amplifier 635 and then SAW (Surfa
ce acoustic wave; selected by the filter 65 and introduced into the IQ detection block 66.

In the IQ detection block 66, the second intermediate frequency is amplitude-controlled by the variable gain amplifier 661 and then input to the first and second mixers 662 and 663. on the other hand,
The oscillator 664 generates a signal of 480 MHz which is the same as the second intermediate frequency. The 480 MHz signal is directly input to the second mixer 663, and the phase thereof is delayed by 90 ° by the phase shifter 665, and then input to the first mixer 662. As a result, the I signal is separated by the second mixer 663, and the Q signal is separated by the first mixer 662, and output. The I signal and the Q signal are amplified by the baseband amplifiers 666 and 667 and output. Then I
The signals and the Q signals are A / D converters 67a and 67b.
After being converted into a digital signal by, the signal is demodulated by the QPSK demodulator 68 and further error-corrected by the error correction circuit 69 to be a video signal output.

Consider the IQ detection block 66 in the digital satellite broadcast receiver configured as described above. Regarding the oscillator 664, it is necessary to oscillate at the same frequency as the second intermediate frequency, and it is desirable that no adjustment is made from the viewpoint of cost reduction. In order to enable this adjustment-free, conventionally, SA
The oscillation frequency of the oscillator 664 is determined using the W oscillator 668.

[0006]

As described above, when the SAW oscillator 668 is used, since the oscillation frequency of the oscillator 664 is determined by the resonance frequency of the SAW oscillator 668, no adjustment is required. , SAW oscillator 668
Is generally costly and IQ due to the CAN package
There is a problem that the detection block 66 becomes large.

The present invention has been made in view of the above problems, and an object of the present invention is to make adjustment-free and inexpensive L
An object of the present invention is to provide a digital modulation signal detection circuit which is realized by a C resonance circuit and which enables simplification and downsizing of the circuit configuration.

[0008]

A digital modulation signal detection circuit according to the present invention includes an oscillator that oscillates a signal for phase detection, and first and second oscillators that have a phase difference of 90 ° between oscillation signals of the oscillator. A phase control circuit that outputs a signal, a first mixer that mixes a predetermined digital modulation signal and a first output signal of the phase control circuit and outputs a first signal, and the digital modulation signal and the phase control circuit The second mixer that mixes the second output signal of 1 to output the second signal, and the PLL circuit that fixes the oscillation frequency of the oscillator to a predetermined reference frequency are configured.

In the digital modulation signal detection circuit having the above configuration, a predetermined digital modulation signal is input to each of the first and second mixers, while the oscillation signal of the oscillator has a phase difference of 90 ° with each other in the phase control circuit. The first and second output signals are input, and the first output signal is input to the first mixer and the second output signal is input to the second mixer. P
The LL circuit fixes the oscillation frequency of the oscillator to a predetermined frequency by feeding back so that the phase error between the frequency obtained by dividing the oscillation frequency of the oscillator and the reference frequency becomes zero. The first mixer outputs the first signal by mixing the digital modulation signal and the first output signal of the phase control circuit, and the second mixer outputs the digital modulation signal and the second output signal of the phase control circuit. To output the second signal.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention when applied to, for example, a digital satellite broadcast receiver will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. In FIG. 1, a tuner block (not shown) of a digital satellite broadcast receiver is, for example, 480 MHz.
The IF signal converted to the second intermediate frequency (IF) in the z band is
It becomes the IF input of the integrated circuit 11 shown by the broken line in the figure of this detection circuit. The second intermediate frequency is a QPSK-modulated signal, which is input into the integrated circuit 11 via the terminal pin 12,
After the amplitude is controlled by the variable gain amplifier 13, it becomes an input to each of the first mixer 14 and the second mixer 15. These mixers 14 and 15 include oscillators 16 to 480M.
The first and second oscillation signals of Hz have a phase difference of 90 ° with each other.
After being phase controlled to the second signal, it is provided as the other input of each.

That is, the oscillation signal of the oscillator 16 is 90
The phase is shifted by 90 ° by the phase shifter 17 and becomes the other input of the first mixer 14, and directly becomes the other input of the second mixer 15. As a result, the first and second
In the mixers 14 and 15, the phase detection is performed by the signals having the phase difference of 90 °. As a result, QPSK
The modulated second intermediate frequency is separated into an I signal and a Q signal. The I signal and the Q signal are amplified by the baseband amplifiers 18 and 19, respectively, and then the terminal pin 2
It is output as an IQ baseband signal to the outside of the integrated circuit 11 via 0 and 21.

On the other hand, the oscillator 16 oscillates at the resonance frequency of the LC resonance circuit 23 externally attached to the terminal pin 22. The LC resonance circuit 23 includes an inductance L connected between the terminal pin 22 and the ground, and a series connection circuit of a capacitor C and a varactor diode (variable capacitance diode) VC connected in parallel to the inductance L. The capacitance value of the varactor diode VC changes according to the voltage value of the control voltage applied to the common connection point (A) of the capacitor C and the varactor diode VC, and the resonance frequency changes accordingly.

The oscillation signal of the oscillator 16 is passed through a buffer amplifier 24 and a programmable divider (dividing circuit) 25.
Is also supplied. The frequency division ratio M of the programmable divider 25 is set, for example, by frequency division data given via a terminal pin 26 from a microcomputer (not shown) that controls the entire receiver. Programmable divider 25
Divides the oscillation signal of 480 MHz supplied from the oscillator 16 into 1 / M, and uses it as one input of the phase comparator 27 of the next stage.

On the other hand, the reference oscillator 28 oscillates at the resonance frequency of the crystal oscillator 30 externally attached to the terminal pin 29. This oscillating signal is divided into 1 / N by the reference divider 31 with a fixed dividing ratio N, and then the phase comparator 2
The other input of 7 serves as a reference signal for phase comparison.
The oscillation signal of the reference oscillator 28 further passes through the buffer amplifier 32 and then through the terminal pin 33.
1 is output as a reference frequency.

The phase comparator 27 compares the phases of the frequency-divided signals of the programmable divider 25 and the reference divider 31 and outputs a phase error signal corresponding to the phase error of both. This phase error signal passes through the charge pump circuit 34 and then is externally attached to the terminal pin 35.
It is integrated by a PF (low-pass filter) 36 and becomes a DC voltage. This DC voltage is applied to the varactor diode driver 3
Amplified in the range from ground voltage to power supply voltage at 7 and terminal pin 3
8 and is applied as a control voltage to the point (A) of the LC resonance circuit 23 via the resistor R0.

As described above, the LC resonance circuit 23 is responsive to the voltage value of the control voltage applied to the point (A).
Of the oscillator 16 changes, and the oscillation frequency of the oscillator 16 changes accordingly. That is, the feedback loop is configured so that the phase error in the phase comparator 27 becomes zero. The above-described configuration is the PLL circuit 39 for fixing the oscillation frequency of the oscillator 16 to a predetermined reference frequency.
4, 15, the oscillator 16, the phase shifter 17, and the like are integrated into a single chip.

In the PLL circuit 39 having the above structure, the reference frequency output from the reference divider 31 is fref, the oscillation frequency of the crystal oscillator 30 is f (x'tal),
When the frequency division ratio of the programmable divider 25 is M and the frequency division ratio of the reference divider 31 is N, the oscillation frequency fosc of the oscillator 16 is

## EQU00001 ## fosc = fref.times.M = (f (x'tal) / N) .times.M.

Here, in order to change the oscillation frequency fosc of the oscillator 16, the frequency division ratio M of the programmable divider 25 may be changed. In the present embodiment, this division ratio M
The frequency division data for determining is given from an external microcomputer. That is, the frequency division data is given to the programmable divider 25 from an external microcomputer so that the frequency division ratio M at which the oscillation frequency fosc of the oscillator 16 becomes a predetermined frequency (480 MHz in this example) is set. By the action of, the oscillation frequency fosc of the oscillator 16 is fixed to a predetermined frequency.

As described above, by providing the PLL circuit 39 for feeding back to the oscillator 16 so that the phase error between the frequency obtained by dividing the oscillation frequency fosc of the oscillator 16 and the reference frequency fref becomes zero, Oscillator 16
Oscillation frequency fosc is automatically the reference frequency fre
Since it is fixed at M times f, it is possible to obtain an unadjusted and highly accurate oscillation signal by the inexpensive LC resonance circuit 23 without using an expensive SAW resonator.

FIG. 2 is a block diagram showing a second embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 2, a tuner block of a digital satellite broadcasting receiver, for example, a second block of 480 MHz band
The IF signal converted to the intermediate frequency is the IF signal of the integrated circuit 11.
Input. The second intermediate frequency is a QPSK-modulated signal, is input into the integrated circuit 11 via the terminal pin 12, is amplitude-controlled by the variable gain amplifier 13, and then is supplied to the first mixer 14 and the second mixer 15. One of the inputs. These mixers 14, 15 have oscillators 16 through 4
An 80 MHz oscillating signal is provided as the other input of each.

That is, the oscillation signal of the oscillator 16 is 90
The phase is shifted by 90 ° by the phase shifter 17 and becomes the other input of the first mixer 14, and directly becomes the other input of the second mixer 15. As a result, the first and second
In the mixers 14 and 15, the phase detection is performed by the signals having the phase difference of 90 °. As a result, QPSK
The modulated second intermediate frequency is separated into an I signal and a Q signal. The I signal and the Q signal are amplified by the baseband amplifiers 18 and 19, respectively, and then the terminal pin 2
It is output as an IQ baseband signal to the outside of the integrated circuit 11 via 0 and 21.

On the other hand, the oscillator 16 oscillates at the resonance frequency of the LC resonance circuit 23 externally attached to the terminal pin 22. As in the case of the first embodiment, the LC resonance circuit 23 includes an inductance L connected between the terminal pin 22 and the ground, a capacitor C and a varactor diode VC connected in parallel to the inductance L. And a varactor diode VC corresponding to the voltage value of the control voltage applied to the common connection point (A) of the capacitor C and the varactor diode VC.
Changes the capacitance value and changes the resonance frequency accordingly.

The oscillation signal of the oscillator 16 is also supplied to the programmable divider 25 via the buffer amplifier 24. The frequency division ratio M of the programmable divider 25 is set by the frequency division data supplied from the frequency division data setting circuit 40. The frequency division data setting circuit 40 sets the frequency division data based on the digital data output from the A / D converter 41. The divided voltage by the resistors R1 and R2 connected between the terminal pin 26 and the power supply Vcc and the ground is applied to the A / D converter 41 through the terminal pin 26.

On the other hand, the reference oscillator 28 oscillates at the resonance frequency of the crystal oscillator 30 externally attached to the terminal pin 29. This oscillating signal is divided into 1 / N by the reference divider 31 with a fixed dividing ratio N, and then the phase comparator 2
It becomes the other input of 7. The oscillation signal of the reference oscillator 28 is further output to the outside of the integrated circuit 11 as a reference frequency via the terminal pin 33 after passing through the buffer amplifier 32.

The phase comparator 27 compares the phases of the divided signals of the programmable divider 25 and the reference divider 31 and outputs a phase error signal corresponding to the phase error of both. This phase error signal passes through the charge pump circuit 34 and then is externally attached to the terminal pin 35.
It is integrated by the PF 36 and becomes a DC voltage. This DC voltage is amplified by the varactor diode driver 37 in the range from the ground voltage to the power supply voltage, and is applied as a control voltage to the point (A) of the LC resonance circuit 23 via the terminal pin 38.

Depending on the voltage value of this control voltage, L
The resonance frequency of the C resonance circuit 23 changes, and the oscillation frequency of the oscillator 16 changes accordingly. That is, the feedback loop is configured so that the phase error in the phase comparator 27 becomes zero. The above configuration is the PLL circuit 39 for making the oscillation frequency of the oscillator 16 unadjusted. This PLL
The circuit 39, the divided data setting circuit 40, and the A / D converter 41 are integrated into a single chip together with the mixers 14 and 15, the oscillator 16, the phase shifter 17, and the like.

In the PLL circuit 39 having the above configuration, the first
The oscillation frequency f of the oscillator 16 is the same as in the above embodiment.
To change osc, the frequency division ratio M of the programmable divider 25 may be changed. In the present embodiment, the frequency division data setting circuit 40 for setting the frequency division data for determining the frequency division ratio M is built in the integrated circuit 11, and this frequency division data is
The output data of the / D converter 41 is rewritten.

Specifically, the reference frequency fref of the reference divider 31 is set to 50 kHz, and the oscillator 16
Taking the case where the oscillation frequency fosc of each is selected to 480 MHz as an example, to obtain fosc = 480 MHz, M
= 9600, and when expressed in binary, it becomes 14-bit binary data. The A / D converter 41 is a 3-bit converter, and is responsible for the lower 3 bits of the M binary data, as shown in FIG.

As a result, the lower bits of the divided data are changed according to the input voltage of the A / D converter 41, and the oscillation frequency fosc of the oscillator 16 can be finely adjusted in 50 kHz steps. For example, when the pass frequency band of the SAW filter 65 in FIG. 6 is deviated from 480 MHz due to manufacturing variations or the like, it is possible to shift the second intermediate frequency from 480 MHz in accordance with the SAW filter 65. At this time, the oscillation frequency fosc of the oscillator 16 can also be finely adjusted according to the second intermediate frequency by the input voltage of the A / D converter 41.

That is, the oscillation frequency f of the oscillator 16 is controlled by the A / D converter 41 and the external resistors R1 and R2.
A fine adjustment circuit for fine adjustment of osc is configured. In addition,
It is also possible to finely adjust the oscillation frequency fosc of the oscillator 16 by using a variable resistor for at least one of the external resistors R1 and R2 and controlling the input voltage of the A / D converter 41 by changing the resistance value. is there.

As described above, by providing the PLL circuit 39 for feeding back to the oscillator 16 so that the phase error between the frequency obtained by dividing the oscillation frequency fosc of the oscillator 16 and the reference frequency fref becomes zero, As in the case of the first embodiment, the oscillation frequency fosc of the oscillator 16 is automatically fixed to M times the reference frequency fref, so that an inexpensive LC resonator can be used without using an expensive SAW resonator.
The resonance circuit 23 can obtain an oscillation signal with no adjustment and high accuracy.

By the way, in the case of the first embodiment, P
Frequency division data for determining the frequency division ratio of the programmable divider 25 of the LL circuit 39 is given from an external microcomputer. In this case, the tuner package itself needs a signal port for fetching frequency-divided data from the microcomputer, and the configuration becomes complicated accordingly.

On the other hand, in this embodiment, PL
A frequency division data setting circuit 40 for setting frequency division data that determines the frequency division ratio of the programmable divider 25 of the L circuit 39 is provided, and the frequency division data setting circuit 40 and the A / D converter 41 are integrated with the PLL circuit 39. So P
Since the frequency division data for determining the frequency division ratio of the LL circuit 39 can be set internally without being given from an external microcomputer or the like, an interface with the microcomputer is not required, so that the system can be simplified.

In the first and second embodiments, the phase control circuit 90 outputs the first and second signals having a phase difference of 90 ° based on the oscillation signal of the oscillator 16.
The phase shifter 17 is used to supply the output signal of the 90 ° phase shifter 17 to the first mixer 14 as the first output signal of the phase control circuit, and the oscillation signal of the oscillator 16 is directly subjected to the phase shift control. The second mixer 15 is used as the second output signal of the circuit.
However, the present invention is not limited to this. For example, by using a + 45 ° phase shifter and a −45 ° phase shifter, the output signal of the + 45 ° phase shifter is supplied to the first mixer 14 as a first output signal, and the output of the −45 ° phase shifter is output. It is also possible to configure so that the signal is supplied to the second mixer 15 as the second output signal, that is, the two output signals supplied to the first and second mixers 14 and 15 are 90% apart from each other.
Any structure may be used as long as it has a phase difference of °.

FIG. 4 is a block diagram showing an example of a digital satellite broadcast receiver using the digital modulation signal detection circuit of the first or second embodiment described above as an IQ detection block. The same parts as those in FIG. 2 are designated by the same reference numerals. However, the peripheral circuits of the PLL circuit 39 are shown in a simplified manner, and particularly the programmable divider 25, the phase comparator 27, the reference divider 31, the charge pump circuit 34, the varactor diode driver 37, etc. are collectively shown as the PLL circuit 39. There is.

In FIG. 4, the radio waves sent from the satellite are collected by the antenna 42, and the first intermediate frequency (1
To the 2 GHz band), and then the tuner block 44
Is introduced through the terminal pin 45. In this tuner block 44, the first intermediate frequency is the variable gain amplifier 44.
The signal is amplified by 1 and input to the mixer 442. Mixer 44
Further, a local oscillation signal corresponding to the desired reception channel is added to 2 from the oscillator 443.

The frequency of the local oscillation signal of the oscillator 443 is controlled by the PLL circuit 444. The PLL circuit 444 includes a crystal oscillator 47 externally attached to the terminal pin 46.
The oscillation frequency is used as a reference frequency, and its frequency division ratio can be controlled by an external microcomputer or the like (not shown). The mixer 442 calculates the frequency difference between the first intermediate frequency and the local oscillation signal as the second intermediate frequency (for example, 480 MH).
z). This second intermediate frequency is applied to the amplifier 44
After being amplified by 5, the signal is supplied to the SAW filter 49 via the terminal pin 48. And this SAW filter 49
And is introduced into the IQ detection block 50 according to the present invention.

The structure and operation of the IQ detection block 50 are as described in the first and second embodiments. That is, the Q signal is separated and output by the first mixer 14, and the I signal is separated and output by the second mixer 15. The I signal and the Q signal are amplified by the baseband amplifiers 18 and 19, respectively, and then output to the outside of the IQ detection block 50. And after being digitized, Q
PSK demodulation is performed and error correction is further performed to produce a video signal output.

As described above, in the digital satellite broadcast receiver to which the present invention is applied, the frequency division data for setting the frequency division ratio of the PLL circuit 39 is a data value given from the microcomputer in the case of the first embodiment. By changing the input voltage of the A / D converter 41 by changing the resistance values of the external resistors R1 and R2 in the case of the second embodiment, the oscillator 16 of the oscillator 16 is adjusted according to the manufacturing variation of the SAW filter 49. The oscillation frequency can be finely adjusted.

As shown in the third embodiment of FIG. 5, the reference frequency output from the IQ detection block 50 via the terminal pin 33 is applied to the terminal pin 46 of the tuner block 44. , The reference frequency of the PLL circuit 39 of the IQ detection block 50 can be used as the reference frequency of the PLL circuit 444 of the tuner block 44. As a result, P of the tuner block 44
Since the crystal oscillator 47 (see FIG. 4) used to generate the reference frequency of the LL circuit 444 can be eliminated, the cost of the system can be reduced accordingly.

Conversely, by inputting the reference frequency of the PLL circuit 444 of the tuner block 44 to the terminal pin 29 of the IQ detection block 50, it can be used as the reference frequency of the PLL circuit 39 of the IQ detection block 50. is there. In this case, the PLL of the IQ detection block 50
Since the crystal oscillator 30 used to generate the reference frequency of the circuit 39 can be eliminated, the cost of the system can be reduced accordingly.

It should be noted that not only the reference frequency of the PLL circuit 444 of the tuner block 44, but also other reference frequencies are I
It can also be used as the reference frequency of the PLL circuit 39 of the Q detection block 50. For example, the reference frequency may be given from the microcomputer that controls the QPSK demodulation circuit, and in this case also, as in the previous case, it is used to generate the reference frequency of the PLL circuit 39 of the IQ detection block 50. The crystal oscillator 30 can be eliminated.

[0044]

As described above, according to the present invention,
For an oscillator that generates a signal for phase detection, a PLL circuit that feeds back the oscillator so that the phase error between the divided frequency of the oscillation frequency and the reference frequency becomes zero is provided. Since the oscillation frequency is automatically fixed at a predetermined frequency, an inexpensive LC resonance circuit can be used to obtain an oscillation signal with no adjustment and high accuracy without using an expensive SAW resonator.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the present invention.

FIG. 3 is a diagram showing a relationship between frequency-divided data and output data of an A / D converter.

FIG. 4 is a block diagram showing an example of a configuration of a digital satellite broadcast receiver to which the present invention is applied.

FIG. 5 is a block diagram showing a third embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

14 First Mixer 15 Second Mixer 16
Oscillator 17 Phase shifter 23 LC resonant circuit 25 Programmable divider 27 Phase comparator 28 Reference oscillator 3
0 crystal oscillator 31 reference divider 39 PLL circuit 40 frequency division data setting circuit 41 A / D converter

Claims (7)

[Claims] 1. A digital modulation signal detection circuit for detecting a predetermined digital modulation signal, comprising: an oscillator for oscillating a signal for phase detection; and first and second oscillators having oscillation signals of the oscillator of 90 °. A phase control circuit that outputs the signal as a signal, a first mixer that mixes the digital modulation signal with a first output signal of the phase control circuit and outputs a first signal, the digital modulation signal and the phase A second mixer that mixes the second output signal of the control circuit and outputs the second signal; and a PLL circuit that fixes the oscillation frequency of the oscillator to a predetermined reference frequency. Digital modulation signal detection circuit. 2. The phase control circuit includes a phase shifter that shifts an oscillation signal of the oscillator by 90 °, supplies an output signal of the phase shifter to the first mixer, and oscillates the oscillator. 2. The digital modulation signal detection circuit according to claim 1, wherein a signal is directly supplied to the second mixer. 3. The PLL circuit includes a frequency dividing circuit that divides the oscillation frequency of the oscillator and has a variable frequency dividing ratio, and sets frequency dividing data that determines the frequency dividing ratio of the frequency dividing circuit. The digital modulated signal detection circuit according to claim 1, further comprising a frequency division data setting circuit. 4. The PLL circuit and the frequency division data setting circuit are integrated on one chip together with the oscillator, the phase shifter, and the first and second mixers. 3. The digital modulation signal detection circuit described in 3. 5. The digital modulation signal detection according to claim 3, further comprising a fine adjustment circuit that finely adjusts the oscillation frequency of the oscillator by changing the divided data set by the divided data setting circuit. circuit. 6. In a digital satellite broadcast receiver, a reference frequency of the PLL circuit is set to a PLL of a tuner block.
The digital modulation signal detection circuit according to claim 1, which is used as a reference frequency of the circuit. 7. The digital modulated signal detection circuit according to claim 1, wherein in the digital satellite broadcast receiver, the reference frequency of the external circuit is used as the reference frequency of the PLL circuit.