JPH09219466A - Electronic component base - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electronic component base which enables providing a capacitor onto the upper surface of insulating layers having two or more circuit patterns laterally arrayed at predetermined intervals, or along the lateral direction between the insulating layers, without occupying a large area. SOLUTION: A via-hole 8 filled with a conductor 23 is provided in an insulating layer portion directly below each of circuit patterns 14 which are laterally arrayed at predetermined intervals. Also, a via-hole 8 filled with a ferroelectric material 22 is provided in an insulating layer portion which is located between the via-holes 8 filled with the conductors 23 and between the adjacent circuit patterns 14. Using these ferroelectric material 24 and conductor 23, a capacitor 24 is three-dimensionally provided in the direction of thickness of the insulating layer of the electronic component base.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a substrate for electronic parts such as a package and a substrate, which is formed by arranging two or more circuit patterns at a predetermined interval on an upper surface of an insulating layer or between insulating layers.

[0002]

2. Description of the Related Art Conventionally, there is a substrate for electronic components such as a package and a substrate, which is formed by arranging two or more circuit patterns on an insulator such as ceramic or resin at a predetermined interval.

[0003] This electronic component base is generally formed by laminating a plurality of insulating layers, and has a multilayer structure. Then, two or more circuit patterns may be arranged side by side at predetermined intervals on the upper surface or the insulating layers of the plurality of insulating layers, or two or more circuit patterns may be arranged vertically at predetermined intervals. ing.

Conventionally, when a capacitor is provided on the electronic component substrate, the capacitor is conventionally provided in a planar layer form exclusively along the upper surface of the insulating layer constituting the electronic component substrate or along the lateral direction between the insulating layers. I have.

[0005]

By the way, the conventional capacitor has a structure in which a conductor layer is widely provided on the upper and lower surfaces of a ferroelectric layer with a ferroelectric layer interposed therebetween. As described above, the capacitor is used as an electronic component. If it is provided in the substrate for electronic parts, the capacitor will occupy an extremely large area along the upper surface of the insulating layer or the insulating layer constituting the substrate for electronic parts.

As a result, the capacitor hinders the degree of freedom in arranging two or more circuit patterns arranged side by side at a predetermined interval along the upper surface of the insulating layer of the same electronic component substrate or the lateral direction between the insulating layers. . Then, the arrangement of two or more circuit patterns arranged side by side on the upper surface of the insulating layer or the insulating layer is complicated and made difficult, or two or more circuit patterns arranged side by side at a predetermined interval are arranged on the upper surface of the insulating layer or the insulating layer. The array density was reduced.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem, and a capacitor for an electronic component in which two or more circuit patterns are arranged at predetermined intervals on the upper surface of an insulating layer or between insulating layers is provided. A substrate for an electronic component, which does not occupy a large area in a layer along the upper surface of an insulating layer in which two or more circuit patterns are arranged at predetermined intervals or in a lateral direction between the insulating layers in a planar manner. It is intended to provide.

[0008]

In order to achieve the above object, a substrate for electronic parts of the present invention is a package in which two or more circuit patterns are arranged at a predetermined interval on an upper surface of an insulating layer or between insulating layers. In a substrate for electronic parts such as a substrate, conductors are respectively filled in via holes provided above and below in an insulating layer portion immediately below each circuit pattern arranged at a predetermined interval, and between the via holes filled with those conductors. Insulating layer portions located, filling the via holes provided above and below the insulating layer portion located between the circuit patterns with a ferroelectric, and using those ferroelectrics and conductors,
It is characterized in that capacitors are three-dimensionally provided in the thickness direction of the insulating layer.

In this electronic component substrate, a conductor for forming a capacitor is filled in the insulating layer portion by effectively utilizing an insulating layer portion immediately below the circuit pattern, where the circuit pattern is not generally formed. There is a via hole.

Therefore, the via hole filled with the conductor for forming the capacitor is located on the upper surface of the insulating layer or the insulating layer suitable for forming the circuit pattern, and the upper surface of the insulating layer other than the portion where the circuit pattern is formed or It is possible to prevent a large area from occupying a plane along the lateral direction between the insulating layers. Then, another circuit pattern is placed on the upper surface of the insulating layer or between the insulating layers other than where the circuit pattern is formed,
The via hole filled with the conductor for forming the capacitor can be easily and freely formed without any obstruction. And the density of the circuit pattern formed on the electronic component base can be increased.

Further, in this electronic component substrate, the inner portion of the insulating layer located between the circuit patterns, which is generally not formed with the circuit pattern, is effectively utilized, and the upper and lower portions of the inner portion of the insulating layer are effectively used. A via hole filled with a ferroelectric material for forming a capacitor is provided in the direction.

This prevents the via hole filled with the ferroelectric for forming the capacitor from occupying a large area in the lateral direction between the upper surface of the insulating layer or the insulating layer suitable for forming a circuit pattern. be able to. Then, the circuit pattern can be easily and freely formed with a margin without being largely obstructed by the via hole filled with the ferroelectric for forming the capacitor.
And the density of the circuit pattern formed on the electronic component base can be increased.

[0013]

1 to 3 show a preferred embodiment of a ceramic package of a substrate for electronic parts of the present invention, FIG. 1 is a partial front sectional view thereof, and FIG. 2 is a partial plan view thereof. 3 is a partial side sectional view thereof. Hereinafter, this package will be described.

In the package shown in FIG.
%, Three low-temperature firing green sheets 5a, 5b, 5 in the form of a rectangular frame containing 40% by weight of borosilicate glass.
c are sequentially stacked to form a package forming member. A cavity 4 for housing a semiconductor element is formed inside the package forming member. On the upper surface of the intermediate green sheet 5b of the package forming member, Au or Ag-Pd for low-temperature firing for forming the circuit pattern 14 is provided.
A plurality of metallized paste lines 6 are provided side by side at a predetermined pitch.

On the upper surface of the upper green sheet 5c and on the lower surface of the lower green sheet 5a, a metallized paste layer 6 of Au or Ag-Pd for low-temperature firing for forming the metallized layer 9 is provided.

In the intermediate green sheet 5b immediately below the metallized paste line 6 for forming the circuit pattern 14,
As shown in FIGS. 1, 2 and 3, a plurality of via holes 8 are formed by vertically penetrating the green sheet 5b.
Are arranged in parallel with the metallized paste line 6 at predetermined intervals. Then, Au or Ag- for low-temperature firing for forming the conductor 23 is formed in each of the via holes 8.
Each is filled with a metallizing paste 7 such as Pd. The upper end of the metallized paste 7 filled in each of the via holes 8 is connected to the metallized paste line 6 for forming the circuit pattern 14.

The intermediate green sheet 5b located between the via holes 8 filled with the metallizing paste 7 and the intermediate green sheet 5b located between the adjacent metallizing paste lines 6 for forming the circuit patterns 14 As shown in FIG. 2 and FIG. 3, a plurality of via holes 8 are formed by vertically penetrating the green sheet 5b.
Are arranged in parallel with the metallized paste line 6 at predetermined intervals. Each of the via holes 8 is filled with a ferroelectric material 20 such as a Pb composite perovskite for low-temperature firing.

Next, three green sheets 5a, 5a
A ceramic package forming member formed by stacking b and 5c is placed in a furnace or the like and integrally fired at a low temperature of about 1000 ° C. to form a ceramic package 1d formed by stacking three insulating layers.

At the same time, a plurality of circuit patterns 14 are formed side by side on the upper surface of the intermediate insulating layer at a predetermined pitch, a metallized layer 9 is formed on the upper surface of the upper insulating layer, and a metallized layer 9 is formed on the lower surface of the lower insulating layer. Via holes 8 formed or provided in the intermediate insulating layer portion directly below the circuit pattern 14
Is filled with the conductor 23, or the via hole 8 provided in the intermediate insulating layer portion located between the adjacent circuit patterns 14 is filled with the ferroelectric substance 22. Using the conductor 23 filled in the via hole 8, the upper end of which is a conductor 23 connected to the circuit pattern 14 and the ferroelectric substance 22 filled in the via hole 8, the adjacent circuit pattern 1 is used.
Capacitors 24 electrically connecting the four in parallel are provided three-dimensionally in the thickness direction of the intermediate insulating layer portion of the ceramic package 1d.

Thereafter, a bottom plate 10 is brazed to the metallized layer 9 formed on the lower surface of the ceramic package 1d. Then, the bottom surface of the cavity 4 of the ceramic package 1d is covered with the bottom plate 10. At the same time, a stage 11 is brazed to the surface of the bottom plate 10 exposed in the cavity 4.

The ceramic package 1d shown in FIGS. 1 to 3 is configured as described above.

Next, an example of use of the ceramic package 1d and its operation will be described.

As shown in FIG. 1, the semiconductor element 12 is mounted on the stage 11 in the cavity 4. Then, the electrode 13 of the semiconductor element and the inner end of the circuit pattern 14 are electrically connected by a wire 16.

Next, the upper surface of the cavity 4 is
And the cap 17 is brazed to the metallized layer 9 on the upper surface of the upper insulating layer. Then, the semiconductor element 12 is sealed in the cavity 4. The inner end of the lead 18 is connected to the outer end of the circuit pattern 14 by soldering or the like, and the lead 18 extends outside the ceramic package 1d.

Then, when a power supply current or an electric signal flows through the lead 18, the current or the signal is transmitted to the electrode 13 of the semiconductor element through the circuit pattern 14 and the wire 16. Then, the semiconductor element 12 operates with the current or the signal.

At this time, the high-frequency signals transmitted through the adjacent circuit patterns 14 mix with each other through the capacitors 24 electrically connecting the adjacent circuit patterns 14 in parallel.

Here, an equivalent circuit of the capacitor 24 provided in the ceramic package 1d shown in FIGS. 1 to 3, wherein the adjacent circuit patterns 14 of the ceramic package 1d are electrically connected in parallel. FIG. 4 shows the diagram.

In the ceramic package 1d shown in FIG. 1 to FIG.
Via holes 8 filled with conductors 23 for forming capacitors 24 electrically connected in parallel are provided three-dimensionally in the thickness direction of the intermediate insulating layer portion immediately below the circuit pattern 14.
Therefore, the via hole 8 filled with the conductor 23 for forming the capacitor 24 has a sufficient space without being disturbed by the circuit pattern 14 on the upper surface of the intermediate insulating layer by effectively utilizing the intermediate insulating layer portion immediately below the circuit pattern 14. It can be easily and accurately provided three-dimensionally. At the same time, another circuit pattern is formed on the upper surface of the intermediate insulating layer other than where the circuit pattern 14 is formed or between the upper insulating layer and the intermediate insulating layer by a via hole 8 filled with a conductor 23 for forming a capacitor 24.
It can be easily and freely formed with a margin without being disturbed.

Further, by effectively utilizing the inner portion of the intermediate insulating layer located between the circuit patterns 14, the ferroelectric substance 22 for forming the capacitor 24 is formed in the vertical direction of the inner portion of the intermediate insulating layer.
A via hole 8 filled with is provided. Therefore, the via hole 8 filled with the ferroelectric substance 22 for forming the capacitor 24 is wide in the lateral direction between the upper surface of the intermediate insulating layer suitable for forming the circuit pattern 14 or between the upper insulating layer and the intermediate insulating layer. The circuit pattern 14 can be easily and freely formed with a margin while preventing the area from being occupied in a plane, and between the upper insulating layer or the upper insulating layer and the intermediate insulating layer.

FIG. 5 shows another preferred embodiment of the ceramic package of the electronic component substrate of the present invention, and FIG. 5 is a partial front sectional view thereof. Hereinafter, this package will be described.

In the package shown in the figure, three green sheets 5a similar to the package forming member shown in FIG.
A metallized paste line 6 for low-temperature firing for forming the circuit pattern 14 is provided between the upper green sheet 5c and the intermediate green sheet 5b, which is the upper surface of the intermediate green sheet 5b of the package forming member formed by sequentially stacking 5b and 5c. Is provided in a state in which the middle part thereof is cut into a predetermined length. In other words, two metallized paste lines 6 for forming the circuit pattern 14 are provided at predetermined intervals between the upper layer green sheet 5c and the intermediate layer green sheet 5b.
They are arranged vertically.

In the intermediate green sheet 5b immediately below the inner end of each metallized paste line 6 vertically arranged between the upper green sheet 5c and the intermediate green sheet 5b, the green sheet 5b is vertically penetrated. Let me
Each via hole 8 is provided. Each of the via holes 8 is filled with a metallizing paste 7 for low-temperature firing for forming the conductor 23. The upper ends of the metallized pastes 7 are connected to the inner ends of the metallized paste lines 6, respectively.

The intermediate green sheet 5b located between the inner ends of the metallized paste lines 6 vertically arranged between the upper green sheet 5c and the intermediate green sheet 5b.
In the intermediate green sheet 5b located between the via holes 8 provided in the intermediate green sheet 5b immediately below the inner end of each metallized paste line 6, the green sheet 5b is vertically penetrated. A via hole 8 is provided. And in the via hole 8,
A ferroelectric forming material 20 such as a Pb composite perovskite system for low temperature firing is filled.

Next, the three green sheets 5a, 5a
A ceramic package forming member formed by laminating b and 5c is placed in a furnace or the like and integrally fired at a low temperature of about 1000 ° C. to form a ceramic package 1e formed by laminating three insulating layers.

At the same time, two circuit patterns 14 are provided between the upper insulating layer corresponding to the upper surface of the intermediate insulating layer and the intermediate insulating layer.
Are arranged vertically, the metallized layer 9 is formed on the upper surface of the upper insulating layer, the metallized layer 9 is formed on the lower surface of the lower insulating layer, and the metallized layer 9 is formed on the intermediate insulating layer immediately below the inner end of the circuit pattern 14. The via holes 8 are filled with the conductors 23, and the via holes 8 provided in the intermediate insulating layer portion located between the inner ends of the circuit pattern 14 are filled with the ferroelectric substance 22. An intermediate insulating layer is formed by using the conductor 23 filled in each of the via holes 8 and having the upper end thereof connected to the inner end of each circuit pattern 14 and the ferroelectric 22 filled in the via hole 8. A capacitor 24 that electrically connects in series the inner ends of the circuit patterns 14 that are vertically arranged on the upper surface is three-dimensionally provided in the thickness direction of the intermediate insulating layer portion of the ceramic package 1e.

Thereafter, the bottom plate 10 is brazed to the metallized layer 9 formed on the lower surface of the ceramic package 1e. The bottom surface of the cavity 4 of the ceramic package 1e is closed by the bottom plate 10. At the same time, a stage 11 is brazed to the surface of the bottom plate 10 exposed in the cavity 4.

The ceramic package 1e shown in FIG.
Is configured as described above.

Next, an example of use of the ceramic package 1e and its operation will be described.

As shown in FIG. 5, the semiconductor element 12 is mounted on the stage 11 in the cavity 4. Then, the electrode 13 of the semiconductor element and the inner end of the circuit pattern 14 are electrically connected by a wire 16.

Then, the upper surface of the cavity 4 is capped with a cap 17.
And the cap 17 is brazed to the metallized layer 9 on the upper surface of the upper insulating layer. Then, the semiconductor element 12 is sealed in the cavity 4. The inner end of the lead 18 is connected to the outer end of the circuit pattern 14 by soldering or the like, and the lead 18 extends outside the ceramic package 1e.

Then, when a power supply current or an electric signal flows through the lead 18, the current or the signal is transmitted to the electrode 13 of the semiconductor element through the circuit pattern 14 and the wire 16. Then, the semiconductor element 12 operates with the current or the signal.

At this time, the high-frequency signals transmitted through the circuit patterns 14 vertically arranged on the upper surface of the intermediate insulating layer are transmitted to each other through the capacitors 24 electrically connecting the circuit patterns 14 in series.

Here, an equivalent circuit diagram of the capacitor 24 provided in the ceramic package 1e shown in FIG. 5 and electrically connecting the inner ends of the circuit patterns 14 of the ceramic package 1e in series is shown. Indicate
It becomes like FIG.

The ceramic package 1 shown in FIG.
In e, the via hole 8 filled with the conductor 23 for forming the capacitor 24 that electrically connects the inner ends of the circuit pattern 14 in series is formed in the thickness direction of the intermediate insulating layer portion immediately below the inner end of the circuit pattern 14. It is equipped with three-dimensional. Therefore, by effectively utilizing the intermediate insulating layer portion immediately below the circuit pattern 14, the via hole 8 filled with the conductor 23 for forming the capacitor 24 is formed in the circuit pattern 1 on the upper surface of the intermediate insulating layer.
It is possible to easily and accurately prepare three-dimensionally with a margin without being disturbed by 4. Along with that, the circuit pattern 14
Other circuit patterns are provided between the upper surface of the intermediate insulating layer or between the upper insulating layer and the intermediate insulating layer other than the location where Can be easily and freely formed.

Further, by effectively utilizing the inner portion of the intermediate insulating layer located between the inner ends of the circuit pattern 14, the via filled with the ferroelectric substance 22 for forming the capacitor 24 is formed in the vertical direction of the inner portion of the intermediate insulating layer. Hall 8 is provided. Therefore, the via hole 8 filled with the ferroelectric material 22 for forming the capacitor 24 is wide in the lateral direction between the upper surface of the intermediate insulating layer suitable for forming the circuit pattern 14 or the upper insulating layer and the intermediate insulating layer. Preventing the area from occupying a plane,
The circuit pattern 14 can be easily and freely formed with a margin between the upper surface of the intermediate insulating layer or between the upper insulating layer and the intermediate insulating layer.

The above-mentioned ceramic packages 1d, 1
In the case of e, the green sheets 5a, 5b, and 5c may be ordinary green sheets for high-temperature firing containing 92 Wt% of alumina, or the metallized paste line 6, the metallized paste layer 6, and the metallized paste 7 may have about 150
It is also possible to use a metallizing paste for high temperature firing that does not melt or collapse even if a high temperature of 0 ° C. is applied.

Further, an insulating layer made of a molded resin or the like may be used as an insulating layer for forming the ceramic packages 1d and 1e. Then, via holes may be provided above and below the insulating layer, the via holes may be filled with a metallizing paste or a ferroelectric forming material, and then the insulating layer may be exposed to a high temperature. Then, the metallized paste or the ferroelectric forming material may be dried, and the metallization or the ferroelectric for forming the capacitor may be integrally fixed and filled in the via holes provided in the insulating layer. Then, by using these metallized and ferroelectric materials, capacitors may be three-dimensionally provided vertically in the thickness direction of the insulating layers of the ceramic packages 1d and 1e.

The via hole 8 filled with the ferroelectric substance 22 and the via hole 8 filled with the conductor 23 are formed not in a circular shape but in a polygonal shape such as a quadrangle or an elliptical shape. Is also good.

Further, the above-mentioned ceramic packages 1d, 1
In e, the via hole 8 filled with the ferroelectric substance 22
It goes without saying that the capacitor 24 is formed by using the insulating layer portion made of ceramic around the via hole 8 filled with the conductor 23 and a part of the dielectric for forming the capacitor 24.

The present invention is also directed to a substrate having a circuit pattern formed on the upper surface of the insulating layer or between the insulating layers, and a substrate for electronic components such as a package having a circuit pattern formed on the upper surface of the insulating layer and a substrate. Is also available.

[0051]

As described above, according to the substrate for electronic parts of the present invention, the insulating layer portion directly below the circuit pattern in which the circuit pattern is not generally formed is effectively used, and the insulating layer portion is formed in the thickness direction. The via hole filled with the conductor for forming the capacitor can be provided vertically and three-dimensionally easily and freely without being disturbed by the circuit pattern.

Also, the via hole filled with a conductor for forming a capacitor may be provided between the upper surface of the insulating layer or the insulating layer suitable for forming a circuit pattern, and the upper surface or the insulating layer other than the portion where the circuit pattern is formed. It is possible to prevent a large area in a layer form from being occupied in a plane along the horizontal direction between the layers. Then, along the upper surface of the insulating layer other than where the circuit pattern is formed or along the horizontal direction between the insulating layers, another circuit pattern is formed at a high density without being disturbed by the via hole filled with the conductor for forming the capacitor. It can be formed freely.
In addition, high integration of the electronic component substrate can be achieved.

Further, it is prevented that the via hole filled with the ferroelectric material for forming the capacitor planarly occupies a wide area in the lateral direction between the upper surface of the insulating layer or the insulating layer suitable for forming the circuit pattern. It is possible to freely form a circuit pattern on the upper surface of the insulating layer or between the insulating layers with a high density without being greatly disturbed by the via hole filled with the ferroelectric for forming the capacitor. In addition, high integration of the electronic component substrate can be achieved.

[Brief description of drawings]

FIG. 1 is a partial front sectional view of a ceramic package of the present invention.

FIG. 2 is a partial plan sectional view of the ceramic package of the present invention.

FIG. 3 is a partial side sectional view of the ceramic package of the present invention.

FIG. 4 is an equivalent circuit diagram of a capacitor provided in the ceramic package of FIG. 1;

FIG. 5 is a partial front sectional view of the ceramic package of the present invention.

FIG. 6 is an equivalent circuit diagram of a capacitor provided in the ceramic package of FIG.

[Explanation of symbols]

 1 Substrate for Electronic Component 1d, 1e Ceramic Package 4 Cavities 5a, 5b, 5c Green Sheet 6 Metallized Paste Line, Metallized Paste Layer 7 Metallized Paste 8 Via Hole 9 Metallized Layer 10 Bottom Plate 11 Stage 12 Semiconductor Element 14 Circuit Pattern 16 Wire 17 Cap 18 Lead 20 Ferroelectric Material 22 Ferroelectric 23 Conductor 24 Capacitor

Claims (3)

[Claims] 1. A package in which two or more circuit patterns are arranged at a predetermined interval on the upper surface of the insulating layer or between the insulating layers,
In a substrate for electronic parts such as a substrate, conductors are respectively filled in via holes provided above and below in an insulating layer portion immediately below each circuit pattern arranged at a predetermined interval, and between the via holes filled with those conductors. Insulating layer portions that are located, filling the via holes provided above and below the insulating layer portions that are located between the circuit patterns with a ferroelectric,
A substrate for electronic parts, characterized in that a capacitor is three-dimensionally provided in the thickness direction of the insulating layer by using these ferroelectrics and conductors. 2. The substrate for electronic parts according to claim 1, wherein two or more circuit patterns are arranged side by side at a predetermined interval. 3. The substrate for electronic parts according to claim 1, wherein two or more circuit patterns are vertically arranged at a predetermined interval.