JPH09219447A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to manufacture a bipolar transistor of a high cut-off frequency by a method wherein the distances between an element isolation region and a collector buried region and a collector contact region in the depth direction of the element isolation region are shortened by etching an epitaxial layer other than an element part and with a parasitic capacity due to the element isolation region reduced, a collector resistance is reduced. SOLUTION: An N-type collector buried and diffused region 2 and a P-type element isolation buried region 3 are formed in a P-type silicon substrate 1, an N-type epitaxial layer 4 is grown on the regions 2 and 3 and moreover, after an oxide film 5 is formed on the layer 4, a resist film 6 is formed at a prescribed position on the film 5. The film 5 is removed using the film 6 as a mask, the film 4 is etched using the left film 5 as a mask and an element isolation diffused region 7 is formed. Then, the film 5 is all removed, an oxide film 8 is again formed and such a resist film 9 as the surface of the film 9 becomes flat is formed on the film 8. The film 9 is removed in such a way that the surface of the film 5 on an active part of the film 4 is exposed and P-type ions are implanted in the film 5.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a method of manufacturing a semiconductor device including a bipolar transistor having a high cutoff frequency f _T.

[0002]

2. Description of the Related Art A typical method of manufacturing a bipolar transistor will be described with reference to process sectional views of FIG.

As shown in FIG. 2A, the P-type substrate 1 has N
Type collector buried diffusion region 2 and P type element isolation buried region 3 are formed by a thermal diffusion method or the like, and an N type epitaxial layer 4 is further grown.

Next, as shown in FIG. 2B, a P-type element isolation diffusion region 14 and a P-type base region 15 are formed by an ion implantation method.

Finally, as shown in FIG. 2C, an N-type emitter contact region 17 is formed in the N-type collector contact region 16 and the base region by ion implantation.

[0006]

In the above-mentioned prior art, since the distance in the depth direction of the element isolation region 3 becomes long, the parasitic capacitance due to the element isolation region becomes large. Also,
Since the epitaxial layer between the collector buried region and the collector contact region has a large specific resistance, the spreading resistance increases and the collector resistance also increases. Junction capacitance C _sub and collector resistance r _C due to these parasitic elements and element isolation regions
Is larger, the cutoff frequency f _T becomes smaller,
It is difficult to manufacture a bipolar transistor having a high cutoff frequency f _T.

[0007]

The present invention is based on the cutoff frequency f
_In order to manufacture a bipolar transistor with a high _T , the epitaxial layer other than the element part is etched, the distance between the element isolation region and the collector buried region and the collector contact region in the depth direction is shortened, and the epitaxial layer is etched. It is intended to provide a manufacturing method capable of forming a diffusion region that does not require a mask when the diffusion region is formed over the entire non-existing portion (hereinafter referred to as an active portion).

According to the present invention, the parasitic capacitance and collector resistance due to the element isolation region are reduced, and the diffusion region formed in the active portion of the epitaxial layer can be formed at a predetermined position by self-alignment without any deviation. Since it is not necessary to consider the alignment margin, the element size can be reduced. Further, since the diffusion region is not formed even in the etched portion of the epitaxial layer (hereinafter referred to as the passive portion) due to the mask shift, the designed base-collector breakdown voltage can be secured.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the cross-sectional views of FIG.

As shown in FIG. 1A, an N type collector buried diffusion region 2 and a P type element isolation buried region 3 are formed on a P type silicon substrate 1 by a thermal diffusion method, and are formed thereon. N
After the epitaxial layer 4 is grown and an oxide film 5 is further formed, a resist film 6 is formed at a predetermined position by a photoresist process.

Next, as shown in FIG. 1B, the resist film 6
Is used as a mask to remove the oxide film 5, and the remaining oxide film 5 is used as a mask to etch the epitaxial layer 4 to form a diffusion region 7 for element isolation.

Next, as shown in FIG. 1C, the oxide film is completely removed once, an oxide film 8 is formed again, and a resist film 9 is formed thereon so that the surface becomes flat.

Next, as shown in FIG. 1D, the resist film is removed so that the surface of the oxide film on the active portion of the epitaxial layer is exposed, and P-type ions 10 are implanted by the ion implantation method. At this time, since the etched portion is filled with the mask material, impurity ions are not introduced into the passive portion.

Finally, as shown in FIG. 1E, the resist film is completely removed and an annealing process is performed to form a base diffusion region 11, and an N-type collector contact region 12 is formed by an ion implantation method. An N type emitter contact region 13 is formed in the region 11 by an ion implantation method. Parasitic capacitance C _sub and collector resistance r _C due to the element isolation region in the bipolar transistor
The smaller the value of, the larger f _T.

For the above reasons, this manufacturing method can improve the cutoff frequency f _T of the bipolar transistor.

[0016]

As described above, according to the present invention, by etching the epitaxial layer other than the element portion, the distance in the depth direction of the element isolation region is shortened, so that the parasitic capacitance due to the element isolation region can be reduced. . Further, since the spreading resistance of the collector buried region and the collector contact region is also reduced, the collector resistance can be reduced. Further, when forming the diffusion region in the entire active portion of the epitaxial layer, it is possible to form a base diffusion region that does not require a mask, so it can be formed at a predetermined position without any deviation, and it is necessary to consider the mask alignment margin. Therefore, the element size can be reduced. Further, since there is no mask displacement, the diffusion region is prevented from being formed even in the passive portion of the epitaxial layer, so that the base-collector breakdown voltage as designed can be secured. With these improvements, a semiconductor device including a bipolar transistor having a high cutoff frequency f _T can be manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing a process of a semiconductor device according to the present invention.

FIG. 2 is a sectional view showing a process of a semiconductor device according to a conventional example.

[Explanation of symbols]

1: P-type silicon substrate, 2: collector buried diffusion region,
3: element isolation diffusion buried region, 4: N type epitaxial layer, 5: first oxide film, 6: first resist film, 7: element isolation diffusion region, 8: second dioxide film, 9: second resist film,
10: P-type ions, 11: base diffusion region, 12: collector contact region, 13: emitter contact region, 14: element isolation diffusion region by conventional method, 15:
Base diffusion region by a conventional method, 16: collector contact region by a conventional method, 17: emitter contact region by a conventional method.

Claims (1)

[Claims] 1. A semiconductor device having a passive element formed on the surface of a first conductivity type semiconductor substrate, the step of etching an arbitrary portion of the semiconductor substrate, and forming an oxide film on the entire surface of the semiconductor substrate. Forming a material film serving as a mask on the oxide film so as to have a flat surface; and etching the material film until the surface of the oxide film on the semiconductor substrate not etched in the etching step is exposed A method of manufacturing a semiconductor device, comprising: a step of implanting ions into the exposed region of the surface.