JPH09215182A - Load drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect an output transistor against thermal breakdown due to overcurrent through simple circuitry including no microcomputer by a constitution wherein a decision circuit receives a signal from a delay circuit and a short circuit detection signal of a load and produces a decision signal for turning the output transistor off. SOLUTION: A decision circuit 9 receives a delayed input signal from a delay circuit 11 and a short circuit detection signal of a load Z and produces a decision signal. A control circuit 8 turns an output transistor off based on the decision signal. Since short circuit of output terminals P1, P2 is monitored constantly at the output terminals P1, the output transistor 5 at an output circuit section 2 can be protected against thermal breakdown due to overcurrent. Since no microcomputer is employed, the circuitry can be constituted simply at low cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a load drive circuit.

[0002]

2. Description of the Related Art Conventionally, various load drive circuits have been proposed. FIG. 5 shows a load drive circuit according to the current flow-out method. In the load drive circuit 50, the control input circuit 5
1, a PNP transistor 52, resistors 53 and 54, a diode Df, and output terminals X and Y,
Power is supplied from the power supply (power supply voltage) VCC. That is, the load drive circuit 50 includes a drive stage by the control input circuit 51 and an output stage by the transistor 53, and drives the inductive load Z such as a solenoid or a motor.

When a signal is input to the input terminal of the control input circuit 51, an L level signal is output from the output terminal of the control input circuit 51. The transistor 52 is turned on by the L level output signal from the output terminal of the control input circuit 51. As a result, a current is supplied from the power supply Vcc to the load Z via the transistor 52 and driven. The diode Df is a flywheel diode for flowing the induced electromotive force generated in the load Z.

FIG. 6 shows a load drive circuit based on the current limiting method. The load drive circuit 70 is different from the load drive circuit 50 based on the current flow-out method shown in FIG.
The resistor 54 is removed and an overcurrent protection circuit 60 is newly provided. The overcurrent prevention circuit 60 is composed of a PNP transistor 61 and resistors 62 and 63. The emitter of the transistor 61 is connected to the power supply Vcc, and the collector of the transistor 61 is connected to the base of the transistor 52. The emitter of the transistor 52 is
It is connected to the power supply VCC through the resistor 63, and the resistor 62
Is connected to the base of the transistor 61 through.

When a signal is input to the input terminal of the control input circuit 51, an L level signal is output from the output terminal of the control input circuit 51. The transistor 52 is turned on by the L level output signal from the output terminal of the control input circuit 51. As a result, a current is supplied from the power supply Vcc to the load Z via the transistor 52 and driven.

At this time, the overcurrent prevention circuit 60 operates the power source V
The current I flowing from CC to the transistor 52 is detected by the resistor 63, and when the current I exceeds a certain level, the transistor 6
1 turns on, pulling up the base of transistor 52 to turn off transistor 52. As a result, even when a signal is input to the input terminal of the control input circuit 51 and an L level signal is output from the output terminal of the control input circuit 51, the transistor 52 is turned off, and when the load is short-circuited or the ground is short-circuited. It is also possible to prevent overcurrent from flowing.

FIG. 7 shows a load driving circuit having a protection circuit using a microcomputer. Load drive circuit 90
A protection circuit 80 and a microcomputer (hereinafter, referred to as a microcomputer) 81 are newly provided inside the load driving circuit 50 shown in FIG. The protection circuit 80 includes a resistor 82, a Zener diode 83 and a capacitor 84. An input terminal of the control input circuit 51 is connected to the output port P1 of the microcomputer 81. Transistor 52
A resistor 82 is connected between the emitter and collector of the.
The resistance 82 is a high resistance and is sufficiently larger than the resistance of the load Z. Therefore, when the transistor 52 is off, the current flowing from the power supply Vcc to the load Z via the resistor 82 is extremely small, the load Z is not driven by the current, and the power consumption is small. The collector (output terminal X) of the transistor 52 is connected to the input port P2 of the microcomputer 81. The Zener diode 83 and the capacitor 5 are connected between the input port P2 and the ground.

When an L level signal is input from the output port P1 of the microcomputer 81 to the input terminal of the control input circuit 51,
An L level signal is output from the output terminal of the control input circuit 51. The transistor 52 is turned on by the L level output signal from the output terminal of the control input circuit 51. As a result, a current is supplied from the power supply Vcc to the load Z via the transistor 52 and driven.

At this time, when the load is short-circuited or the earth is short-circuited, the potential of the output terminal X becomes almost 0V.
That is, the input port P2 of the microcomputer 81 changes from H level to L level. As a result, the microcomputer 81 determines that the load is shorted or the ground is shorted, and switches the signal of the output port P1 from the L level to the H level. Then, the control input circuit 51 is turned off, the transistor 52 is also turned off,
Overcurrent can be prevented from flowing to the transistor 52.

[0010]

However, in the load drive circuit 50 shown in FIG. 5, when the output terminal X is short-circuited to the load or short-circuited to the ground, an overcurrent flows through the transistor 52 and causes thermal damage.

Further, the load drive circuit 70 shown in FIG. 6 sets the necessary and sufficient current value for the load Z by means of the resistor 63.
When the output terminal X is short-circuited to the load or shorted to earth,
Only the set current flows to the transistor 52,
It cannot be said to be a reliable protection circuit.

Further, the load drive circuit 90 shown in FIG. 7 always monitors the state of the output terminal X to ensure the transistor 52.
However, the load drive circuit 90 cannot be used in a simple circuit that does not use the microcomputer 81.

The present invention has been made in order to solve the above problems, and an object thereof is to prevent thermal damage to an output transistor due to overcurrent with a simple circuit configuration without using a microcomputer. It is to provide a load drive circuit.

[0014]

In order to solve the above problems, the invention according to claim 1 controls an output transistor based on an input signal, and supplies power to the load through the transistor to supply a load. In a load drive circuit for driving a circuit, a delay circuit that delays and outputs the input signal, a signal from the delay circuit, and a detection signal that detects a short circuit of the load are input, and determination is performed based on those signals. A determination circuit that outputs a signal and a control circuit that controls the output transistor to turn off based on the determination signal output from the determination circuit are provided.

According to a second aspect of the present invention, in a load drive circuit for controlling an output transistor based on an input signal and supplying power to the load through the transistor to drive the load, the input signal is supplied to the load drive circuit. A delay circuit for delaying and outputting, the input signal, and a signal from the delay circuit,
A determination circuit that inputs a detection signal that detects a short circuit of the load and outputs a determination signal based on those signals,
A holding circuit that holds the judgment signal output from the judgment circuit, and a control circuit that controls the output transistor to be turned off based on the holding state of the holding circuit are provided.

According to a third aspect of the present invention, in the load drive circuit for controlling the output transistor based on the input signal and supplying the power to the load through the transistor to drive the load, the input signal is A determination that inputs a first transistor input to the base terminal, an output signal from the first transistor, and a detection signal that detects the short circuit of the load, and outputs a determination signal based on those signals A circuit, a holding circuit that holds the judgment signal output from the judgment circuit, and a base terminal of the output transistor, which is controlled based on a holding state of the holding circuit and which controls the output transistor to be turned off. 2 transistors, and the first and second transistors and the output transistor are turned on and off,
A delay signal generator for delaying the input signal and inputting it to the determination circuit is provided.

Therefore, according to the invention of claim 1,
The delay circuit delays the input signal and outputs it. The determination circuit inputs the signal from the delay circuit and the detection signal for detecting the load short circuit, and outputs the determination signal based on these signals. The control circuit controls the output transistor to be off based on the determination signal output from the determination circuit.

According to the second aspect of the invention, the delay circuit delays the input signal and outputs it. The judgment circuit
The input signal, the signal from the delay circuit, and the detection signal for detecting the load short circuit are input, and the determination signal based on those signals is output. The holding circuit holds the determination signal output from the determination circuit. The control circuit controls the output transistor to be off based on the holding state of the holding circuit.

According to the invention described in claim 3, the first
An input signal is input to its base terminal, and the transistor is controlled based on the input signal. The determination circuit is the first
The output signal from the transistor and the detection signal for detecting the load short circuit are input, and the determination signal based on these signals is output. The holding circuit holds the determination signal output from the determination circuit. The second transistor is connected to the base terminal of the output transistor, is controlled based on the holding state of the holding circuit, and turns off the output transistor. The delay signal generation unit delays the input signal by the ON / OFF time of the first and second transistors and the output transistor, and inputs the delayed input signal to the determination circuit.

[0020]

DETAILED DESCRIPTION OF THE INVENTION

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS.

FIG. 1 shows a load drive circuit 1. The load drive circuit 1 includes an output circuit unit 2 for supplying electric power to the load Z, a control circuit unit 3 for driving and controlling the output circuit unit 2, and a control signal for driving the control circuit unit 3 And a control input circuit section 4 for supplying S3.

The output circuit section 2 includes a PNP transistor 5,
It consists of resistors 6 and 7, a diode Df, and output terminals P1 and P2. The emitter of the transistor 5 is connected to the power supply (power supply voltage) Vcc, and the collector of the transistor 5 is connected to the output terminal P1. A resistor 7 is connected between the base and the emitter of the transistor 5. The base of the transistor 5 is connected to the control circuit unit 3 via the resistor 6. The transistor 5 is turned on and off based on the drive signal S1 from the control circuit unit 3.

On the other hand, the output terminal P2 is grounded. An inductive load Z such as a solenoid or a motor is connected between the output terminals P1 and P2. The load Z is designed so that when the transistor 5 is turned on, a current is supplied from the power source Vcc and it is driven. The output terminal P1 is connected to the control circuit unit 3
The voltage applied to the load Z at the output terminal P1 is supplied to the control circuit unit 3 as the detection signal S2. In the present embodiment, the detection signal S2
Is a positive potential (hereinafter referred to as H level) when the transistor 5 is in the ON state and supplying power to the load Z. Further, when the transistor 5 is on and the load Z is short-circuited, the potential is zero (hereinafter referred to as L level). A diode Df is connected between the output terminals P1 and P2, and the diode Df is a flywheel diode for flowing an induced electromotive force generated in the load Z.

Next, the control circuit section 3 includes the control input circuit section 4
To input the control signal S3. The input terminal of the control input circuit unit 4 is connected to an internal circuit (not shown), and the control signal S3 of H and L levels based on the control signal S4 output from the internal circuit is output to the control circuit unit 3. ing.

The control circuit unit 3 is a NAN as a control circuit.
D circuit 8, OR circuit 9 as a determination circuit, NOT circuit 1
0, a delay circuit 11, and a storage circuit 12 as a holding circuit. The NAND circuit 8 has two input terminals, and one input terminal is connected to the output terminal of the control input circuit unit 4. The output terminal of the NAND circuit 8 is connected to the base of the transistor 5 via the resistor 6 and outputs the drive signal S1 to the base of the transistor 5.

The OR circuit 9 has three input terminals, and one input terminal is connected to the output terminal of the control input circuit section 4 via the NOT circuit 10. Then, the OR circuit 9 inputs an inversion signal S5 which is the inversion of the control signal S3.
Further, the second input terminal is connected to the output terminal of the control input circuit unit 4 via the delay circuit 11. Further, the third input terminal is connected to the output terminal P1 and receives the detection signal S2.

The delay circuit 11 comprises a NOT circuit 13, resistors 14, 15 and a capacitor 16. The input terminal of the NOT circuit 13 is connected to the control input circuit section 4 via the resistor 14, and the output terminal of the NOT circuit 13 is connected to the input terminal of the OR circuit 9. Resistor 14 and N
One end of the capacitor 16 is connected to the OT circuit 13 and the other end is grounded. Further, one end of the resistor 15 is connected between the resistor 14 and the NOT circuit 13, and the other end is grounded.

Therefore, when the control signal S3 changes from L level to H level, the capacitor 16 is charged with electric charge,
When the capacitor 16 is completely charged, the NOT circuit 13
Outputs an L level signal S6 to the OR circuit 9.
On the contrary, when the control signal S3 changes from the H level to the L level, the charge stored in the capacitor 16 is changed to the resistance 15
When the discharge of the capacitor 16 is completed, the NOT circuit 13 outputs the H level signal S6 to the OR.
Output to the circuit 9. That is, the signal S6 output from the NOT circuit 13 (inverted signal of the control signal S3) is
The inverted signal S5 output from the T circuit 10 is input to the OR circuit 9 after a delay of the time required for charging / discharging. The time required for this charging / discharging is the resistance 14 and 15 and the capacitor 1.
It is preset by the circuit constant of 6.

In the present embodiment, the delay time T0 of the signal S6 with respect to the inversion signal S5 is set to ON when the transistor 5 is turned on and off based on the control signal S3.
The detection signal S2 from the output terminal P1 based on the off operation is O
It is set longer than the time until it is input to the R circuit 9. That is, the delay circuit 11 delays the control signal S3 from the control input circuit unit 4 until the detection signal S2 appearing at the output terminal P1 in response to the control signal S3 is input to the OR circuit 9. ing.

Therefore, the OR circuit 9 outputs an H level signal S7 from the output terminal when at least one of the input signals S2, S5 and S6 is at H level. On the contrary, the OR circuit 9 outputs an L level signal S7 from the output terminal when all of the input signals S2, S5 and S6 are L level. That is, when the control signal S3 changes from the L level to the H level, the inversion signal S5 changes to the L level, and the detection signal S2 indicates that the transistor 5 is just before being turned on, and the load Z is not supplied with electric power. It is a level.
On the other hand, the delay signal S6 remains at H level. Therefore, the OR circuit 9 outputs the H-level determination signal S7. Eventually, when the transistor 5 is turned on and power is supplied to the load Z, the detection signal S2 becomes H level. This H
The level detection signal S2 is output before the delay time T0. Then, when the delay time T0 elapses, the delay signal S
6 changes from H level to L level. At this time, since the detection signal S2 is already at the H level, the OR circuit 9
Outputs an H level determination signal S7.

Further, although the transistor 5 is turned on, the load Z may cause a short circuit or the like and the detection signal S2 remains at the L level. At this time, when the delay time T0 elapses, the OR circuit 9 determines the L level determination signal S
7 will be output.

The judgment signal S7 of the OR circuit 9 is used as the storage circuit 1
2 is supplied. The memory circuit 12 includes an RS flip-flop (hereinafter referred to as FF) 17 and a reset circuit 18. The input terminal bar S of the FF 17 is connected to the output terminal of the OR circuit 9. Therefore, the input terminal bar S
Inputs the determination signal S7. Also, FF
A reset circuit 18 is connected to the input terminal bar R of 17. The output terminal bar Q of FF17 has the NAN
The input terminal of the D circuit 8 is connected.

When an L level signal is input to the input terminal bar R of the FF 17, the FF 17 is reset and the signal from the output terminal bar Q becomes H level. When an L level signal is input to the input terminal bar S of the FF 17, the F
F17 is set and the signal from the output terminal bar Q becomes L level. Therefore, the NAND circuit 8 outputs the drive signal S1 based on the control signal S3 to the transistor 5 when the output terminal Q is at the H level. Also, NAND
When the output terminal bar Q is at L level, the circuit 8 cuts off the control signal S3 and outputs at H level, that is, the drive signal S1 for turning off the transistor 5, to the transistor 5.

The reset circuit 18 comprises a resistor 19 and a capacitor 20. One end of the resistor 19 is connected to the power source VR, and the other end of the resistor 19 is connected to the input terminal bar R. Further, one end of the capacitor 20 is connected to the connection point between the resistor 19 and the input terminal bar R, and the other end of the capacitor 20 is grounded.

Therefore, when the power source VR is turned on, a current flows from the power source VR to the capacitor 20 through the resistor 19, and the capacitor 20 is charged with electric charge. And
When the capacitor 20 is charged, the input terminal bar R
A voltage is applied from a power source VR to the resistor via a resistor 19. That is, the input terminal bar R changes from the L level to the H level after the capacitor 20 is charged.

At this time, the power supply VR is turned on and the input terminal bar R of the FF 17 is set to H based on the charging of the capacitor 20.
Before the level is reached, the FF 17 becomes operational. As a result, L before the input terminal bar R becomes H level
In response to the level, the FF 17 is reset. Then, the FF 17 is reset and the output terminal bar Q is set to the H level.

On the other hand, when the L level determination signal S7 is input to the input terminal bar S of the FF 17, the FF 17 is set and the output terminal bar Q is set to the L level. Further, even if the H-level determination signal S7 is input, the FF 17 is not set and the output terminal bar Q maintains the same state.

Next, the operation of the load drive circuit 1 configured as described above will be described. As a basic operation, each power supply VCC,
When the power is turned on from VR, the FF 17 is reset and the output terminal bar Q is set to the H level. That FF1
When the output terminal bar Q of 7 is set to the H level, the NAND circuit 8 outputs the drive signal S1 based on only the control signal S3 from the control input circuit unit 4 to the base of the transistor 5. Therefore, the transistor 5 is turned on / off based only on the control signal S3.

On the contrary, the set input terminal bar S of the FF17
This is set when an L level signal is input to, and the output terminal bar Q is set to L level. Then, this set state is held until the FF 17 is reset. That is, it is held until the power supply VR is turned off. That FF1
When the output terminal bar Q of 7 is set to the L level, the NAND circuit 8 continues to output the drive signal S1 of the H level to the transistor 5 regardless of the control signal S3 from the control input circuit unit 4.

Next, the details of the operation of the control circuit section 3 will be described with reference to the timing charts of FIGS. First, the case where the output terminals P1 and P2 are not short-circuited and are in a normal state will be described with reference to FIG. When the control signal S3 of the control input circuit unit 4 is L level, both the inversion signal S5 and the delay signal S6 are H level. Further, the detection signal S2 becomes L level. Therefore,
The determination signal S7 of the OR circuit 9 becomes H level.

When the control signal S3 changes from L level to H level, the inverted signal S5 of the NOT circuit 10 changes to L level. Then, the delay signal S6 changes from the H level to the L level after the elapse of a predetermined delay time T0, but before that, the detection signal S2 changes from the L level to the H level, so that the determination signal S7 of the OR circuit 9 changes to the H level. Hold on level. Therefore, the output terminal bar Q of the FF 17 is held at the H level.

On the contrary, when the control signal S3 changes from the H level to the L level, the transistor 4 is turned off and the inversion signal S5 changes from the L level to the H level before the detection signal S2 changes to the L level. The determination signal S7 of the OR circuit 9 is H
It remains at the level.

Next, the case where the output terminals P1 and P2 are short-circuited from the beginning will be described with reference to FIG. When the control signal S3 is at the L level, the determination signal S7 is at the H level as described above.

When the control signal S3 changes from L level to H level, the inverted signal S5 of the NOT circuit 10 changes to L level. Then, the delay signal S6 goes from the H level to the L level after the elapse of a predetermined delay time T0. Before that, the transistor 4 is turned on based on the control signal S3, and the detection signal S2 should originally be changed from the L level to the H level, but since the output terminals P1 and P2 are short-circuited, the detection signal S2 is It remains at the L level.

As a result, the decision signal S7 of the OR circuit 9 is L
It becomes a level. Therefore, the output terminal bar Q of FF17 is L
The level becomes a level and the transistor 5 is turned off. The OFF state of the transistor 5 is held by the FF 17, and the state is continued until the power source VR is turned off. As a result, the transistor 5 remains off even if the control signal S3 goes high again.

Next, when the load Z is normally driven,
A case where a short circuit occurs between the output terminals P1 and P2 on the way will be described with reference to FIG. When the load Z is normally driven, that is, when the transistor 5 is on, the inversion signal S5 and the delay signal S6 are at L level.
The detection signal S2 is at H level, and the determination signal S7
Is at the H level.

If the output terminals P1 and P2 are short-circuited on the way, the detection signal S2 becomes L level and the determination signal S7 becomes L level. Therefore, the output terminal bar Q of the FF 17 becomes L level and the transistor 5 is turned off. The OFF state of the transistor 5 is held by the FF 17, and the state is continued until the power source VR is turned off. As a result, the transistor 5 remains off even if the control signal S3 goes high again.

As described above, according to the present embodiment,
It has the following features. (1) Since the output terminal P1 always detects whether the output terminals P1 and P2 are normal or short-circuited, the output transistor 5 of the output circuit unit 2 is reliably prevented from being thermally damaged due to overcurrent.

(2) Since the control circuit section 3 is composed of the NAND circuit 8, the OR circuit 9, the NOT circuit 10, the delay circuit 11, and the memory circuit 12 (FF17) without using a microcomputer, the circuit can be easily and It can be constructed at low cost, leading to cost reduction.

(3) When the output terminals P1 and P2 are short-circuited, the FF 17 remains in the set state until the power is turned off. Therefore, when the FF 17 is in the set state, the load Z cannot be driven unless it is reset even if it returns to the normal state on the way. Therefore,
The thermal damage to the output transistor 5 of the output circuit section 2 due to overcurrent is reliably prevented.

(4) Since the reset circuit 18 is composed of the resistor 19 and the capacitor 20, it is resistant to noise and can keep the set state of the FF 17 as long as the power supply VR is not turned off.

(5) When the control signal S3 changes from L level to H level, the transistor 5 has an operating time, and the detection signal S2 from the output terminal P1 is delayed, but the delay circuit 1
The delay signal S6 generated in 1 is used for compensation. Therefore, it is possible to reliably prevent the malfunction of the control circuit unit 4 due to the operation delay of the output circuit unit 2 such as the transistor 5.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to FIGS. In this embodiment, the same members as those in the first embodiment are designated by the same reference numerals and the description thereof will be omitted. Therefore, the difference from the first embodiment will be mainly described below.

FIG. 3 shows the load drive circuit 1a. The load drive circuit 1a differs from the first embodiment in that the NOT circuit 9 and the delay circuit 11 are omitted and a control circuit section 3a is newly provided with a delay inverting circuit 10a as a delay signal generating section. .

The control circuit section 3a comprises a NAND circuit 8, an OR circuit 9a as a judging circuit, a delay inverting circuit 10a, a memory circuit 12 and a reset circuit 18. The NAND circuit 8 includes diodes 21 to 23 and an NPN transistor 2
4 and resistors 25 and 26. NAND
The circuit 8 has two input terminals, and the cathode of the diode 21, which is one of the input terminals, is connected to the output terminal of the control input circuit unit 4 and receives the control signal S3. The anode of the diode 21 is connected to the power supply VR via the resistor 26. The cathode of the diode 23, which is the other input terminal, is connected to the memory circuit 12, and the anode of the diode 23 is connected to the connection point N1 of the diode 21 and the resistor 26.

The anode of the diode 22 is connected to the connection point N1, and the cathode of the diode 22 is connected to the base of the NPN transistor 24 whose emitter is grounded. A resistor 25 is connected between the base and emitter of the transistor 24. The collector of the transistor 24, which is the output terminal of the NAND circuit 8, is connected to the base of the transistor 5 via the resistor 6 of the output circuit unit 2 and outputs the drive signal S1 to the base of the transistor 5. .

Therefore, when the cathode of the diode 23 connected to the memory circuit 12 is at the H level, and the control signal S3 of the H level is input from the control input circuit section 4, the base of the transistor 24 receives a resistance from the power supply VR. Current is supplied via 26 and the diode 22, and the transistor 24 is turned on. As a result, the drive signal S1 is at the L level because a current flows from the power supply VCC to the resistors 7 and 6 and the transistor 24 while the transistor 24 is on. An L level drive signal S1 is input to the base of the transistor 5. Then, the transistor 5 is turned on.

On the contrary, when the cathode of the diode 23 connected to the memory circuit 12 is also at the H level, when the control signal S3 of the L level is input from the control input circuit section 4, the base of the transistor 24 receives the power supply VR. Current flows through the resistor 26 and the L-level cathode diode. Therefore, no current is supplied to the base of the transistor 24, and the transistor 24 turns off. As a result, the drive signal S1 becomes H level, and the transistor 5 is turned off.

That is, when the cathode of the diode 23 connected to the memory circuit 12 is at the H level, the transistors 24 and 5 are turned on and off based on the control signal S3 from the control input circuit section 4.

The OR circuit 9a as a detection circuit is composed of diodes 30, 31 and a resistor 32. O
The R circuit 9a has two input terminals, and the anode of the diode 31, which is one input terminal, is connected to the output terminal P1 and inputs the detection signal S2. The cathode of the diode 31 is grounded via the resistor 32. Diode 3
The cathode of 0 is connected to the connection point N2 of the diode 31 and the resistor 32. The anode of the diode 30, which is the other input terminal, is connected to the output terminal of the control input circuit unit 4 via the delay inverting circuit 10a.

The delay inverting circuit 10a includes resistors 27 and 2
8 and a PNP transistor 29.
The emitter of the transistor 29 is connected to the power supply VR. The collector of the transistor 29, which is the output terminal of the delay inverting circuit 10a, is connected to the anode of the diode 30 of the OR circuit 9a. Transistor 29
A resistor 28 is connected between the base and emitter of the.
The base of the transistor 29 is connected to the output terminal of the control input circuit unit 4 via the resistor 27.

When the control signal S3 changes from L level to H level, the control signal S3 of H level is input to the base of the transistor 29 and the transistor 29 is turned off. At that time, the off operation of the transistor 29 requires time T1. Therefore, the delay inversion signal S8 from the output terminal of the delay inversion circuit 10a is at the L level and is input to the OR circuit 9a with a delay of the time T1 from the control signal S3. On the contrary, when the control signal S3 changes from H level to L level,
The L-level control signal S3 is input to the base of the transistor 29, and the transistor 29 is turned on. At that time, the ON operation of the transistor 29 requires time T2. Therefore, the delayed inverted signal S8 is at the H level and is input to the OR circuit 9a after a delay of the time T2 from the control signal S3.

In a general transistor, paying attention to the time of turning off rather than the time of turning on, the control signal S of H level is given.
Delay time T1 of the L level delayed inverted signal S8 with respect to 3
In the present embodiment, when each of the transistors 24 and 5 is turned on based on the H level control signal S3, the detection signal S2 from the output terminal P1 based on the ON operation is input to the OR circuit 9a. It is longer than time T3. On the contrary, the delay time T2 of the delayed inverted signal S8 of H level with respect to the control signal S3 of L level is, in this embodiment, when the respective transistors 24 and 5 are turned off based on the control signal S3 of L level. The time T4 until the detection signal S2 from the output terminal P1 based on the ON operation is input to the OR circuit 9a is set shorter than T4.

Therefore, if at least one of the input signals S2 and S8 is at H level, the OR circuit 9
An H level signal S7 is output from the output terminal. On the contrary, the OR circuit 9 receives each input signal S
If all of S2 and S8 are L level, an L level signal S7 is output from the output terminal.

That is, when the control signal S3 changes from the L level to the H level, the detection signal S2 is output to each transistor 2
Since the power lines 4 and 5 are turned on and the power is supplied to the load Z, the H level is set. The H-level detection signal S2 is output before the delay time T1. Subsequently, when the delay time T1 elapses, the delayed inverted signal S8 changes from H level to L level. At this time, since the detection signal S2 is already at the H level, the OR circuit 9 outputs the H level determination signal S7. When the control signal S3 changes from H level to L level, the delay inversion signal S8 changes to L level after the delay time T2 elapses.
The level changes from the H level. Then, the detection signal S2 is
Since the transistors 24 and 5 are turned off and the power supply to the load Z is stopped, the L level is set. Since this L level detection signal S2 is output after the delay time T2,
The R circuit 9 outputs an H level determination signal S7.

Further, although the transistor 5 is turned on, the load Z may cause a short circuit or the like, and the detection signal S2 may remain at the L level. At this time, when the delay time T1 elapses, the OR circuit 9 determines the L level determination signal S
7 will be output.

The determination signal S7 of the OR circuit 9 is the storage circuit 1
2 is supplied. The memory circuit 12 includes an RS flip-flop (hereinafter referred to as FF) 17 and a reset circuit 18. The FF 17 is composed of diodes 33 to 35, transistors 36 and 37, and resistors 38 to 41. The cathode of the diode 33 is connected to the connection point N2, and the anode of the diode 33 is connected to the resistor 38.
It is connected to the power source VR via the power source and is supplied from the power source VR. The anode of the diode 34 is connected to the connection point N3 between the anode of the diode 33 and the resistor 38, and the cathode of the diode 34 is
It is connected to the base of an NPN transistor 36 whose emitter is grounded. The base of the transistor 36 is FF1
7 is a set input terminal bar S of 7. A resistor 39 is connected between the base and emitter of the transistor 36.

The collector of the transistor 36 has a resistor 40.
Is connected to the base of an NPN transistor 37 whose emitter is grounded. Base of transistor 37
A resistor 41 is connected between the emitters. Resistance 19
Is connected to a connection point N4 between the resistor 40 and the base of the transistor 37. One end of the resistor 19 has a power source V
Connected to R. One end of the capacitor 20 is connected to the connection point N4, and the other end of the capacitor 20 is grounded. The connection point N4 is the set input terminal bar R of the FF 17. As described above, the reset circuit 18 is composed of the resistor 19, the power supply VR and the capacitor 20.

The cathode of the diode 35 is connected to the collector of the transistor 37, and the anode of the diode 35 is connected to the connection point N3. The N
The cathode of the diode 23 of the AND circuit 8 is connected to the connection point N5 between the diode 35 and the collector of the transistor 37. The cathode of the diode 23 of the NAND circuit 8 is connected to the connection point N5 which is the output terminal bar Q of the FF17.

When the power source is turned on from the power source VR, the capacitor 20 of the reset circuit 18 starts to be charged. Then, when the determination signal S7 of the OR circuit 9a is at the H level, a current flows from the power supply VR to the base of the transistor 36 through the resistor 38 and the diode 34. Therefore, the transistor 36 is turned on. Then, charging of the capacitor 20 from the power supply VR is stopped, and the transistor 3
7 remains off. As a result, the output terminal bar Q of the FF 17 is set to the H level.

When the judgment signal S7 of the OR circuit 9a is at L level, a current flows from the power supply VR through the resistor 38, the diode 33 and the resistor 32 of the OR circuit 9a, and no current flows through the base of the transistor 36. . Therefore, the transistor 36 is turned off, and the capacitor 20 of the reset circuit 18 is charged. When the capacitor 20 is completely charged, the transistor 37 is turned on. As a result, the output terminal bar Q of the FF 17 is set to the L level.

At this time, the determination signal S7 changes from L level to H level.
Even if the transistor 36 is turned on and the transistor 36 is turned on, the capacitor 20 of the reset circuit 18 is charged with electric charge, and therefore the transistor 37 remains on. As a result, the output terminal bar Q of the FF 17 remains in the L level.

Therefore, the NAND circuit 8 outputs the drive signal S1 based on the control signal S3 to the transistor 5 when the output terminal bar Q is at the H level. Also, NAND
When the output terminal bar Q is at L level, the circuit 8 cuts off the control signal S3 and outputs at H level, that is, the drive signal S1 for turning off the transistor 5, to the transistor 5.

Next, the operation of the load drive circuit 1a configured as described above will be described. As a basic operation, each power supply VC
When the power is turned on from C and VR, the capacitor 20 of the reset circuit 18 starts to be charged. When the control signal S3 from the control input circuit unit 4 is at the L level, the transistor 29 of the delay inverting circuit 10a is on, so the delay inverting signal S8 from the delay inverting circuit 10a.
Is at the H level. Therefore, the determination signal S7 of the OR circuit 9a becomes H level.

A current flows from the power supply VR to the base of the transistor 36 of the FF 17 through the resistor 38 and the diode 34. Therefore, the transistor 36 is turned on. Then, the charging of the capacitor 20 from the power source VR is stopped, and the transistor 37 remains in the off state. As a result, the FF 17 is reset and the output terminal bar Q is set to the H level.

By setting the output terminal bar Q of the FF 17 to the H level, the NAND circuit 8 drives the drive signal S based only on the control signal S3 from the control input circuit section 4.
1 is output to the base of the transistor 5. Therefore, the transistor 5 is turned on / off based only on the control signal S3.

On the contrary, when the control signal S3 from the control input circuit section 4 is at H level, the transistor 5 of the output circuit 2
Is on. However, although the transistor 5 is turned on, the load Z may cause a short circuit or the like and the detection signal S2 remains at the L level. At this time, since the transistor 29 of the delay inverting circuit 10a is off, the delay inverting signal S8 from the delay inverting circuit 10a is at L level. Therefore, the determination signal S7 of the OR circuit 9a becomes L level. When the determination signal S7 is at L level, a current flows from the power supply VR through the resistor 38, the diode 33 and the resistor 32 of the OR circuit 9a, and no current flows through the base of the transistor 36. Therefore, the transistor 36 is turned off, and the capacitor 20 of the reset circuit 18 is charged. When the capacitor 20 is completely charged, the transistor 37 is turned on. As a result, the output terminal bar Q of the FF 17 is set to the L level.

At this time, the determination signal S7 changes from L level to H level.
Even when the level becomes the level, the connection point N3 is at the L level and the transistor 36 is off, so the transistor 37 remains on. As a result, the output terminal bar Q of FF17
Holds the L level. And FF
This set state is held until 17 is reset. That is, it is held until the power supply VR is turned off. By setting the output terminal bar Q of the FF 17 to the L level, the NAND circuit 8 continues to output the L level drive signal S1 to the transistor 5 regardless of the control signal S3 from the control input circuit unit 4.

Here, regarding the operation of the control circuit section 3a,
It will be described with reference to the timing charts of FIGS. First, a case where the output terminals P1 and P2 are not short-circuited and are in a normal state will be described with reference to FIG. When the control signal S3 of the control input circuit unit 4 is L level, the FF 17 sets the output terminal bar Q to H level as described above.

Here, when the control signal S3 changes from the L level to the H level, the FF 17 sets the output terminal bar Q to the H level, so that the transistor VR is connected from the power supply VR of the NAND circuit 8 via the resistor 26 and the diode 22. A current flows through the base of 24. Transistor 24 turns on and NA
The drive signal S1 of the ND circuit 8 becomes L level. And
The L-level drive signal S1 is input to the base of the transistor 5 of the output circuit unit 2. Therefore, the transistor 5 is turned on, so that the detection signal S2 at the output terminal P1 becomes H level after the delay time T3 elapses.

Further, the transistor 2 of the delay inverting circuit 10a
Since 9 is turned off, the delayed inverted signal S8 becomes L level after the delay time T1 has elapsed. However, since it is quicker for the detection signal S2 to reach the H level, the determination signal S7 of the OR circuit 9a is maintained at the H level. Therefore, the transistor 36 of the FF 17 is held in the on state and the transistor 37 is held in the off state. That is, the output terminal bar Q of the FF 17 is held at the H level.

On the contrary, when the control signal S3 changes from the H level to the L level, the transistor 29 is turned on and the delay inversion signal S8 becomes the H level after the delay time T2 elapses. Also, N
Since no current flows through the base of the transistor 24 of the AND circuit 8, the transistor 24 is turned off and the drive signal S1 becomes H level. The H-level drive signal S1 is input to the base of the transistor 5 of the output circuit unit 2. Therefore, the transistor 5 is turned off, and the detection signal S2 becomes L level after the lapse of the delay time T3. However, since it is quicker for the delayed inverted signal S8 to be at the H level,
The determination signal S7 of the OR circuit 9a is held at H level.
Therefore, similarly to the above, the output terminal bar Q of the FF 17 is H level.
Hold on to the level.

Next, the case where the output terminals P1 and P2 are short-circuited from the beginning will be described with reference to FIG. When the control signal S3 is at L level, the output terminal bar Q of the FF 17 is set at H level as described above.

Here, when the control signal S3 changes from the L level to the H level, the transistor 29 is turned off, so that the delay inversion signal S8 becomes the L level after the lapse of the delay time T1.
If it is normal, the detection signal S2 becomes H earlier than that.
Although it is at the level, the detection signal S2 remains at the L level because the output terminals P1 and P2 are short-circuited.

Therefore, when the delayed inverted signal S8 becomes L level, the determination signal S7 of the OR circuit 9a becomes L level. Therefore, the current from the power supply VR flowing to the base of the transistor 36 of the FF 17 flows through the resistor 38, the diode 33, and the resistor 32. Therefore, the transistor 36 is turned off and the capacitor 20 which has been discharged is discharged.
Are charged via the resistor 19. Then, after charging the capacitor 20, that is, after the lapse of the delay time T5, the base of the transistor 37 changes from the L level to the H level. Then, the transistor 37 turns on after the lapse of the delay time T5.

Therefore, the output terminal bar Q of the FF 17 is set to the L level, and the NAND circuit 8 and the transistors 24 and 5 of the output circuit section 2 are turned off. Further, since each of the transistors 36 and 37 of the FF 17 holds this state, it continues until the power is turned off. In this state, even if the control signal S3 is once set to the L level and then set to the H level again, the transistors 24 and 5 remain off.

Next, when the load Z is normally driven,
A case where a short circuit occurs between the output terminals P1 and P2 on the way will be described with reference to FIG. When the load Z is normally driven, the delayed inversion signal S8 is at L level. or,
The detection signal S2 is at H level, and the determination signal S7 of the OR circuit 9a is at H level.

Here, when the output terminals P1 and P2 are short-circuited, the detection signal S2 becomes L level, and the OR circuit 9a.
The determination signal S7 of becomes the L level. Therefore, FF17
The transistor 36 is turned off, and the discharged capacitor 20 is charged via the resistor 19. After charging the capacitor 20, that is, after the delay time T5 has elapsed,
The base of the transistor 37 changes from L level to H level. Then, the transistor 37 turns on after the lapse of the delay time T5.

Accordingly, the output terminal bar Q of the FF 17 is set to the L level, and the NAND circuit 8 and the transistors 24 and 5 of the output circuit section 2 are turned off. Further, since each of the transistors 36 and 37 of the FF 17 holds this state, it continues until the power is turned off. In this state, even if the control signal S3 is once set to the L level and then set to the H level again, the transistors 24 and 5 remain off.

As described above, according to this embodiment,
In addition to the features of the first embodiment, the following features are provided. (1) Paying attention to the fact that the off time is longer than the on time of each transistor 5, 24, 29.
By configuring a, it is possible to combine the operations of both the inverting circuit 10 and the delay circuit 11 of the first embodiment, so that a simpler and cheaper circuit configuration can be achieved, leading to cost reduction.

The present invention may be modified as follows, and in that case, the same operation and effect can be obtained. (1) In each of the above embodiments, a circuit configuration using a transistor as a switching element is used, but a circuit configuration using another switching element may be used. For example, Mo
s-transistor, IGBT (Insulated Ga)
te Bipolar Transistor) or the like.

(2) Although the NAND circuit 8, the NOT circuits 10 and 13 and the OR circuit 9 are used in the first embodiment, the circuit structure may be unified in one logic circuit.

[0093]

As described above in detail, according to the present invention, it is possible to provide a load drive circuit which can prevent thermal damage to an output transistor due to overcurrent with a simple circuit configuration without using a microcomputer. it can.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a load drive circuit according to a first embodiment.

2A, 2B, and 2C are timing charts in each case.

FIG. 3 is a circuit diagram of a load drive circuit according to a second embodiment.

4A, 4B, and 4C are timing charts in each case.

FIG. 5 is a circuit diagram of a load drive circuit according to a conventional technique.

FIG. 6 is a circuit diagram of another load driving circuit in the related art.

FIG. 7 is a circuit diagram of another load driving circuit in the related art.

[Explanation of symbols]

5 ... Output transistor, 8 ... NAND as control circuit
Circuit, 9, 9a ... OR circuit as decision circuit, 10a ...
Delay inversion circuit as delay signal generation unit, 11 ... Delay circuit, 12 ... Storage circuit as holding circuit, 24, 29 ... Transistor, S2, S3, S6, S7, S8 ... Signal, V
CC ... Power supply, Z ... Load.

Claims (3)

[Claims] 1. An output transistor (5) is controlled based on an input signal (S3), and a power supply (VCC) is supplied to the load (Z) via the transistor (5) to drive the load (Z). In the load drive circuit, a delay circuit (11) that delays and outputs the input signal (S3), a signal (S6) from the delay circuit (11), and a detection signal that detects a short circuit of the load (Z). (S2) as an input and a determination circuit (9) that outputs a determination signal (S7) based on those signals (S6, S2) and a determination signal (S7) output from the determination circuit (9). And a control circuit (8) for controlling the output transistor (5) to be turned off based on the load drive circuit. 2. An output transistor (5) is controlled based on an input signal (S3), and a power supply (VCC) is supplied to the load (Z) via the transistor (5) to drive the load (Z). In the load drive circuit, a delay circuit (11) that delays and outputs the input signal (S3), the input signal (S3), the signal (S6) from the delay circuit (11), and the load (Z ) And the detection signal (S2) that detects the short circuit of
6, S2), a determination circuit (9) for outputting a determination signal (S7), a holding circuit (12) for holding the determination signal (S7) output from the determination circuit (9), and the holding circuit. A load drive circuit comprising: a control circuit (8) for controlling the output transistor (5) to be turned off based on the holding state of (12). 3. An output transistor (5) is controlled based on an input signal (S3), and a power supply (VCC) is supplied to the load (Z) via the transistor (5) to drive the load (Z). In the load driving circuit, a first transistor (29) to which the input signal (S3) is input to its base terminal, and an output signal (S) from the first transistor (29).
8) and a detection signal (S2) which detects the short circuit of the load (Z), and outputs a determination signal (S7) based on these signals (S8, S2) (9a).
And a determination signal (S7) output from the determination circuit (9a)
A holding circuit (12) for holding and a base terminal of the output transistor (5),
Controlled based on the holding state of the holding circuit (12),
A second transistor (24) for controlling the output transistor (5) to be turned off. The on / off time of the first and second transistors (29, 24) and the output transistor (5) causes A load drive circuit including a delay signal generation unit (10a) for delaying an input signal (S3) and inputting the delayed signal to the determination circuit (9a).