JPH09214700A - Photoelectric converter and multichip type integrated circuit - Google Patents

Photoelectric converter and multichip type integrated circuit

Info

Publication number
JPH09214700A
JPH09214700A JP8013960A JP1396096A JPH09214700A JP H09214700 A JPH09214700 A JP H09214700A JP 8013960 A JP8013960 A JP 8013960A JP 1396096 A JP1396096 A JP 1396096A JP H09214700 A JPH09214700 A JP H09214700A
Authority
JP
Japan
Prior art keywords
chip
photoelectric conversion
output
circuit
gain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8013960A
Other languages
Japanese (ja)
Inventor
Takao Koide
能男 小出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP8013960A priority Critical patent/JPH09214700A/en
Publication of JPH09214700A publication Critical patent/JPH09214700A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To reduce the photoelectric conversion sensitivity difference of each chip in a multichip type photoelectric converter. SOLUTION: In the photoelectric converter composed by arranging many photoelectric conversion elements and arranging plural of image sensor chips 1 to n having scanning circuits for successively reading optical signals and output processing circuits for outputting read signals to the outside, each image sensor chip 1 to n makes it possible to perform more than two different settings including a set value in the gain setting of the output circuit. This setting is set through the output of a control circuit in which the pad taken out to the outside is made an input. In a multichip type integrated circuit, the output circuit which is arranged within a chip for every chip and is possible to perform a gain setting is provided. The photoelectric conversion sensitivity of the chip is compared with the photoelectric conversion sensitivity of other chips and the output level of the chip is made almost the same as the output levels of other chips.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、光電変換装置及び
マルチチップ型集積回路に関し、特にチップ毎の光電変
換効率を均一化できるチップを複数個配置した光電変換
装置及びマルチチップ型集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device and a multi-chip type integrated circuit, and more particularly to a photoelectric conversion device and a multi-chip type integrated circuit in which a plurality of chips capable of equalizing photoelectric conversion efficiency for each chip are arranged.

【0002】[0002]

【従来の技術】光電変換素子としては一般にCCD型,
MOS型及び増幅型等があり、CCD型では読み取った
光電変換の電荷を順次転送して画像信号とする一方、M
OS型はMOSトランジスタのゲートに光電変換の電荷
を蓄積し、その電荷の変化を外部へ電荷増幅して出力す
る。この光電変換装置には、光学系の方式差として縮小
系の光学系と等倍系の光学系を用いる2方式が存在す
る。等倍系の光電変換装置は、半導体の結晶から1枚の
ウェハを取り出し、このウェハに複数工程を加えて光電
変換素子と周辺回路のチップを複数個形成し、このチッ
プを例えば1ライン状に配置して、マルチチップ型ライ
ンセンサーとして形成する。
2. Description of the Related Art As a photoelectric conversion element, a CCD type is generally used.
There are a MOS type and an amplification type. In the CCD type, the read photoelectric conversion charges are sequentially transferred to form an image signal, while M
In the OS type, photoelectric conversion charges are accumulated in the gate of the MOS transistor, and the change in the charges is amplified and output to the outside. In this photoelectric conversion device, there are two methods that use a reduction-type optical system and an equal-magnification optical system as the difference in the optical system. In a unity-scale photoelectric conversion device, one wafer is taken out from a semiconductor crystal, and a plurality of steps are added to this wafer to form a plurality of photoelectric conversion elements and peripheral circuit chips. The chips are formed into, for example, one line. Arranged and formed as a multi-chip type line sensor.

【0003】一方、縮小系の光電変換装置は、ワンチッ
プの大きさに対象物をレンズで縮小して画像信号を得
て、レンズの歪みや光電変換素子毎の感度差を補正する
ためにシェーディング補正を行っていた。しかし、装置
が大きくなると共に、シェーディング補正だけでは均一
な画像信号を得ることが困難であった。そこで近年は装
置の小型化のためと光学的に直接画像信号を読み出せる
マルチチップ化が望まれていた。しかし、半導体ウェハ
の大きさは6〜8インチが主流であり、例えばA4サイ
ズの21cmを直接読み出せる光電変換用チップを形成
することは困難であり、複数のチップを従属接続するこ
とで、対応する傾向にある。例えば半導体ウェハの大き
さが12インチであっても、ウェハの使用効率の点から
マルチチップとするほうがよい。
On the other hand, a reduction-type photoelectric conversion device reduces an object to a size of one chip with a lens to obtain an image signal, and shading is performed to correct the distortion of the lens and the difference in sensitivity between photoelectric conversion elements. I was making corrections. However, as the apparatus becomes larger, it is difficult to obtain a uniform image signal only by shading correction. Therefore, in recent years, in order to reduce the size of the device, a multi-chip structure that can directly read the image signal optically has been desired. However, the size of the semiconductor wafer is generally 6 to 8 inches, and it is difficult to form a photoelectric conversion chip that can directly read, for example, 21 cm of A4 size, and it is possible to deal with it by connecting a plurality of chips in cascade. Tend to do. For example, even if the size of the semiconductor wafer is 12 inches, it is better to use multiple chips in terms of wafer usage efficiency.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、対象画
像を直接読み込むために光電変換用チップを複数個直線
上に配置して光学的に等倍系とするマルチチップ型/密
着型イメージセンサの光電変換装置とすれば、個々のチ
ップ毎の光電変換感度差が問題となる。従って本発明は
個々のチップの光電変換感度差を減少することを課題と
する。
However, the photoelectric conversion of a multi-chip type / contact type image sensor in which a plurality of photoelectric conversion chips are arranged in a straight line to directly read the target image and optically becomes an equal magnification system. In the case of a device, a difference in photoelectric conversion sensitivity between individual chips becomes a problem. Therefore, it is an object of the present invention to reduce the difference in photoelectric conversion sensitivity between individual chips.

【0005】マルチチップ型イメージセンサでは、各々
のチップの光電変換感度差(感度バラツキ)がセンサ全
体としての感度バラツキを決定する。従って、各々のチ
ップの感度バラツキは小さいことが望ましい。そこで、
半導体ウェハのプロセス処理のバラツキ等によって発生
する感度バラツキがある程度予測できれば、センサ内部
の信号処理系の出力ゲインを調節することで、各チップ
の相対的な感度を近づけることが可能となる。本発明は
この方法の一手段を提供する。
In the multi-chip type image sensor, the photoelectric conversion sensitivity difference (sensitivity variation) of each chip determines the sensitivity variation of the entire sensor. Therefore, it is desirable that the variations in sensitivity among the chips are small. Therefore,
If the variation in sensitivity caused by the variation in process processing of the semiconductor wafer can be predicted to some extent, the relative sensitivity of each chip can be made closer by adjusting the output gain of the signal processing system inside the sensor. The present invention provides one means of this method.

【0006】[0006]

【課題を解決する手段】本発明は、上記課題を解決する
ために成されたもので、光電変換素子を多数配置し、光
信号を順次読み出すための走査回路と、読み出された信
号を外部へ出力するための出力処理回路とを有するイメ
ージセンサチップを複数配置して構成される光電変換装
置において、前記各イメージセンサチップはその出力回
路のゲイン設定が設定値を含めて2つ以上の異なる設定
が可能であり、この設定は外部に取り出されたチップ内
のI/Oパッドを入力とする制御回路の出力を通して設
定されることを特徴とする。
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. A large number of photoelectric conversion elements are arranged and a scanning circuit for sequentially reading optical signals, and a read signal are externally read. In a photoelectric conversion device configured by arranging a plurality of image sensor chips each having an output processing circuit for outputting to each of the image sensor chips, the gain setting of the output circuit of each image sensor chip is different by two or more including a set value. The setting is possible, and this setting is characterized in that it is set through the output of the control circuit having the I / O pad in the chip taken out to the input as an input.

【0007】また、光電変換素子を複数配置したチップ
を複数個配置したマルチチップ型集積回路において、前
記チップ毎にチップ内に配置したゲイン設定可能な増幅
回路と、当該チップの光電変換利得を他のチップの光電
変換利得と比較して各チップの出力レベルを一定とする
ように前記増幅回路のゲインを設定することを特徴とす
る。
Further, in a multi-chip type integrated circuit in which a plurality of chips in which a plurality of photoelectric conversion elements are arranged are arranged, a gain setting amplifier circuit arranged in each chip and a photoelectric conversion gain of the chip are The gain of the amplifier circuit is set so that the output level of each chip is constant compared with the photoelectric conversion gain of the chip.

【0008】[0008]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

(第1の実施形態)図1は本発明によるマルチチップ型
光電変換装置の概念的ブロック図を示す。1,2,……
nは光電変換素子を含むセンサチップを示す。各センサ
チップ1,2,……nには、対象画像を電気信号に変換
する光電変換素子1−1,2−1,……n−1と、外部
からの指示信号を入力しその指示信号をデコードして所
定の制御電圧を出力するデコーダ回路1−2,2−2,
……n−2と、光電変換素子1−1,2−1,……n−
1の読み出し信号を制御電圧に従った増幅率で出力する
出力回路1−3,2−3,……n−3と、デコーダ回路
2の制御電圧とその制御電圧を出力回路1−3,2−
3,……n−3のゲイン設定を行なうデコーダ出力線1
−4,2−4,……n−4と、光電変換素子1の各素子
の出力を所定の時間で時系列的に読み出す読み出し走査
回路1−5,2−5,……n−5と、外部からデコーダ
回路1−2,2−2,……n−2へ指示信号を入力する
入力端子パッド1−6,2−6,……n−6とを含んで
いる。従って、センサチップ1,2,……nは、各ウェ
ハの状態で半導体プロセス技術によって上記各回路を搭
載し、各チップに分割して光電変換素子1−1,2−
1,……n−1を一直線に配置する。この配置手段は、
各光電変換素子1−1,2−1,……n−1の両端末で
隣接素子と極近接して組み立てられる。
(First Embodiment) FIG. 1 is a conceptual block diagram of a multi-chip type photoelectric conversion device according to the present invention. 1, 2, ...
n represents a sensor chip including a photoelectric conversion element. Photon conversion elements 1-1, 2-1, ... N-1 for converting the target image into an electric signal and an instruction signal from the outside are input to each of the sensor chips 1, 2 ,. Decoder circuit 1-2, 2-2, which decodes the signal and outputs a predetermined control voltage
... n-2 and photoelectric conversion elements 1-1, 2-1, ... n-
N-3, which outputs the read signal of No. 1 at an amplification factor according to the control voltage, and the control voltage of the decoder circuit 2 and the control voltage thereof are output circuits 1-3, 2 −
Decoder output line 1 for setting gain of 3, ... n-3
-4, 2-4, ... n-4, and read scanning circuits 1-5,2-5, ... n-5 for reading out the output of each element of the photoelectric conversion element 1 in a time series in a predetermined time. , And input terminal pads 1-6, 2-6, ... N-6 for inputting an instruction signal to the decoder circuits 1-2, 2-2 ,. Therefore, each of the sensor chips 1, 2, ...
1, ... Arrange n-1 in a straight line. This arrangement means
Each photoelectric conversion element 1-1, 2-1, ... N-1 is assembled in close proximity to an adjacent element.

【0009】次に、上記出力回路1−3,2−3,……
n−3の具体的回路図を図2、図3に示す。図2は正転
出力型出力回路を示し、21はMOSタイプ又はバイポ
ーラ形式の演算増幅器、22,23はスイッチであり、
MOSタイプであればゲートにデコーダ回路1−2,2
−2,……n−2からの制御電圧を供給し主電極である
ソース/ドレイン間をオン/オフして出力回路1−3,
2−3,……n−3のゲインを制御する。24〜26は
抵抗である。こうして、この出力回路1−3,2−3,
……n−3の出力ゲインGAはスイッチSW1(22)
がオンで、スイッチSW2(23)がオフの場合に、 ゲインGA1={1+(R2+R3)/R1} ……(1) また、スイッチSW1(22)がオフで、スイッチSW
2(23)がオンの場合に、 ゲインGA2={1+R3/R1} ……(2) となり、外部のデコーダからの制御信号によって2種の
ゲインが得られる。
Next, the output circuits 1-3, 2-3, ...
Specific circuit diagrams of n-3 are shown in FIGS. FIG. 2 shows a normal output type output circuit, 21 is a MOS type or bipolar type operational amplifier, 22 and 23 are switches,
If it is a MOS type, it has decoder circuits 1-2 and 2 at the gate.
-2, ... Output circuit 1-3 by supplying control voltage from n-2 and turning on / off between the source / drain which is the main electrode
2-3, ... Controls the gain of n-3. 24-26 are resistors. Thus, the output circuits 1-3, 2-3,
The output gain GA of n-3 is the switch SW1 (22).
Is on and the switch SW2 (23) is off, the gain GA1 = {1+ (R2 + R3) / R1} (1) Also, the switch SW1 (22) is off and the switch SW
When 2 (23) is on, gain GA2 = {1 + R3 / R1} (2), and two types of gain are obtained by the control signal from the external decoder.

【0010】図3は差動出力形式の出力回路を示し、3
1は一方の入力を信号成分とし他方の入力をノイズ成分
とする差動演算増幅器、32〜35はスイッチであり、
一般にMOSタイプで構成され、各スイッチのゲートに
デコーダ回路1−2,2−2,……n−2から4種の制
御電圧を供給し主電極であるソース/ドレイン間をオン
/オフして出力回路1−3,2−3,……n−3のゲイ
ンを制御する。36〜41は抵抗である。この構成によ
る出力回路1−3,2−3,……n−3のゲインGB
は、抵抗R1=R4,R2=R5,R3=R6として、スイッ
チSW1(32),SW2(33)がオンで、スイッチ
SW3(34),SW4(35)がオフの場合、 ゲインGB1=(R2+R3)/R1 ……(3) スイッチSW1(32),SW2(33)がオフで、ス
イッチSW3(34),SW4(35)がオンの場合、 ゲインGB2=R3/(R2+R1) ……(4) となり、信号成分に含まれるノイズ成分からノイズ成分
を差し引いて、残りの信号成分だけを所定のゲインで増
幅された出力信号を得ることができる。
FIG. 3 shows a differential output type output circuit.
1 is a differential operational amplifier having one input as a signal component and the other input as a noise component, and 32 to 35 are switches,
Generally, it is composed of a MOS type and supplies four kinds of control voltages from the decoder circuits 1-2, 2-2, ..., N-2 to the gate of each switch to turn on / off between the source / drain which is the main electrode. The gain of the output circuits 1-3, 2-3, ... N-3 is controlled. 36 to 41 are resistors. The gain GB of the output circuits 1-3, 2-3, ...
When the switches SW1 (32) and SW2 (33) are on and the switches SW3 (34) and SW4 (35) are off with the resistors R1 = R4, R2 = R5, R3 = R6, the gain GB1 = (R2 + R3 ) / R1 (3) When the switches SW1 (32) and SW2 (33) are off and the switches SW3 (34) and SW4 (35) are on, the gain GB2 = R3 / (R2 + R1) (4) Therefore, the noise component is subtracted from the noise component included in the signal component, and it is possible to obtain an output signal in which only the remaining signal component is amplified with a predetermined gain.

【0011】図4はイメージセンサの各チップの感度分
布を示した特性図である。(1)ウェハ状態で各チップ
の光電変換感度を測定し、(2)各チップをどのゲイン
設定にするのかを決定し、(3)各チップの感度のデー
タを用いて各チップを所定の基板上に配置する時点で外
部パッドに供給する指定信号を所定の制御信号として出
力回路1−3,2−3,……n−3のゲインを得る。
FIG. 4 is a characteristic diagram showing the sensitivity distribution of each chip of the image sensor. (1) The photoelectric conversion sensitivity of each chip is measured in a wafer state, (2) which gain setting is to be set for each chip, and (3) the sensitivity data of each chip is used to make each chip a predetermined substrate. The gain of the output circuits 1-3, 2-3, ..., N-3 is obtained by using the designation signal supplied to the external pad as a predetermined control signal at the time of arranging it above.

【0012】そうすれば、例えば出力回路1−3,2−
3,……n−3のゲインの設定を、基準とプラスとマイ
ナスの3設定として、図4に示す斜線部11,22の部
分のチップを感度補正を行って、感度分布の中心付近に
集中して、各チップの出力レベルをほぼ一定とすること
ができる。
Then, for example, the output circuits 1-3 and 2-
3, ... Setting the gain of n-3 to three, plus and minus, the chips in the shaded areas 11 and 22 shown in FIG. 4 are subjected to sensitivity correction and concentrated near the center of the sensitivity distribution. Then, the output level of each chip can be made almost constant.

【0013】図5はスイッチ23,24,…の状態で3
種以上のゲインを獲得できる正転増幅器の出力回路1−
3,2−3,……n−3の回路図である。また、図6は
スイッチ32,33とスイッチ34,35とをそれぞれ
ペアー動作とし、各スイッチの状態で3種のゲインを獲
得できる差動増幅器の出力回路1−3,2−3,……n
−3の回路図である。
FIG. 5 shows the state of the switches 23, 24, ...
Output circuit of a non-inverting amplifier that can obtain more than one gain 1-
It is a circuit diagram of 3,2-3, ... n-3. Further, in FIG. 6, the switches 32, 33 and the switches 34, 35 are pair-operated, respectively, and the output circuits 1-3, 2-3, ...
It is a circuit diagram of -3.

【0014】ここで、図1のマルチチップ光電変換装置
の出力回路1−3,2−3,……n−3に、図5の出力
回路を用いた場合の動作について説明する。各チップの
光電変換素子の感度をウェハの状態で別途設けた感度測
定装置によって感度のバラツキが図4に示す領域のどの
部分に該当するかを判断し、そのチップが例えば11の
領域であればプラスとなる図5の出力回路の最大ゲイン
となるスイッチをオンとし、また例えば22の領域であ
ればマイナスとなる図5の出力回路の最小ゲインとなる
スイッチをオンとし、また例えば33の領域であれば基
準となる図5の出力回路の基準ゲインとなるスイッチを
オンして、図4の基準領域33,44の出力レベルとな
るように設定する。基板上にマルチチップを形成した後
は、外部指示信号をデコーダによって各スイッチに所定
の制御電圧を供給して各チップ上の出力回路1−3,2
−3,……n−3のゲインをウェハ時点で設定されたゲ
インとして各チップの出力レベルをほぼ一定にすること
ができる。
The operation when the output circuit of FIG. 5 is used for the output circuits 1-3, 2-3, ... N-3 of the multi-chip photoelectric conversion device of FIG. 1 will be described. The sensitivity of the photoelectric conversion element of each chip is determined in a wafer state by a separately provided sensitivity measuring device to determine which part of the area shown in FIG. 4 the variation in sensitivity corresponds to. The switch with the maximum gain of the output circuit of FIG. 5 that is positive is turned on, and the switch with the minimum gain of the output circuit of FIG. 5 that is negative is turned on in the region of 22 and, for example, in the region of 33. If so, the switch serving as the reference gain of the output circuit of FIG. 5 serving as the reference is turned on, and the output levels of the reference regions 33 and 44 of FIG. 4 are set. After forming the multi-chip on the substrate, the decoder is supplied with an external instruction signal to supply a predetermined control voltage to each switch to output circuits 1-3, 2 on each chip.
The output level of each chip can be made almost constant by setting the gain of -3, ..., N-3 as the gain set at the time of wafer.

【0015】次に、図1のマルチチップ光電変換装置の
出力回路1−3,2−3,……n−3に図6の差動増幅
型の出力回路を用いた場合の動作については、光電変換
素子をリセットした直後に素子のノイズレベルを検出し
て、ノイズ入力端子に入力し、次に対象物に対して所定
時間露光した後に正規に光電変換された画像信号を信号
入力端子に入力して、画像信号に含まれるノイズ成分を
除去すると共に、他のチップの出力レベルと整合する増
幅度に設定できるスイッチをオンして増幅し、当該チッ
プの画像信号の出力を得ることができる。
Next, the operation when the differential amplifier type output circuit of FIG. 6 is used for the output circuits 1-3, 2-3, ... N-3 of the multi-chip photoelectric conversion device of FIG. Immediately after resetting the photoelectric conversion element, the noise level of the element is detected and input to the noise input terminal, then the image signal that has been photoelectrically converted to normal is input to the signal input terminal after the object is exposed for a predetermined time. Then, the noise component included in the image signal is removed, and a switch capable of setting an amplification degree that matches the output level of another chip is turned on to perform amplification to obtain the output of the image signal of the chip.

【0016】なお、上記実施形態では、各チップの光電
変換感度のバラツキを4つに分けた例を示したが、2つ
以上に分けることも可能であり、そのバラツキに応じて
多数の領域にわけてその分割領域数に応じた出力回路の
設定ゲイン数を増加することも可能であり、現実的に
は、ウェハの状態で測定した各チップの感度差に応じて
出力回路のゲインを各種設定して各チップ毎の出力レベ
ルのバラツキを小さくすることが可能である。
In the above embodiment, the variation of the photoelectric conversion sensitivity of each chip is divided into four, but it can be divided into two or more, and a large number of areas can be formed in accordance with the variation. Therefore, it is possible to increase the number of gains of the output circuit set according to the number of divided areas.In reality, various gains of the output circuit can be set according to the sensitivity difference of each chip measured in the wafer state. Therefore, it is possible to reduce variations in the output level of each chip.

【0017】また、各チップ内の素子出力レベルのバラ
ツキに関しては、出力回路内にシェーディング補正回路
を内蔵しても良いし、マルチチップとしての出力からタ
イムリーにAGC回路等を施してシェーディング補正を
行ってもよい。
Regarding the variation of the element output level in each chip, a shading correction circuit may be built in the output circuit, or shading correction may be performed by timely applying an AGC circuit or the like from the output as a multi-chip. You can go.

【0018】更に、上記実施態様では、その出力回路に
正転増幅型と差動増幅型の例を示したが、反転増幅型の
出力回路を用いてもよく、他のチップの出力回路と合わ
せて、チップ毎の出力レベルのバラツキを減少し得るゲ
イン設定を可能とすれば、位相差や遅延時間の差異は現
実的に問題ないので、いかなる出力回路でもよい。例え
ば、単に抵抗によるアッテネータを設けて、スイッチ回
路で減衰度を調節・設定できれば、本発明の課題を達す
ることも可能である。ただし、出力回路の出力のS/N
は高いことが望ましいので、増幅型のほうが好ましい。
Further, in the above-mentioned embodiment, the output circuit of the normal amplification type and the differential amplification type is shown. However, an inverting amplification type output circuit may be used, and it may be combined with the output circuits of other chips. Then, if it is possible to set the gain that can reduce the variation of the output level for each chip, the difference in the phase difference and the delay time is practically no problem, so any output circuit may be used. For example, the object of the present invention can be achieved by simply providing an attenuator with a resistor and adjusting / setting the attenuation degree with a switch circuit. However, the S / N of the output of the output circuit
Is desirable, so that the amplified type is preferable.

【0019】[0019]

【発明の効果】以上説明したように、本発明によるマル
チチップ型の光電変換装置及び半導体集積回路によれ
ば、多数配置されたマルチチップの各チップの光電変換
出力のレベルをほぼ同一にできるので、個々のチップの
光電変換感度差を減少することができる。
As described above, according to the multi-chip type photoelectric conversion device and the semiconductor integrated circuit of the present invention, the levels of the photoelectric conversion outputs of the multi-chips arranged in large numbers can be made substantially the same. , The difference in photoelectric conversion sensitivity between individual chips can be reduced.

【0020】また、ウェハ状態で各チップの感度差を測
定して各チップ毎に出力回路のゲインを設定するので、
各チップの縦列接続に何の制約もなく、ウェハの使用効
率を向上することができる。
Since the sensitivity difference of each chip is measured in the wafer state and the gain of the output circuit is set for each chip,
There is no restriction on the cascade connection of each chip, and the wafer use efficiency can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるマルチチップ型の光電変換装置の
回路図である。
FIG. 1 is a circuit diagram of a multi-chip type photoelectric conversion device according to the present invention.

【図2】本発明による光電変換装置の出力回路の回路図
である。
FIG. 2 is a circuit diagram of an output circuit of a photoelectric conversion device according to the present invention.

【図3】本発明による光電変換装置の出力回路の回路図
である。
FIG. 3 is a circuit diagram of an output circuit of the photoelectric conversion device according to the present invention.

【図4】本発明によるマルチチップの感度バラツキの分
布図である。
FIG. 4 is a distribution diagram of sensitivity variations of a multi-chip according to the present invention.

【図5】本発明による光電変換装置の出力回路の回路図
である。
FIG. 5 is a circuit diagram of an output circuit of the photoelectric conversion device according to the present invention.

【図6】本発明による光電変換装置の出力回路の回路図
である。
FIG. 6 is a circuit diagram of an output circuit of the photoelectric conversion device according to the present invention.

【符号の説明】[Explanation of symbols]

1〜n センサチップ 1−1,2−1,……n−1 光電変換素子 1−2,2−2,……n−2 デコーダ回路 1−3,2〜3,……n−3 出力回路 1−4,2−4,……n−4 デコーダ出力線 1−5,2−5,……n−5 読み出し走査回路 1−6,2−6,……n−6 デコーダ入力端子パッド m 共通出力線 1-n sensor chip 1-1,2-1, ... n-1 photoelectric conversion element 1-2,2-2, ... n-2 decoder circuit 1-3,2-3, ... n-3 output Circuit 1-4, 2-4, ... n-4 Decoder output line 1-5,2-5, ... n-5 Read-out scanning circuit 1-6,2-6, ... n-6 Decoder input terminal pad m Common output line

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H04N 5/335 H04N 1/40 101B ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 6 Identification code Internal reference number FI Technical display location H04N 5/335 H04N 1/40 101B

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 光電変換素子を多数配置し、光信号を順
次読み出すための走査回路と、読み出された信号を外部
へ出力するための出力処理回路とを有するイメージセン
サチップを複数個配置して構成される光電変換装置にお
いて、 前記各イメージセンサチップはその出力回路のゲイン設
定が設定値を含めて2つ以上の異なる設定が可能であ
り、この設定は各チップ内のI/Oパッドを入力とする
制御回路の出力を通して設定されることを特徴とする光
電変換装置。
1. A plurality of photoelectric conversion elements are arranged, and a plurality of image sensor chips each having a scanning circuit for sequentially reading optical signals and an output processing circuit for outputting the read signals are arranged. In the photoelectric conversion device configured as described above, the gain setting of the output circuit of each of the image sensor chips can be set to two or more different settings including the set value, and this setting is performed by setting the I / O pad in each chip. A photoelectric conversion device, which is set through an output of a control circuit which is an input.
【請求項2】 光電変換素子を多数配置したチップを複
数個配置したマルチチップ型集積回路において、 前記チップ毎にチップ内に配置したゲイン設定可能な出
力回路を備え、当該チップの光電変換感度を他のチップ
の光電変換感度と比較して当該チップの出力レベルを他
のチップの出力レベルとほぼ同一となるように前記出力
回路のゲインを設定することを特徴とするマルチチップ
型集積回路。
2. A multi-chip type integrated circuit having a plurality of chips having a large number of photoelectric conversion elements arranged therein, wherein each chip is provided with an output circuit capable of setting a gain and the photoelectric conversion sensitivity of the chip is increased. A multi-chip type integrated circuit characterized in that the gain of the output circuit is set so that the output level of the chip is substantially the same as the output level of the other chip as compared with the photoelectric conversion sensitivity of the other chip.
JP8013960A 1996-01-30 1996-01-30 Photoelectric converter and multichip type integrated circuit Pending JPH09214700A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8013960A JPH09214700A (en) 1996-01-30 1996-01-30 Photoelectric converter and multichip type integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8013960A JPH09214700A (en) 1996-01-30 1996-01-30 Photoelectric converter and multichip type integrated circuit

Publications (1)

Publication Number Publication Date
JPH09214700A true JPH09214700A (en) 1997-08-15

Family

ID=11847789

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8013960A Pending JPH09214700A (en) 1996-01-30 1996-01-30 Photoelectric converter and multichip type integrated circuit

Country Status (1)

Country Link
JP (1) JPH09214700A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518761B2 (en) * 2003-08-21 2009-04-14 Seiko Epson Corporation Image scanning apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7518761B2 (en) * 2003-08-21 2009-04-14 Seiko Epson Corporation Image scanning apparatus

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