JP2003018465A - Imaging apparatus and imaging system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an imaging apparatus that prevents an occupied area of an imaging area from being increased by a switch means and a control line. SOLUTION: A 1st pixel group comprises 4 arranged pixels and 3 1st switch means that connect/disconnect the 4 pixels each other, a 2nd pixel group comprises 4 sets of the 1st pixel groups arranged and 3 2nd switch means that connect/disconnect in common one or two ore more pixels in the 4 sets of the 1st pixel groups, on/off control of 3 sets of the 1st switch means selects a summing processing mode where signals of the pixels in the 1st pixel group are summed or a non summing processing mode where no signals are summed, and on/off control of 3 sets of the 2nd switch means select a summing processing mode where signals of the pixels in the 1st pixel group are summed or a non summing processing mode where no signals are summed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus and an image pickup system, and more particularly to an image pickup apparatus and an image pickup system capable of adding and outputting outputs from two or more pixels.

[0002]

2. Description of the Related Art Some image pickup apparatuses are required to have a standard operation for reading out all pixels and a method capable of reading out at a high frame rate (speed) even if the resolution is lowered. . In this case, there is also a method of thinning out pixels for scanning, but in this case, the information of the skipped pixels is discarded, which is disadvantageous in terms of sensitivity. Therefore, a method has been proposed in which the outputs from the pixels are added in the imaging region and read out as an addition signal, and the signals are read out at a high frame rate.

FIG. 13 is a schematic diagram showing an example of an addition method between pixels in an image pickup area of an image pickup apparatus. FIG.
In the image pickup device shown in (1), an addition switch is arranged between the arranged pixels (indicated by a black square in the figure), and a decoder (indicated by a square in the figure) to control each addition switch. Is provided for each addition switch. Further, a plurality of control lines CL are arranged in the image pickup device to control each decoder, and each decoder is controlled to individually turn on / off each addition switch in the addition mode of the image pickup device.

[0004]

However, as shown in FIG.
Providing the addition switch as shown in (1) between each pixel, and providing the switch control means such as a decoder and the control line for each addition switch leads to an increase in the area occupied by the imaging region.

[0005]

The image pickup device of the present invention comprises a number of a pixels (a is a natural number of 2 or more) arranged, and a
A first pixel group including a first switch means for connecting and disconnecting a plurality of pixels, b arranged (b is a natural number of 2 or more) of the first pixel group, and b A second pixel group including a second switch means for connecting and disconnecting a plurality of pixels respectively included in the first pixel group, and on / off control of the first switch means to control the first pixel Included in a plurality of first pixel groups for switching between an addition processing mode for performing signal addition processing of pixels in the pixel group and a non-addition processing mode for not performing signal addition processing of pixels in the first pixel group. A first common signal line for commonly controlling a plurality of first switch means and an on / off control of the second switch means between the first pixel groups in the second pixel group. An addition processing mode for performing signal addition processing and a first pixel in the second pixel group. A second common signal line for commonly controlling a plurality of second switch means included in a plurality of second pixel groups for switching a non-addition processing mode in which signal addition processing between prime groups is not performed; It is characterized by having.

An image pickup system of the present invention comprises the image pickup apparatus of the present invention, an optical system for forming an image of light on the image pickup apparatus, and a signal processing circuit for processing an output signal from the image pickup apparatus. To do.

[0007]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1 is a schematic configuration diagram showing a first embodiment of an image pickup apparatus of the present invention. Here, 8 × 8 pixels are shown. A11 to A88 indicate pixels, S1 to S8 indicate control lines for controlling the addition switch (SW), CL indicates a plurality of addition mode control lines, and 11
-18 shows a decoder. 2A to 2C are configuration diagrams showing the configuration of one pixel. 3A to 3D are conceptual diagrams showing a 4-pixel addition state, a 16-pixel addition state, a 64-pixel addition state, and a 256-pixel addition state, respectively.

As shown in FIG. 3A, in the case of 4-pixel addition, the control lines S1, S3, S5 and S7 shown in FIG. 1 are set to a high level and the addition switches connected to them are turned on. Thus, the pixels are commonly connected in units of four pixels. For example,
In the area A shown in FIG. 3A, the pixels A11, A12, A21, A
22 are commonly connected and signals are added.

As shown in FIG. 3 (b), in the case of 16 pixel addition, the control lines S1, S2, S3, S5, S shown in FIG.
With 6 and S7 at the high level, the addition switches connected to them are turned on to connect the pixels in common in units of 16 pixels. For example, in the area B shown in FIG.
.About.A14, A21 to A24, A32 to A34, A41 to A44 are commonly connected and signals are added.

As shown in FIG. 3C, in the case of 64-pixel addition, the control lines S1 to S7 and S9 to S15 (S9) shown in FIG.
(S15 is not shown) is set to a high level, the addition switches connected to the respective switches are turned on, and pixels are commonly connected in units of 64 pixels. For example, in the area C shown in FIG. 3C, the pixels A11 to A88 are commonly connected and signals are added.

As shown in FIG. 3D, in the case of 256 pixel addition, the control lines S1 to S15 and S17 to (S9 shown in FIG. 1 are used.
(S17 are not shown) is set to a high level, the addition switches connected to the respective switches are turned on, and the pixels are commonly connected in 256 pixel units.

In the present embodiment, assuming that the area A shown in FIG. 3A is the first pixel group (4 pixels and 3 addition switches), the second pixel group is shown in FIG. A region B shown in FIG. 3B) and a third pixel group are regions C shown in FIG. If the region B shown in FIG. 3B is the first pixel group (16 pixels and 15 addition switches), the second pixel
The pixel group of is a region C shown in FIG.

The above-mentioned addition method will be described with reference to FIGS. 4A to 4D. In the case of 4-pixel addition, as shown in FIG. 4A, a pixel (in the figure, 1 represents one pixel). ) Are added using three addition switches. The addition pixel unit here is the addition area A. Next, in the case of 16-pixel addition, as shown in FIG. 4B, four addition areas A to which four pixels have been added are added using three addition switches. The addition pixel unit here is the addition area B. Next, in the case of 64-pixel addition, as shown in FIG. 4C, four addition regions B to which 16 pixels have been added are added using three addition switches. The addition pixel unit here is the addition area C. Next, in the case of 256 pixel addition, as shown in FIG. 4D, four addition regions C to which 64 pixels have been added are added using three addition switches. The addition pixel unit here is the addition area D. As can be understood from FIGS. 4A to 4D, this embodiment has a configuration in which four pixels or four addition regions are connected by turning on three addition switches.

Next, the structure of one pixel will be described with reference to FIGS. As shown in FIG. 2A, the cathode side of the photodiode PD is the first amplifier Amp1.
And a switch (which is a sampling switch controlled by the sample / hold signal (S / H)) that configures the sample and hold circuit and a capacitor C that are connected to the output side of the first amplifier Amp1. Capacity C
Is connected to the second amplifier Amp2. Second amplifier A
The output of mp2 is output to the vertical output line SL via the switch controlled by the control signal G. First amplifier Am
As shown in FIG. 2B, for example, p1 is composed of a source follower circuit composed of a MOS transistor M1 and a current source I1. The second amplifier Amp2 and the switch (selection switch) are, for example, as shown in FIG.
It is composed of a MOS transistor M2 and a MOS transistor M3 connected to the drain side thereof (controlled by a control signal G applied to the control line GL). The addition of pixels is performed by connecting the capacitances C of the pixels with an addition switch (SW), and the charges accumulated in the capacitance C can be added and output in other words as an average value of the potential. it can.

Although the pixel addition read operation has been described above, the operation of reading the output from all the pixels can be performed by turning off all the addition switches.

(Second Embodiment) In the first embodiment described above, a decoder for controlling an addition switch for adding pixels is provided separately from a scanning circuit for reading out signals from the pixels. Indicated. In this embodiment, an example will be described in which a signal from a scanning circuit such as a shift register for reading a signal from a pixel is used to control an addition switch for adding pixels.

FIG. 5 is a schematic configuration diagram showing a second embodiment of the image pickup apparatus of the present invention. In FIG. 5, Sw1 to S
w8 is a signal for controlling the addition switch, G1 to G8
Is a signal for performing control to output a signal from each of the pixel groups arranged in one direction. Each of the signals G1 to G8 is applied to the control line GL shown in FIG. 2A, for example. FIG. 6 is a diagram showing a circuit for outputting a signal for controlling the addition switch and the pixel selection switch. FIG. 7 is a diagram showing a logical operation circuit and its truth table.

FIG. 8 is a timing chart in the all-pixel reading mode, FIG. 9 is a timing chart in the 4-pixel addition mode, FIG. 10 is a timing chart in the 16-pixel addition mode, and FIG. 11 is a 64-pixel addition mode. It is a timing chart in the case of.

As shown in FIG. 6, a circuit for outputting a signal for controlling the addition switch and the pixel selection switch is composed of a shift register for outputting signals Q1 to Q8 and a logical operation circuit. The logic operation circuit is composed of the logic gate 1 shown in FIG. 7A and the logic gate (AND gate) shown in FIG. 7B, and the input sides of the logic gates 1 and 2 output the signals Q1 to Q8 of the shift register, respectively. Connected from the output side of the logic gate 1 to the control signals G1 to G1.
G8 is output, and the control signals Sw1 to Sw8 are output from the output side of the logic gate 2. OE is a signal for on / off controlling the output of the shift register.

In the all-pixel reading mode shown in FIG. 8, S
Since the clock CLK is operated by only one pulse when IN is at the high level, the control signals G1 to G8 sequentially become the high level in accordance with the signals Q1 to Q8 output from the shift register, and the control signals Sw1 to Sw8 are all Since the addition switches are held at the low level and all the addition switches are turned off, a signal is output from each pixel to the vertical output line for each pixel row.

In the 4-pixel addition mode shown in FIG. 9, the SIN
Since two pulses of the clock CLK are input when is at a high level, two shift pulses are generated inside the shift register. From the shift register, the signals Q1, Q2 and Q
, 3 and Q4, ... and 2 pulses are simultaneously output, and in accordance with this pulse, the control signals G2, G4, G6, and G8 are at a high level, the control signals Sw1, Sw3, Sw5, and Sw7 are at a high level, and the control signal Sw1, Sw3, Sw5, Sw
Since the addition switch controlled by 7 is turned on, the 4-pixel addition processing as shown in FIG. 3A is performed, and for example, addition (average) of the pixels in the area A of FIG. 3A is performed.
The value is output.

In the 16-pixel addition mode shown in FIG. 10, S
Since four pulses of the clock CLK are input when IN is at the high level, four shift pulses are generated inside the shift register. Signals Q1 to Q from the shift register
4, Q5 to Q8 and 4 pulses are simultaneously output, and in accordance with this pulse, the control signals G4 and G8 are at a high level, and the control signals Sw1 to Sw3 and Sw5 to Sw7 are at a high level.
Since the addition switches controlled by the control signals Sw1 to Sw3 and Sw5 to Sw7 are turned on, the 16-pixel addition processing as shown in FIG.
The addition (average) value of the pixels in the area B in (b) is output.

In the 64-pixel addition mode shown in FIG. 11, S
Since eight pulses of the clock CLK are input when IN is at the high level, eight shift pulses are generated inside the shift register. Signals Q1 to Q8 from the shift register
8 pulses at the same time, the control signal G8 goes to high level and the control signals Sw1 to Sw7 go to high level according to this pulse, and the addition switches controlled by the control signals Sw1 to Sw7 are turned on. 64 pixel addition processing as shown in FIG.
The addition (average) value of the pixels in the area C in (c) is output.

In the embodiment described above, four arranged
The (a = 4) pixels and the 3 (a-1 = 3) first switch means constitute a first pixel group and are arrayed in four.
The (b = 4) first pixel group and the 3 (b-1 = 3) second switch means constitute a second pixel group, and 4 (c = 4) arrayed pixels are arranged. Of the second pixel group of 3 (b-1 =
3) Taking the case where the third pixel group is composed of three third switch means as an example, 4 pixel addition, 16 pixel addition, and 64 pixel addition are performed, but the number of pixels or pixel groups is 4. However, the number of pixels or pixel groups may be 2, 3 or 5 or more.

Next, an image pickup system using the above image pickup apparatus will be described. An embodiment in which the image pickup apparatus of the present invention is applied to a still camera will be described in detail with reference to FIG.

FIG. 12 is a block diagram showing a case where the image pickup apparatus of the present invention is applied to a "still video camera".

In FIG. 12, reference numeral 101 is a barrier that also serves as a lens switch and a main switch, 102 is a lens for forming an optical image of a subject on an image pickup element (image pickup apparatus) 104, and 103 is a variable amount of light passing through the lens 102. Is an image pickup element for taking in the subject formed by the lens 102 as an image signal, 106 is an A / D converter for performing analog-digital conversion of the image signal output from the image pickup element 104, and 107 is A / D converter 1
The signal processing unit 108 performs various corrections on the image data output from the image processing unit 06 and compresses the data.
4, a timing generator that outputs various timing signals to the imaging signal processing circuit 105, the A / D converter 106, and the signal processing unit 107, and 109 is an overall control / operation unit that controls various operations and the entire still video camera. Is a memory unit for temporarily storing image data, 111 is an interface unit for recording or reading on a recording medium, and 112 is a removable recording medium such as a semiconductor memory for recording or reading image data. , 113 are interface units for communicating with an external computer or the like.

Next, the operation of the still video camera at the time of shooting with the above-mentioned structure will be described.

When the barrier 101 is opened, the main power source is turned on, then the control system power source is turned on, and further, the image pickup system circuit such as the A / D converter 106 is turned on.

Then, in order to control the exposure amount, the overall control / arithmetic unit 109 opens the diaphragm 103, the signal output from the image pickup device 104 is converted by the A / D converter 106, and then the signal processing unit. It is input to 107. The overall control / calculation unit 109 calculates the exposure based on the data.

The brightness is determined based on the result of the photometry, and the overall control / calculation unit 109 controls the aperture according to the result.

Next, based on the signal output from the image pickup device 104, a high frequency component is extracted and the distance to the object is calculated by the overall control / calculation unit 109. After that, the lens is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens is driven again to measure the distance.

Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the image sensor 104 is A / D converted by the A / D converter 106, passes through the signal processing unit 107, and is written in the memory unit by the overall control / calculation 109. Thereafter, the data accumulated in the memory unit 110 is recorded on the removable recording medium 112 such as a semiconductor memory through the recording medium control I / F unit under the control of the overall control / arithmetic unit 109. Alternatively, the image may be processed by directly inputting it to a computer or the like through the external I / F unit 113.

[0035]

As described above, according to the present invention,
The area occupied by the imaging region can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a first embodiment of an image sensor of the present invention.

2A to 2C are configuration diagrams showing the configuration of one pixel.

FIG. 3A to FIG. 3D are four-pixel addition states,
It is a conceptual diagram which shows a 16 pixel addition state, a 64 pixel addition state, and a 256 pixel addition state.

4A to 4D are explanatory diagrams for explaining addition methods.

FIG. 5 is a schematic configuration diagram showing a second embodiment of the image sensor of the present invention.

FIG. 6 is a diagram showing a circuit for outputting a signal for controlling an addition switch and a pixel selection switch.

FIG. 7 is a diagram showing a logical operation circuit and a truth table thereof.

FIG. 8 is a timing chart in the all-pixel reading mode.

FIG. 9 is a timing chart in the case of a 4-pixel addition mode.

FIG. 10 is a timing chart in the 16-pixel addition mode.

FIG. 11 is a timing chart in the 64-pixel addition mode.

FIG. 12 is a block diagram showing a case where the image pickup apparatus of the present invention is applied to a still video camera.

FIG. 13 is a schematic configuration diagram showing an example of an addition method between pixels in an image pickup area of an image pickup device.

[Explanation of symbols]

A11 to A88 pixels S1 to S8 Control line for addition switch (SW) CL Multiple addition mode control lines

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) // H04N 101: 00 H01L 31/02 A (72) Inventor Kazuaki Tashiro 3-30 Shimomaruko, Ota-ku, Tokyo No. 2 Canon Inc. (72) Inventor Tetsunobu Mitsuchi 3-30-2 Shimomaruko, Ota-ku, Tokyo No. 2 Canon Inc. (72) Shin-Kikuchi 3-30-2 Shimomaruko, Ota-ku, Tokyo No. Canon Inc. (72) Inventor Tomoyuki Noda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. F-term (reference) 4M118 AA10 BA14 CA02 DB09 FA06 FA34 FA42 5C022 AA13 AB02 AB22 AC31 AC42 AC69 5C024 CX00 GX03 GY31 HX28 HX50 5F088 BA15 BB03 EA04 EA08 EA16 KA03 KA08

Claims (9)

[Claims] 1. Arranged a number (a is a natural number of 2 or more)
Pixel group, and a first pixel group that includes a first switch unit that connects and disconnects the a number of pixels, and the arranged b number (b is a natural number of 2 or more) of the first pixels. A second pixel group including a group and a second switch unit that connects and disconnects a plurality of pixels respectively included in the b first pixel groups, and an on / off state of the first switch unit. A plurality of first switching processing modes for switching between an addition processing mode for performing signal addition processing of pixels in the first pixel group and a non-addition processing mode for not performing signal addition processing of pixels in the first pixel group under control. 1
A first common signal line for commonly controlling a plurality of first switch means included in the second pixel group, and an on / off control of the second switch means for controlling the first common signal line in the second pixel group. A plurality of second pixels for switching between an addition processing mode for performing signal addition processing between the pixel groups and a non-addition processing mode for not performing signal addition processing between the first pixel groups in the second pixel group A second common signal line for commonly controlling a plurality of second switch means included in the group, and an imaging device. 2. The image pickup device according to claim 1, wherein c second pixel groups (c is a natural number of 2 or more) are arranged,
By a third pixel group including a third switch unit that connects and disconnects a plurality of pixels respectively included in the c second pixel group, and by controlling ON / OFF of the third switch unit. , A plurality of third processing modes for switching between an addition processing mode for performing signal addition processing of pixels in the third pixel group and a non-addition processing mode for not performing signal addition processing of pixels in the third pixel group.
And a third common signal line for commonly controlling a plurality of third switch means included in the pixel group, and the image pickup apparatus. 3. The image pickup device according to claim 1, wherein the pixel includes a photoelectric conversion unit and a capacitor for accumulating a signal from the photoelectric conversion unit or an amplified signal obtained by amplifying the signal. An image pickup device in which the second switch means is a means for controlling connection / disconnection of the capacitors between the pixels. 4. The image pickup device according to claim 2, wherein the pixel includes a photoelectric conversion unit and a capacitance for accumulating a signal from the photoelectric conversion unit or an amplified signal obtained by amplifying the signal. The image pickup device, wherein the second and third switch means are means for controlling connection / disconnection of the capacitors between the pixels. 5. The image pickup device according to claim 1, wherein the first pixel group includes (a-1) number of the first switch units, and the first co-communication is performed. Connected to the signal line and controlled simultaneously, the second pixel group is (b-
1) An image pickup device having a plurality of the second switch means, connected to the second common signal line, and controlled simultaneously. 6. The first pixel group has (a-1) number of the first switch means, is connected to the first common signal line, and is simultaneously controlled, and the second pixel group is connected to the first common signal line. The group is (b
-1) having the second switch means, connected to the second common signal line and controlled simultaneously, and the third pixel group has (c-1) first An image pickup apparatus having a switch means, connected to the third common signal line, and controlled simultaneously. 7. The image pickup device according to claim 5, further comprising a plurality of output control lines connected to a pixel group of the a pixels arranged in one array direction and sending an output control signal to the pixel group. A scanning circuit capable of sequentially outputting a pulse from a plurality of output terminals, and simultaneously outputting a pulse from any two or more output terminals of the plurality of output terminals, and being connected to the scanning circuit, When sequential pulses are output from the scanning circuit, sequential control signals are sent to the plurality of output control lines, and when pulses are simultaneously output from the scanning circuit, among the plurality of output control lines. A control signal is sent to an arbitrary output control line and the first switch control line, or an arbitrary output control line among the plurality of output control lines, the first switch control line, and the second switch control line. A logical operation circuit, An image pickup apparatus including. 8. The image pickup device according to claim 6, further comprising a plurality of output control lines connected to a pixel group of the a pixels arranged in one array direction and sending an output control signal to the pixel group. A scanning circuit capable of sequentially outputting a pulse from a plurality of output terminals, and simultaneously outputting a pulse from any two or more output terminals of the plurality of output terminals, and being connected to the scanning circuit, When sequential pulses are output from the scanning circuit, sequential control signals are sent to the plurality of output control lines, and when pulses are simultaneously output from the scanning circuit, among the plurality of output control lines. An arbitrary output control line and the first switch control line, an arbitrary output control line among the plurality of output control lines, the first switch control line and the second switch control line, or the plurality of outputs Out of control lines Imaging device and a logical operation circuit for sending a control signal output control line and the first switch control line and the second switch control line to the third switch control line. 9. An image pickup apparatus according to claim 1, an optical system for forming an image of light on the image pickup apparatus, and a signal processing circuit for processing an output signal from the image pickup apparatus. An imaging system comprising: