JPH09214575A - Delay detection circuit/method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a superior delay detection circuit which automatically and precisely corrects a phase and whose error rate is low. SOLUTION: A switch 24 causes either a phase difference correction quantity estimation unit 22 or 23 to estimate phase difference correction quantity. At the same time, a switch 25 selects the estimation correction quantity of the other estimation unit as first correction quantity and outputs it to an adder 15. A normal reception judgment unit 21 switches the selection states of the switches 24 and 25 wherever a known symbol string is normally received by a demodulator. A second correction circuit 16 estimates second correction quantity based on a temporary correction phase difference signal outputted from the adder 15 of a first correction circuit 14 and an ideal phase difference signal, generates a correction phase difference signal based on the temporary correction phase difference signal and second correction quantity and outputs it to a demodulator 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital phase modulation signal demodulation circuit, and more particularly to a PSK (Phase Shift Keyi).
ng) to a differential detection circuit and method for demodulating a signal.

[0002]

2. Description of the Related Art A differential detection system for demodulating a digital phase modulation signal is widely used in the field of mobile communication. However, the differential detection method has a drawback that the error rate is likely to be significantly deteriorated when there is a frequency shift due to a transmission frequency drift or the like. This is because the frequency shift is usually detected on the receiver side as a phase rotation of the reception phase difference. Therefore, a differential detection circuit that corrects this frequency shift has been proposed.

FIG. 3 shows an example of a conventional differential detection circuit.
The received phase difference signal is input to the demodulator 2 through the adder 1,
Then, after the demodulation symbols are estimated, the converter 3 detects the ideal phase difference. Phase difference correction amount estimator 4
Calculates the amount of phase correction by averaging the difference between the received phase difference and the ideal phase difference and outputs it to the adder 1. The adder 1 adds the received phase difference and the phase difference correction amount to correct the frequency shift, and feeds it back to the demodulator 2.

Another conventional example in which two such phase difference correction circuits are connected in series has been proposed. In another conventional example, when a predetermined known symbol sequence (bit synchronization and frame synchronization signal) of a burst signal is received, the phase difference correction circuit of the first stage is connected and the phase difference correction circuit of the second stage is stopped. Then, the phase difference correction circuit of the first stage corrects the phase difference. When receiving the subsequent unknown symbol sequence (data), the first-stage phase difference correction circuit is disconnected, and the second phase is estimated using the phase difference estimated value estimated by the first-stage phase difference correction circuit at that time. The phase difference correction circuit of the stage executes the phase difference correction.

[0005]

However, in the case of the differential detection circuit shown in FIG. 3, an error is likely to occur in the received signal which has been subjected to the frequency offset, and the phase rotation due to the frequency offset is 45. When the frequency exceeds, the received symbol cannot be correctly estimated and the amount of instantaneous frequency offset is erroneously detected.

Further, in the case of a differential detection circuit in which two phase difference correction circuits are connected, it is necessary for the processor (CPU) to predict and control the reception of known symbols and unknown symbol sequences, and the load on the CPU is large. Had the problem of becoming.

[0007]

A differential detection circuit according to the present invention includes a demodulator, a first phase difference correction circuit, a second phase difference correction circuit, and a normal reception determination unit. Switches the two phase difference correction amount estimators provided in the first phase difference correction circuit alternately each time it monitors the output of the demodulator and confirms normal reception of the known symbol sequence. As a result, it is possible to always correct the phase difference signal of the unknown symbol string by using the phase difference correction amount according to the latest known symbol string and accurately demodulate the unknown symbol string using the corrected phase difference signal. it can. At that time, switching control of the phase difference correction amount estimator is performed by the normal reception determining device without depending on the CPU.

More specifically, a circuit for demodulating a demodulated symbol signal from a digital phase-modulated burst reception signal consisting of a known symbol sequence and a subsequent unknown symbol sequence is provided with an instantaneous phase of the burst reception signal and one symbol time before. Phase difference detecting means for detecting a phase difference from the instantaneous phase of the first phase and generating a phase difference signal, a first correcting means for correcting the phase difference signal to generate a first corrected phase difference signal, and a first corrected phase difference signal. And a demodulation means for generating the demodulation symbol signal based on the second correction phase difference signal, and an ideal phase difference signal from the demodulation symbol signal. And a conversion means for outputting the first correction means and the second correction means respectively. The first and second correction means further include the following elements.

The first correcting means estimates the phase difference correction amount based on the phase difference signal and the ideal phase difference signal, and one of the first and second estimating means. Switching means for causing the means to estimate the phase difference correction amount and at the same time selecting the phase difference correction amount estimated by another estimating means as the first correction amount; and a first based on the phase difference signal and the first correction amount. First calculation means for generating a corrected phase difference signal,
Normal reception determination means for switching the selection state of the switching means when the known symbol sequence is normally received by the demodulation means,
Consists of Also, the second correction means estimates the second correction amount based on the first correction phase difference signal and the ideal phase difference signal, and the third correction means based on the first correction phase difference signal and the second correction amount. A second calculation means for generating a second corrected phase difference signal.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a differential detection circuit according to the present invention. In the present embodiment, the received PSK signal is a burst signal and is composed of a known symbol sequence (preamble signal etc.) having a predetermined bit pattern and an unknown symbol sequence (data signal) following it.

Such PSK signal 101 is limited to the limiter 1
The carrier band is limited by 0, and the limiter signal 102 is output to the instantaneous phase measuring device 11. The instantaneous phase measuring device 11 uses the limiter signal 102 to the instantaneous phase signal 103.
The instantaneous phase signal 103 is delayed by one symbol time by the symbol delay unit 12, and the delayed phase signal 104 is output to the subtractor 13. The subtractor 13 calculates the phase difference between the instantaneous phase signal 103 and the delayed phase signal 104 and generates the reception phase difference signal 105.

The received phase difference signal 105 is output to a first phase difference correction circuit consisting of a first correction amount estimation circuit 14 and an adder 15, where a temporary correction phase difference signal 106 estimated according to a known symbol sequence is generated. At the same time, the first correction amount estimation circuit 14 holds the first phase difference correction amount signal 114. The provisional correction phase difference signal 106 output from the adder 15 of the first phase difference correction circuit is further input to the second phase difference correction circuit including the second correction amount estimation circuit 16 and the adder 17, and the correction position is corrected there. The phase difference signal 108 is generated and the second phase difference correction amount signal 107 is held in the second correction amount estimation circuit 16. The corrected phase difference signal 108 is the demodulator 1
8 and the demodulated symbol signal 109 is generated.
Demodulated symbol signal 109 is output to converters 19 and 20 and normal reception determination unit 21, respectively.

The converter 19 converts the demodulated symbol signal 109 from the ideal phase difference signal 11 when the known symbol string is received.
0, and the correction amount estimation circuit 14 of the first phase difference correction circuit
Output to The converter 20 calculates the ideal phase difference signal 11 from the demodulated symbol signal 109 when the unknown symbol string is received.
1 is generated and output to the second correction amount estimation circuit 16. In addition, the normal reception determination unit 21 detects that the known symbol sequence of the received PSK signal is normally received, and outputs the switch switching signals 112 and 113 to the first correction amount estimation circuit 14 each time it is normally received. To do.

The first correction amount estimation circuit 14 comprises phase difference correction amount estimators 22 and 23 and switches 24 and 25. The switch 24 receives the received phase difference signal 105 from the phase difference correction amount estimators 22 and 23. Transfer to either switch 2
Reference numeral 5 denotes an adder 1 for selecting one of the phase difference correction amount signals output from the phase difference correction amount estimators 22 and 23.
Output to 5 At this time, the switching operation of the switches 24 and 25 is performed by switching the switching signals 112 and 1 from the normal reception judging device 21.
Both switches are controlled by 13 to select different phase difference correction amount estimators. For example, when the switch 24 selects the estimator 22 and transfers the received phase difference 105 to the estimator 22, the switch 25 selects the estimator 23 and outputs the phase difference correction amount signal output by the estimator 23. Transfer to the adder 15.

As described above, the phase difference correction amount estimators 22 and 23 receive the instantaneous received phase difference signal 105 and the ideal phase difference signal 110 obtained from the known symbol sequence, and instantaneously receive them. The phase difference correction amount is estimated, and the phase difference correction amount is generated by averaging them while sequentially holding them. Therefore, although not shown, each estimator 2
2 and 23 are provided with memories for holding the phase difference correction amount. The phase difference correction amount estimator 26 that generates the phase difference correction amount 107 from the provisional correction phase difference signal 106 also has the same configuration.

Next, the phase difference correction operation of the differential detection circuit according to the present embodiment will be described. However, in the initial state,
It is assumed that the switch 24 of the first correction amount estimation circuit 14 selects the phase difference correction amount estimator 22 and the switch 25 selects the phase difference correction amount estimator 23, and further, the first phase difference correction circuit The outputs of the phase difference correction amount estimators 22 and 23 and the output of the phase difference correction amount estimator 26 of the second correction amount estimation circuit 16 are both reset to zero, and the provisional correction phase difference signal 106 and the correction phase difference The signal 108 is the received phase difference signal 1
It shall be equal to 05. The case where the PSK burst signal 101 is input to the differential detection circuit in such an initial state will be described below.

First, the preamble part of the burst signal, that is, the received phase difference signal 105 corresponding to the known symbol sequence is input, but the first phase difference correction amount 114 and the second phase difference correction amount 107 are zero, so it is provisional. Corrected phase difference signal 106
And the corrected phase difference signal 108 is the same as the received phase difference signal 105. Therefore, the demodulated symbol signal 109 corresponding to the known symbol sequence is obtained, the ideal phase difference signal 110 according to it is supplied from the converter 19 to the phase difference correction amount estimators 22 and 23, and the ideal phase difference signal 111 is also supplied. Is supplied from the converter 20 to the phase difference correction amount estimator 26. The phase difference correction amount estimator 22 estimates the instantaneous phase difference correction amount using the received phase difference signal 105 input through the switch 24 and the ideal phase difference signal 110 input from the converter 19, A phase difference correction amount signal is generated and held by averaging them. In this case, since the phase difference correction amount generated by the phase difference correction amount estimator 22 corresponds to the known pattern, it can be estimated with high reliability in a short time.

When the known symbol sequence is normally received and the synchronization is established in this way, the normal reception determining unit 21 outputs the switching signals 112 and 113 to the switches 24 and 25 of the first correction amount estimating circuit 14, respectively, whereby the switches 24 and 25 are output. A switch 25 selects the phase difference correction amount estimator 23 and a switch 25 selects the phase difference correction amount estimator 22. As a result, the first phase difference correction amount 114 output to the adder 15 becomes the phase difference correction amount corresponding to the known symbol sequence held in the phase difference correction amount estimator 22. At the same time, the phase difference correction amount estimator 23 inputs the received phase difference signal 105 corresponding to the unknown symbol string (data) following the known symbol string, and estimates the correction amount based on the received phase difference signal 105.

When an unknown symbol sequence (data) is received following this known symbol sequence, the reception phase difference signal 105 of the unknown symbol sequence is input to the adder 15 and output from the phase difference correction amount estimator 22. It is corrected by the first phase difference correction amount 114. The provisional corrected phase difference signal 106 thus obtained is input to the adder 17, but since the phase difference correction amount 107 of the phase difference correction estimator 26 is zero at this time, the corrected phase difference signal 108 is used as it is as the demodulator. It is output to 18. Therefore, the demodulated symbol signal 109 corresponding to the unknown symbol sequence is obtained, and the ideal phase difference signal 111 according to it is supplied from the converter 20 to the phase difference correction amount estimator 26. The phase difference correction amount estimator 26, based on the provisional correction phase difference signal 106 and the ideal phase difference signal 111,
A phase difference correction amount 107 is generated by estimating instantaneous phase difference correction amounts and averaging them while sequentially holding them, and outputs them to the adder 17. The adder 17 corrects the provisional corrected phase difference signal 106 corresponding to the unknown symbol sequence using the phase difference correction amount 107, and outputs it to the demodulator 18 as a corrected phase difference signal 108. The demodulator 18 demodulates the demodulated symbol signal 109 from the corrected phase difference signal 108 of the unknown symbol string.

As described above, when the known symbol sequence (preamble) is received while the unknown symbol sequence (data) is in the demodulation operation state and the normal reception determination unit 21 determines the normal reception as described above, the switching signal 112 and 113
Accordingly, the switches 24 and 2 of the first correction amount estimation circuit 14
5 is switched again. That is, the switch 24 transfers the received phase difference signal 105 to the phase difference correction amount estimator 22, and the switch 25 outputs the phase difference correction amount held in the phase difference correction amount estimator 23 to the adder 15. Therefore, the adder 15
The tentative correction phase difference signal 106 output from is always corrected by the first phase difference correction amount signal 114 of the retrial.

Next, the operation of this embodiment will be described more specifically by taking a burst signal in the digital cordless telephone system as an example.

FIG. 2 shows a signal format (A) of a synchronous burst signal and a signal format (B) of a normal burst signal of a digital cordless telephone. For example, if the bit synchronization signal 201 in the sync burst signal of a digital cordless telephone is a known symbol string, the minimum intersymbol distance between the known symbols is twice that of the unknown symbol string, so the demodulated symbol signal. The probability of 109 being erroneous is extremely low. As a result, the number of instantaneous phase correction amounts averaged by the phase difference correction amount estimator can be reduced, so that the phase difference correction amount estimators 22 and 23 can calculate the phase difference correction amount in a short time with high reliability. Can be estimated. Further, when the frame synchronization signal 202 in the synchronization burst signal is set in the normal reception determination device 21, the switches 24 and 25 are interlocked and switched each time the synchronization burst signal is normally received.

Next, when the normal burst reception comes after the synchronous burst signal reception, since the estimation for outputting the phase correction amount signal 114 has already been completed, the adder 15 sets the reception phase difference signal 105 to the phase. The correction is performed according to the correction amount 114, and the provisional correction phase difference signal 106 is output. At this point, the phase difference correction amount signal 107 of the phase difference correction amount estimator 26 is still reset to zero, so that the correction phase difference signal 1
08 and the provisional correction phase difference signal 105 are equal. In this state, the demodulator 18 estimates and outputs the demodulated symbol signal 109 by detecting the phase difference closest to the corrected phase difference signal 108 from the ideal phase differences of all the transmission symbols. On the other hand, the phase difference correction amount estimation 26 estimates and averages the instantaneous phase correction amount based on the ideal phase difference signal 111 of the demodulated symbol signal 109 output by the converter 20 and the provisional correction phase difference signal 106. Thus, the phase correction amount signal 108 is estimated and output. As described above, the phase difference correction amount estimator 26 corrects the phase difference correction amount estimated in advance by the phase difference correction amount estimator 22 when the transmission symbol is unknown and cannot be predicted, and The ideal phase difference 11 estimated from the corrected
The phase correction amount 108 is estimated from the deviation from 1.

Next, when the synchronous burst signal is received during the normal burst reception, the frame reception signal 202 in the synchronous burst signal is set in the normal reception determination unit 21. Switch to
And 25 are switched, and the latest phase difference correction amount signal 1
The court corrected phase difference signal 106 is obtained using 14. Since such a switching operation timing of the switches 24 and 25 is controlled by the normal reception determining unit 21, the CPU
The control load of is reduced.

As described above, the phase difference correction amount estimator 22
And 23, the phase difference correction amount estimator 26, and the normal signal reception determining unit 21 are used, the error rate of the error rate is corrected by using the corrected phase difference signal 108 in which the influence of the frequency offset is always removed in the demodulator 18. An excellent demodulated symbol signal 109 can be estimated and output.

[0027]

As described above, according to the present invention, it is not necessary for the CPU to predict and control that a predetermined known symbol sequence is received and an unknown information symbol sequence is received. . In addition, even if a sync burst signal, which is a known symbol string, is suddenly received during normal burst reception, correction can always be performed automatically using the latest phase difference correction amount, so there is a frequency shift due to transmission frequency drift, etc. Even in the case, there is an effect that can be received correctly.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a differential detection circuit according to the present invention.

FIG. 2A is a diagram showing a signal format of a sync burst signal of a digital cordless telephone system, and FIG.
FIG. 4 is a diagram showing a signal format of a normal burst signal.

FIG. 3 is a block diagram showing an example of a conventional differential detection circuit.

[Explanation of symbols]

 10 Limiter 11 Instantaneous Phase Measuring Device 12 Delay Element 13 Subtractor 14 First Correction Amount Estimation Circuit 15 Adder 16 Second Correction Amount Estimation Circuit 17 Adder 18 Demodulator 19 Converter 20 Converter 21 Normal Reception Judgmenter 22 Phase Difference Correction amount estimator 23 Phase difference correction amount estimator 24 Switch 25 Switch 26 Phase difference correction amount estimator

Claims (3)

[Claims] 1. A circuit for demodulating a demodulated symbol signal from a digital phase-modulated burst reception signal consisting of a known symbol sequence and a subsequent unknown symbol sequence, the instantaneous phase of the burst reception signal and the instant one symbol time before. Phase difference detecting means for detecting a phase difference from the phase and generating a phase difference signal; first correcting means for correcting the phase difference signal to generate a first corrected phase difference signal; and the first corrected phase difference signal Correcting means for generating a second corrected phase difference signal, demodulation means for generating the demodulated symbol signal based on the second corrected phase difference signal, and an ideal phase difference signal from the demodulated symbol signal. Produces
And a conversion unit that outputs to the first correction unit and the second correction unit, respectively. The first correction unit estimates a phase difference correction amount based on the phase difference signal and the ideal phase difference signal. The first and second estimating means and one of the first and second estimating means are caused to execute the estimation of the phase difference correction amount, and at the same time, the phase difference correction amount estimated by another estimating means is calculated. Switching means for selecting the first correction amount; and the first difference based on the phase difference signal and the first correction amount.
And a normal reception determination unit that switches the selection state of the switching unit when the known symbol sequence is normally received by the demodulation unit. A third estimating means estimates a second correction amount based on the first correction phase difference signal and the ideal phase difference signal, and a third estimation means based on the first correction phase difference signal and the second correction amount. A second detection means for generating a second corrected phase difference signal, and a differential detection circuit comprising: 2. The input switching means for transferring the phase difference signal to a selected one of the first estimating means and the second estimating means, and the first switching means.
An output switching unit that selects, as the first correction amount, the other estimated output that is not selected by the input switching unit from the estimation unit and the second estimation unit; 2. The differential detection circuit according to claim 1, wherein when the demodulation unit receives the signal normally, the selection states of the input switching unit and the output switching unit are switched. 3. A differential detection method for demodulating a demodulated symbol signal from a digital phase-modulated burst reception signal consisting of a known symbol sequence and a subsequent unknown symbol sequence, the instantaneous phase of the burst reception signal and one symbol time before. A phase difference signal is generated by detecting a phase difference from the instantaneous phase of the, an ideal phase difference signal is generated from the demodulated symbol signal, and the known symbol sequence is normally received by the demodulating means. By alternately selecting two phase difference correction amount estimators that perform the phase difference correction amount estimation based on the phase difference signal and the ideal phase difference signal, one of the phase difference correction amount estimators is At the same time as estimating the phase difference correction amount corresponding to, the other phase difference correction amount estimator generates the already estimated phase difference correction amount as the first correction amount, A first correction phase difference signal based on the first correction amount and the first correction amount, and a second correction amount is estimated based on the first correction phase difference signal and the ideal phase difference signal. A differential detection method comprising: generating a second corrected phase difference signal based on a phase difference signal and the second correction amount, and demodulating the demodulated symbol signal from the second corrected phase difference signal.