JP2841980B2 - Demodulation phase detector - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention is used for digital communication. In particular, the present invention relates to a technique for determining a synchronization polarity of a demodulated signal.

[0002]

2. Description of the Related Art A conventional example will be described with reference to FIG. FIG.
Is a diagram for explaining a conventional example.

When a demodulated signal is input from a demodulated signal input terminal 1, a correlator 2 calculates a correlation based on a preset frame timing from a frame timing generator 5. The calculation result is input to the demodulation phase estimation circuit 3 and the demodulation phase n is output. The output of the correlator 2 is also input to an absolute value circuit 6, and the output is input to a slip detection circuit 7. At this time, when the slip detection circuit 7 detects a slip, the slip information is output from the slip detection output terminal 8. Using the slip information, it is possible to check the data damaged by the slip and request the transmission terminal again to transmit the data.

[0004] In communication using a PSK (Phase Shift Keying) modulation signal often used in satellite communication, mobile communication, or the like, the phase of a signal demodulated during reception remains indefinite in principle. For example, in QPSK (8-phase modulation), when a demodulated signal is represented on a phase plane as shown in FIG.
There are four possibilities shown in FIG. 3 (b) as to which of (0), (0, 1), (1, 0) and (1, 1) it corresponds.

In order to remove the uncertainty of the demodulation phase,
Generally, a predetermined fixed word is inserted into a transmission signal, and the demodulation phase is estimated from the phase state of the fixed word detected from the demodulated signal.

When the quality of a communication line is high, the demodulation phase once determined does not change, but the S / N ratio is different from that of a satellite communication line.
In a line with a low ratio, the demodulation phase may slip due to loss of synchronization of the carrier. Therefore, in such a low-quality line, a fixed word is periodically inserted into a transmission signal as shown in FIG. 3C so that a change in demodulation phase can be detected.

Since the quality of the conventional satellite communication line is not so low, a change in demodulation phase due to loss of synchronization rarely occurs. Therefore, the synchronization of fixed words that are periodically inserted can be made very long.

[0008]

However, in lower quality communication lines such as mobile satellite communications and mobile communications, demodulation phase slip is caused by factors such as multipath, fading, and short-term variations in carrier frequency. Occur more frequently. Therefore, it is impossible to detect and correct the slip of the demodulation phase if the period in which the fixed words are inserted is long as in the related art. Therefore, it is necessary to shorten the fixed word insertion cycle, but in order not to reduce the communication efficiency by doing so, the fixed words must be shortened.

However, if the fixed word is shortened, the accuracy of demodulation phase estimation decreases, and the probability of erroneous estimation increases. In that case, all data up to the next fixed word will be erroneous, and the error rate will be degraded.

The present invention has been made in view of such a background, and an object of the present invention is to provide a demodulation phase detection device that reduces a data error rate due to a demodulation phase slip while maintaining communication efficiency.

[0011]

According to the present invention, a demodulated signal input terminal for inputting a PSK demodulated signal including a fixed word for phase detection, a demodulated signal from the demodulated signal input terminal, and a frame timing generator A correlator that calculates a correlation with a long frame timing of the correlator, a demodulation phase estimating circuit that inputs a calculation result of the correlator and outputs a demodulation phase, and inputs a calculation result of the correlator and calculates an absolute value thereof In a demodulation phase detection device comprising an absolute value circuit and a slip detection circuit for receiving a calculation result of the absolute value circuit and detecting a demodulation phase slip, the correlator includes a correlation calculation for coping with the occurrence of a demodulation phase slip. Means, wherein the slip detection circuit includes means for switching a demodulated phase output to an output that copes with the demodulated phase slip when a demodulated phase slip occurs. That.

Further, it is preferable that the correlation calculation means for dealing with the occurrence of the demodulation phase slip includes a correlator with a short frame timing, separately from the correlator.

[0013]

In the demodulation phase detecting device of the present invention, a fixed bit having a shorter period T than a period in which a slip of the demodulation phase occurs is inserted into the transmission signal in advance, and K bits are inserted. The demodulation side calculates a cross-correlation value between the fixed word pattern and the transmitted fixed word pattern for fixed words L × K bits included in the range of the period L × T (L is an integer) in the received signal. When the absolute value of the correlation value is larger than a predetermined threshold value, it is determined that there is no slip of the demodulation phase during this period, and the period is included in the period according to the demodulation phase estimated from the correlation value. Output demodulated data. If it is smaller than the threshold value, it is determined that a slip has occurred, and the fixed word according to the demodulation phase estimated from each received n-bit fixed word,
Output the data contained between the next fixed words.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration of an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

The present invention provides a PSK including a fixed word for phase detection.
A demodulated signal input terminal 1 for inputting a demodulated signal; a correlator 2 for inputting a demodulated signal from the demodulated signal input terminal 1 and calculating a correlation based on a long frame timing from a frame timing generator 5; , A demodulation phase estimating circuit 3 for outputting the demodulation phase, outputting a demodulation phase, an absolute value circuit 6 for inputting the calculation result of the correlator 2 and calculating the absolute value thereof, and a calculation result of the absolute value circuit 6 In a demodulation phase detection device including a slip detection circuit 7 for detecting a slip of a demodulation phase as input, the correlator 2 includes a second correlator 2 ^′ as correlation calculation means for coping with the occurrence of the demodulation phase slip. The slip detection circuit 7 is provided with a selector switch 10 as means for switching the demodulated phase output to an output for coping with the demodulated phase slip when the demodulated phase slip occurs. .

The second correlator 2 ^' as a correlation calculating means for coping with the occurrence of the demodulation phase slip is a correlator 2 ^'.
Apart from this, the correlation is calculated by a short second frame timing.

Next, the operation of the apparatus according to the embodiment of the present invention will be described with reference to FIGS. FIG. 2 is a diagram showing a transmission signal according to the embodiment of the present invention.

FIG. 2 shows a transmission signal. The fixed words are inserted for each cycle T by K bits. This fixed word is a pattern that repeats at a longer cycle L × T (L is an integer),
It is represented as _Vlk using the subscripts l and k (l and k are integers, l ≦ L and k ≦ K). V _lk is a complex number for M-phase PSK

[0019]

(Equation 1) Take the value.

The correlator 2 and data contained between the period LT of the demodulated signal, obtains a correlation value A ₁ of the fixed word V _lk.
If the demodulated signal is represented by D (t) and the clock cycle is represented by t _c

[0021]

(Equation 2) Becomes Here, * represents a complex conjugate. Also, D (t)
It is expressed in the timing such that the head of the data V ₁₁ of the fixed word when t = 0. Therefore, when t = 0, the demodulated data is synchronized with the fixed word, and the correlation value is

[0022]

(Equation 3) Becomes [1] indicates the demodulation phase. This is the absolute value | A ₁ (0) | = LK of A ₁ (0) when no slip occurs in the demodulation phase [outside 1] during this time.

[0023]

[Outside 1] On the other hand, if the demodulation phase slips between l = l ₁ and l = l ₁ +1 and becomes [outside 1],

[0024]

(Equation 4) | A ₁ (0) | <LK.

[0025]

[Outside 2] Therefore, it is possible to detect the slip by inputting the output of the correlator 2 to the absolute value circuit 6 to obtain the absolute value of the correlation value, and comparing the absolute value with the predetermined threshold value _Ath by the comparison circuit 9. it can. The value of A _th can be set to LK when there is no noise, but it is necessary to set the value of A _{th to} a value smaller than LK in consideration of the effect of noise. At the beginning of the reception, the timing when t = 0, that is, since the demodulated signal and the fixed word are not synchronized, A ₁ (t) ≧
T = 0 is determined from the timing of _Ath . Once synchronization is achieved, the frame timing generator 5 outputs an aperture signal to the correlator 2 at the timing of t = 0. After that, the correlator 2 outputs according to the aperture signal. The comparison circuit 9 outputs to the selector switch 10 whether or not a slip is detected at every period LT. The selector switch 10 is set to A when no slip is detected.
_{1 The} demodulation phase estimated by the demodulation phase estimation circuit 3 from the value of (0) is output. On the other hand, when a slip is detected, the demodulation phase estimated based on the output of the second correlator 2 ^' is switched and output. The second correlator 2 ^′ outputs a correlation value A ₂ (t) for only K-bit fixed words in each period T. A ₂ (t) is

[0026]

(Equation 5) And when t = lt

[0027]

(Equation 6) Becomes The demodulation phase estimation circuit 3 ^' estimates the demodulation phase n from the value of A ₂ (lt). This time, the timing at which t = LT is supplied from the frame timing generator 5 to the second correlator 2 ^′, and the second correlator 2 ^′ outputs according to this timing.

When no slip of the demodulation phase occurs during the relatively long period LT, the apparatus according to the present invention is estimated based on the fixed word of the LK bit included during this period LT. The demodulation phase is output, and when a slip occurs, a demodulation phase estimated from a K-bit fixed word included in the shorter cycle T is output.

[0029]

When no slip occurs in a certain time period, the demodulation phase is detected with very high accuracy,
A correct demodulation phase can always be output even when a slip occurs.

[Brief description of the drawings]

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a transmission signal according to the embodiment of the present invention.

FIG. 3 illustrates a conventional example.

[Explanation of symbols]

Reference Signs List 1 demodulation signal input terminal 2, 2 ^' correlator 3, 3 ^' demodulation phase estimation circuit 4 demodulation phase output terminal 5 frame timing generator 6 absolute value circuit 7 slip detection circuit 8 slip detection output terminal 9 comparison circuit 10 selector switch n demodulation phase

Claims (2)

(57) [Claims] 1. A demodulation signal input terminal for inputting a PSK demodulation signal including a fixed word for phase detection, and a demodulation signal input from the demodulation signal input terminal for correlation by a long frame timing from a frame timing generator. A correlator for calculating, a demodulation phase estimating circuit for inputting a calculation result of the correlator and outputting a demodulation phase, an absolute value circuit for inputting a calculation result of the correlator and calculating an absolute value thereof, A demodulation phase detection device comprising: a slip detection circuit for receiving a calculation result of the value circuit to detect a demodulation phase slip; wherein the correlator includes correlation calculation means for coping with demodulation phase slip occurrence; A demodulation phase detecting device comprising: means for switching a demodulation phase output to an output for coping with the demodulation phase slip when a demodulation phase slip occurs. 2. The demodulation phase detecting device according to claim 1, wherein the correlation calculating means for coping with the occurrence of the demodulation phase slip includes a correlator with a short frame timing, separately from the correlator.