JPH09214345A - Circuit converting pulse width into digital value through the use of poly-phase interpolation - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the conversion circuit operated at a high processing speed. SOLUTION: A frequency divider circuit 12 applies 1/8 frequency division to a 1GHz clock signal from a crystal oscillator 10 to generate a clock whose frequency is 125MHz, it is fed to a 4-bit shift register circuit 14, in which the signal is shifted by a clock signal to generate 4-phase conversion clocks each having a phase difference of 1nS. A pulse width signal proportional to a measured analog value such as a peak level of a radiant ray is used to gate a conversion clock and a passing conversion clock is counted (100, 108, 110). A start/stop status latch circuit 16 16 fetches status information of 4-phase conversion clocks at start and stop of the pulse width signal. An arithmetic circuit 18 interpolates the count with the received status information of the 4-phase conversion clocks to calculate a digital value representing the pulse width of the pulse width signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion circuit for converting the pulse width of a pulse width signal into a digital value.

[0002]

2. Description of the Related Art A conversion circuit for converting the pulse width of a pulse width signal into a digital value is used, for example, in a Wilkinson type analog-to-digital converter which is used for wave height analysis of radiation. Specifically, the peak peak value of radiation is stored in a capacitor, and a constant pulse current is discharged by a constant current discharge circuit to obtain a pulse width signal proportional to the peak value, and the pulse width signal is input to the conversion circuit. The pulse width of the pulse width signal is converted into a digital value, and as a result, the peak value of the radiation is converted into a digital value.

FIG. 4 shows a conventional Wilkinson type analog-digital converter (hereinafter referred to as "converter (analog-to-analog)".
"Digital converter)" is called "ADC". ), Which is a circuit that constitutes the digital conversion unit, and is connected to a circuit that obtains a pulse width signal proportional to the peak value by accumulating the peak peak value of radiation in a capacitor and discharging it constantly in a constant current discharge circuit. Then, a conversion circuit for converting the pulse width of the pulse width signal into a digital value is schematically shown. The pulse width signal proportional to the crest value of the radiation generated as described above is input to the data input terminal of the D-type flip-flop 102 at the first stage of the synchronization circuit 100.
On the other hand, the conversion clock generated by the crystal oscillator (not shown) is input to the clock terminal of the D-type flip-flop 102. Q due to the known operation of the D flip-flop
The signal from the output is the D-type flip-flop 10 in the subsequent stage.
4 is input to the data input terminal. On the other hand, the above conversion clock is input to the clock terminal of the D-type flip-flop 104 via the inverter 106. Due to the known operation of the D-type flip-flop, a pulse width signal synchronized with the conversion clock is output from the Q output terminal of the D-type flip-flop 104. The synchronized pulse width signal and conversion clock are input to the AND gate 108. AN
In the D gate 108, the conversion clock is gated by the pulse width signal, and the conversion clock passing through the AND gate 108 is input to the scaler circuit 110. The pulse width of the pulse width signal is converted into a digital value by counting the conversion clock input by the scaler circuit 110. Since the pulse width of the pulse width signal is proportional to the crest value of the radiation, the crest value of the radiation is consequently converted into a digital value. The synchronizing circuit 100 is provided to synchronize the pulse width signal for opening and closing the gate with the conversion clock, and to provide a stable conversion operation. Therefore, it suffices that the pulse width signal and the conversion clock be synchronized, and the number of stages of the D-type flip-flop is not limited to two and may be one stage, three stages or more, and other configurations are also possible.

[0004]

In order to increase the speed of the conventional Wilkinson type ADC using such a conversion circuit, the easiest method is to raise the frequency of the conversion clock. In the D-type flip-flop which constitutes the synchronizing circuit for synchronizing the pulse width signal and the converted clock, the output becomes high depending on the input timing of the D signal of the flip-flop and the clock signal. (It is not fixed to 1 or 0 and becomes an intermediate state and becomes unstable operation), which causes deterioration of the characteristics of the ADC such that the counting result is not constant.

Therefore, the fastest Wilkinson type ADC that has been put to practical use up to now has a conversion clock of 450 MHz.
z. When such a fastest Wilkinson type ADC is used for the wave height analysis of radiation, the time required for conversion into a digital value is longest when the wave height value is maximum, and in this case, the conversion time is about 20 μS.

On the other hand, ADCs other than Wilkinson type
In this case, the conversion time of several μS has been achieved due to the progress of digital circuit technology in recent years, and the Wilkinson type ADC, which has a long conversion time, has been shunned due to demands such as the efficiency of radiation measurement.

However, in the case of ADCs other than the Wilkinson type ADC, the technical limit value is 13 bits (8k channels) as the number of bits converted into digital values, but in the case of the Wilkinson type ADC, this technical limit value is used. In addition, since there is no such problem, and the differential nonlinearity is excellent by one digit, the Wilkinson type ADC is required to be speeded up in a field requiring highly accurate measurement such as radiation analysis.

Although the problem has been described by using the Wilkinson type ADC as a typical example, generally, it is desired to speed up the conversion process of the conversion circuit for converting the pulse width of the pulse width signal into a digital value. .

Therefore, an object of the present invention is to provide a conversion circuit for converting the pulse width of a pulse width signal into a digital value, which has a high conversion speed.

[0010]

In order to achieve the above object, there is provided a means for gating a conversion clock with a pulse width signal and a means for counting the conversion clock passing through the gate. A conversion circuit of the present invention for converting a width into a digital value multiphases the conversion clock so as to have a phase difference of a cycle of a clock signal, and performs the multiphase conversion at a start time point and an end time point of the pulse width signal. It is characterized by further comprising processing means for calculating a digital value of the pulse width of the pulse width signal based on the clock state information and the count information of the converted clock from the counting means.

That is, in order to increase the speed of the present invention, as a speed-increasing method other than increasing the frequency of the conversion clock, a system which has an effect equivalent to the case where the frequency is increased by making the conversion clock multi-phased is obtained. Was devised.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an example of the configuration of a conversion circuit of the present invention for converting the pulse width of a pulse width signal into a digital value, to which the principle of the present invention is applied. Hereinafter, a case where the conversion circuit shown in FIG. 1 is used in a Wilkinson type ADC for wave height analysis of radiation will be described as an example. In FIG. 1, the elements designated by the same reference numerals as those in FIG. 4 indicate the same elements, and therefore the description will not be repeated. In FIG. 1, 10 is a crystal oscillator that generates a 1 GHz clock signal, and 12 is a frequency dividing circuit that divides the 1 GHz clock signal generated by the crystal oscillator 10 by 1/8 to generate a 125 MHz conversion clock. . The 125 MHz conversion clock generated by the frequency dividing circuit 12 is the first stage of the synchronization circuit 100 in the same manner as described with reference to FIG. 4 for the conversion circuit used in the digital conversion unit of the conventional Wilkinson type ADC. Is applied to the clock terminal of the D-type flip-flop 102 and to the clock terminal of the D-type flip-flop 104 in the subsequent stage through the inverter 106 and to the AND gate 108.

Further, in FIG. 1, 14 indicates a 4-bit shift register circuit, and the shift register circuit 14 is
The 125 MHz conversion clock input from the input frequency dividing circuit 12 is shifted by the 1 GHz clock signal applied from the crystal oscillator 10 to the clock terminal to convert the four-phase conversion clock signals (with a phase difference of 1 nS) ( Hereinafter, "four-phase clock") is generated. In FIG. 1, reference numeral 16 indicates a start / stop status latch circuit, and the start / stop status latch circuit 16 is a 1 nS generated by the shift register circuit 14.
In addition to receiving the four-phase clock having the phase difference of, the pulse width signal proportional to the peak value of the radiation is received as a latch signal, and the state information of the four-phase clock at the start and stop of the pulse width signal is fetched. In FIG. 1, 18 is a pulse width signal based on the count value from the scaler circuit 110 and the state information of the 4-phase clock at the start and stop of the pulse width signal from the start / stop status latch circuit 16. 7 shows an arithmetic circuit for calculating the pulse width of

Next, the operation of the conversion circuit of the present invention shown in FIG. 1 will be described with reference to the timing chart of FIG. The crystal oscillator 10 generates a 1 GHz clock having the waveform shown in FIG. In the frequency dividing circuit 12, the 1 GHz clock indicated by A generates a 1 / 8-divided converted clock indicated by B. The generated converted clock is input to the clock terminal of the D-type flip-flop 102 at the first stage of the synchronization circuit 100, and inverted and input to the clock terminal of the D-type flip-flop 104 at the subsequent stage via the inverter 106. A pulse width signal (in this case, a signal having a pulse width of 12 nS) shown in C of FIG. 2 which is proportional to the peak value of the radiation is the data input terminal of the D-type flip-flop 102 of the first stage of the synchronizing circuit 100. Entered in. Therefore, according to the known operation of the D-type flip-flop, from the Q output of the D-type flip-flop 104, as shown in FIG.
The pulse of the waveform shown in D of FIG. 2 is output and synchronized with the conversion clock shown in B of FIG. Figure 2 synchronized
The output pulse of the synchronizing circuit of D and the conversion clock of B are
When input to the ND gate 108, two conversion clocks pass through the AND gate 108 as shown by E in FIG. The gate passing clock of E of FIG. 2 is input to the scaler circuit 110 and counted, and as a result, the count value of the scaler circuit 110 becomes 2 in the case shown in FIG.

Since the clock is divided to obtain the converted clock, the count value of the scaler circuit 110 is n and the division number is k.
Then, the pulse width of the output pulse of the synchronization circuit shown in D of FIG. 2 may be obtained by multiplying n by k. In the present embodiment, since the converted clock is obtained by dividing the clock by 1/8, k is 8. Therefore, the output pulse width of the synchronizing circuit may be obtained by multiplying the obtained count value 2 by 8 to obtain 16 nS. To be

On the other hand, the pulse width shown in C and D of FIG. 2 of both the pulse width signal and the output pulse of the synchronizing circuit can be understood by referring to the waveform of the conversion clock shown in FIG. 2B. , The pulse width of the output pulse of the synchronization circuit is
The pulse width of the pulse width signal is shorter than the pulse width signal start time by the time from the start time of the pulse width signal to the first rising edge of the conversion clock (hereinafter referred to as "start interpolation value") Ta, while the pulse width signal stops from the start time. The time until the rising edge of the conversion clock (hereinafter referred to as "interpolation value at stop") Tb is long. Therefore, in order to obtain the pulse width of the pulse width signal, it is necessary to correct the subtraction of the stop interpolation value Tb by adding the start interpolation value Ta to the pulse width of the synchronization circuit output pulse.

Therefore, the pulse width P _W (n
S) can be calculated by the following equation.

[0019]

## EQU1 ## P _W = n × k + Ta−Tb

Next, the operation of the start interpolation value Ta and the circuit for obtaining the start interpolation value Ta will be described. The conversion clock shown in FIG. 2B is input to the 4-bit shift register circuit 14 from the frequency dividing circuit 12, and the shift register circuit 14 receives 1 nS with the 1 GHz clock from the crystal oscillator 10 shown in FIG. 2A. A four-phase clock having a phase difference of 4 is generated, and the four-phase clocks indicated by F1 to F4 in FIG. 2 are output to the start / stop status latch circuit 16. The start / stop status latch circuit 16 receives the pulse width signal shown in C of FIG. 2 as a latch signal, and the state information of the four-phase clock at each of the start time and the stop time, that is, F1 in FIG. The states at the time points T _S and T _E of the 1st to 4th phases of the 4-phase clock shown by F4 to F4 are fetched at the respective time points. The state information of the four-phase clocks fetched by the start / stop status latch circuit 16 at the time points T _S and T _E is sent to the arithmetic circuit 18.

The start interpolation value Ta and the stop interpolation value Tb can be obtained by converting the clock of the crystal oscillator 10 by the frequency dividing circuit 12 to obtain the converted clock. T _C (1G in this embodiment)
Hz to 1 nS), the minimum is 0 and the maximum is (k−
1) T _C (k is the above frequency division number). Therefore, it suffices to prepare a shift register circuit having the number of stages capable of expressing the frequency division number k. In the present embodiment, since the frequency division number k is 8, the shift register circuit 14 is a 4-bit shift register circuit. Therefore, the start / stop status latch circuit 1
Since the 4-phase clock status information fetched by 6 can always correspond one-to-one with the start-time interpolation value Ta and the stop-time interpolation value Tb, a table corresponding in advance is stored in the arithmetic circuit 18. For example, in the state information of the four-phase clocks shown in F1 to F4 at the start time T _S of the pulse width signal in FIG. 2, the start time interpolation value Ta is 1 nS, and F1 to F4 at the stop time T _E of the pulse width signal. It is assumed that the state information of the four-phase clock shown indicates that the interpolation value Tb at the time of stop corresponds to 5 nS.

Therefore, in the case shown in FIG.
The arithmetic circuit 18 receives the state information of the four-phase clock at the start time T _S and the state information of the four-phase clock at the stop time T _E from the start / stop status latch circuit 16, and sets the interpolation value Ta at the start to 1 nS and the stop value. The time interpolation value Tb is determined to be 5 nS.

The arithmetic circuit 18 also calculates the pulse width P _{W according} to the above equation. In the case shown in FIG. 2, the arithmetic circuit 1
8, the count value n = 2 from the scaler circuit 110,
Ta = 1nS and Tb = 5n determined by the arithmetic circuit 18
Using S, P _W is calculated as 2 × 8 + 1-5 = 12 nS.

In order to increase the speed of a conventional conversion circuit that converts the pulse width of a pulse width signal into a digital value, and to increase the speed of a conventional Wilkinson type ADC using the conversion circuit, the method of the present invention is adopted. Directly 1 GHz without using
When using as a conversion clock, the frequency of the metastable state is high in the D-type flip-flop of the synchronization circuit, and the duration of the metastable is irregular. Even when input, the output pulse width of the synchronizing circuit is not constant, which causes deterioration of differential nonlinearity. Since the influence of the metastable becomes larger as the frequency of the conversion clock becomes higher, the characteristics of the conversion circuit and the ADC become better when the frequency of the conversion clock is as low as possible. Therefore, according to the present invention, in order to achieve both the characteristics of the conversion circuit and ADC and high speed, the conversion clock is multiphased by a clock signal having a frequency higher than the conversion clock, and interpolation is performed by the multiphased signal. . In the above-mentioned embodiment, the conversion time of the 1 GHz Wilkinson type ADC is 8 μS at the maximum, and high-speed AD other than the Wilkinson type ADC is used.
Even when compared with C, it has achieved a sufficiently high speed.

The Wilkinson type ADC using the conversion circuit of the present invention is naturally characterized by the digital conversion unit after converting the analog value of the physical quantity, such as the crest value of the radiation, which continuously changes into a pulse width signal proportional thereto. Therefore, the experimental data is not the characteristics of the ADC as a whole, but the portion for converting the pulse width signal into the time data is shown below. The method for obtaining the experimental data is to generate a pseudo pulse width signal with a logic signal generator and input it to the pulse width signal input terminal 20 shown in FIG. 1 to change the pulse width of the pulse width signal from 98 nS to 101 nS. The operation is confirmed by collecting the frequency data obtained by the arithmetic circuit 18 when it is changed in 1 nS steps.

FIG. 3 shows the result. In FIG. 3, when the pulse width signal A is 98 nS,
B shows the frequency result in the case of 99 nS, C shows the case of 100 nS, and D shows the frequency result in the case of 101 nS. 3A to 3D, the occurrence frequencies of the frequency indicating the pulse width value of the pulse width signal under measurement and the frequency indicating a value 1 nS larger than that are similar to those of the conventional Wilkinson type ADC. Therefore, it can be seen from FIGS. 3A to 3D that the conversion circuit shown in FIG. 1 is normally operating with a time resolution of 1 nS.
A Wilkinson ADC of z is feasible.

The reason why the differential non-linearity of the Wilkinson type ADC is excellent is because of the circuit configuration of the digital conversion unit used, and more specifically, the measured analog value that continuously changes, such as the peak value of radiation, is measured. , Normalized by a conversion clock generated by an oscillator with a highly stable oscillation frequency such as a crystal oscillator, the digital values corresponding to the measured analog values such as peak values are the same as the period stability of a crystal oscillator. This is because it can have stability. In order to maintain such a system, in the embodiment shown in FIG. 1, the conversion clocks are multiphased using the clock of the crystal oscillator, whereby the respective phase differences can be standardized uniformly. Therefore, when the conversion circuit shown in FIG. 1 is applied to the Wilkinson type ADC, high speed can be realized while maintaining the excellent differential nonlinearity of the Wilkinson type ADC.

When high speed is required without requiring such differential nonlinearity depending on the application, the present invention uses a shift register circuit instead of a shift register circuit to multiphase the clock signal. A delay element such as a delay line may be used. When the delay line is used, the adjustment becomes complicated, and since the phases are independent of each other, the phase differences are not standardized uniformly, and the differential nonlinearity is lower than that of the shift register circuit. The element structure is simple.

The present invention is characterized in that the converted clocks have multiple phases, and the means for realizing the same is not limited to the shift register circuit and the delay line, and any one may be used.

As described above with reference to the preferred embodiment, the conversion circuit of the present invention for converting the pulse width of a pulse width signal into a digital value has a conversion clock having a phase difference of the cycle of the clock signal. As described above, the digital value of the pulse width of the pulse width signal is calculated based on the state information of the converted clock and the count information of the converted clock at the start time and the end time of the pulse width signal. It is possible to achieve higher speed than the conventional conversion circuit.

Further, the present invention is not limited to the field of radiation analysis which requires highly accurate measurement by realizing a high-speed conversion circuit, and up to now, ADCs other than the Wilkinson type have been used.
It is possible to utilize the Wilkinson type ADC using the conversion circuit of the present invention even in the field of using the. Further, as in the preferred embodiment of the present invention, by converting the conversion clock into multiple phases with a clock signal, highly accurate measurement can be performed in a shorter time than in the case of the ADC other than the Wilkinson type which has been used so far. It becomes possible.

[Brief description of drawings]

FIG. 1 shows an example of the configuration of a conversion circuit of the present invention for converting the pulse width of a pulse width signal into a digital value, to which the principle of the present invention is applied.

FIG. 2 shows a timing diagram for explaining the operation of the circuit shown in FIG.

FIG. 3 is a diagram showing a result of frequency data obtained when the pulse width of the pulse width signal is changed from 98 nS to 101 nS in 1 nS steps and input to the circuit shown in FIG. 1;

FIG. 4 is a circuit constituting a digital conversion unit of a conventional Wilkinson type analog-digital ADC, in which a peak value of radiation is stored in a capacitor, and the peak value is constantly discharged by a constant current discharging circuit. FIG. 3 is a diagram schematically showing a conversion circuit for converting the pulse width of the pulse width signal into a digital value, following the circuit for obtaining the pulse width signal proportional to

[Explanation of symbols]

 10: Crystal oscillator 12: Frequency divider circuit 14: Shift register circuit 16: Start / stop status latch circuit 18: Arithmetic circuit

Claims (3)

[Claims] 1. A circuit for converting a pulse width of a pulse width signal into a digital value, comprising: a means for gating the conversion clock with a pulse width signal; and a means for counting the conversion clock passing through the gate. The clock is multi-phased so as to have a phase difference of the cycle of the clock signal, and the status information of the multi-phased conversion clock at the start time and the end time of the pulse width signal and the counting of the conversion clock from the counting means A conversion circuit comprising processing means for calculating a digital value of the pulse width of the pulse width signal based on the information. 2. The conversion circuit according to claim 1, wherein the processing means includes a clock generation circuit that generates a clock signal, and a frequency division circuit that divides the generated clock signal to generate the conversion clock. A shift register circuit that multiphases the conversion clock generated by the frequency dividing circuit with the clock signal, and latches the states of the multiphase conversion clock at the start time and end time of the pulse width signal A status latch circuit; a start-time interpolated value indicating a start time of the pulse width signal and a start time of the conversion clock based on the state of the latched multi-phased conversion clock; and the pulse width signal. At the time of stop and at the time of stop, which determine the end time of the And interpolated value, converter, characterized in that it comprises a means for calculating a digital value of the pulse width of the pulse width signal based on the count value of the conversion clock from the means for counting. 3. The conversion circuit according to claim 1, wherein the conversion circuit converts an analog value of a continuously variable physical quantity into a pulse width signal, and converts the pulse width of the pulse width signal into a digital value. A conversion circuit for use in a Wilkinson type analog-to-digital converter.