JPH09213891A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely enable the operation of a lateral bipolar by making at least one part of the second conductivity type of second diffusion area exist between plural adjacent extended regions in the first diffusion area. SOLUTION: An element isolating area 203 being an insulating layer is made between n-type diffusion areas 201 and 202, and this isolates both electrically. At the time of application of high voltage such as static electricity, the lateral bipolar constituted of the three regions of an n-type diffusion are 201, a p-type well are, and an n-type diffusion area 202 operates by the breakdown of the diode between the n-type diffusion area 201 and the p-type well area. Therefore, an excessive current of static electricity application is discharged from an earth terminal to outside of the device. Moreover, between connection holes 211 and 213, by the load for the amount of resistance of the n-type diffusion area, voltage higher than the diode connected in parallel with the lateral bipolar in an inner circuit is applied to the diode between the n-type diffusion area 201 and the p-type well area, and the lateral bipolar operates.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device,
In particular, it relates to protection of internal circuits against high voltage application such as static electricity from the outside of the device.

[0002]

2. Description of the Related Art In a conventional semiconductor device, according to an input protection circuit disclosed in Japanese Patent Laid-Open No. 57-115854,
The two N type diffusion regions 801 and 802 shown in FIG. 8 are formed on the P type well region 803 by being electrically isolated from each other by the element isolation region, and the N type diffusion region 801 serves as an external connection terminal. The N type diffusion region 802 is connected to the ground terminal,
The P-type well region 803 is connected to the ground terminal via a P-type well electrode forming region 804 having a higher concentration than that of the P-type well region 803 by a conductive layer such as Al, Ti, W, or polycrystalline Si. Therefore, when positive static electricity is applied from the outside of the device, the potential of the P-type well region 803 increases due to the breakdown of the diode 821 formed by the N-type diffusion region 801 and the P-type well region 803. An NP composed of an N-type diffusion region 801, a P-type well region 803, and an N-type diffusion region 802.
The N-type lateral bipolar 822 operates, whereby an excessive current due to application of static electricity is discharged from the ground terminal 812 to the outside of the device through the conductive layer from the N-type diffusion region 802,
The internal circuit was protected against the application of static electricity from outside the device.

[0003]

However, in the semiconductor device according to the prior art described above, as shown in FIG. 9, the diode 9 that triggers the operation of the NPN lateral bipolar 910 connected to the external connection terminal 901 by the conductive layer is used.
When the breakdown voltage of 11 is higher or does not have a sufficient difference as compared with the breakdown voltage of the diode 912 between the internal circuit 920 which is the protected circuit and the ground terminal 902, positive static electricity from the outside of the device For application,
There is a possibility that the diode 912 will break down and the internal circuit 920 will be destroyed without the diode 911 breaking down. Therefore, the diode 911 is surely broken down and the NPN lateral bipolar 910 is operated. In order to secure sufficient electrostatic withstand voltage of, sacrifice the integration degree of the electrostatic protection area,
Between the lateral bipolar 910 and the internal circuit 920, it is necessary to separately insert an impurity diffusion region or 903 made of polycrystalline Si or the like.

Therefore, the present invention is intended to solve this problem, and its purpose is to increase the number of manufacturing steps and to complicate the manufacturing steps without increasing the number of manufacturing steps. By providing the diffusion area in the same area, there is no need to insert a resistor separately at the expense of the integration degree of the electrostatic protection area, the lateral bipolar is operated reliably, and high static electricity from the outside of the device is eliminated. This is to improve the breakdown voltage of the semiconductor device against the application of voltage.

[0005]

A semiconductor device according to the present invention comprises an input / output circuit for input / output interface with an external device, and a second conductivity type well region is provided in a first conductivity type well region in the input / output circuit. A first diffusion region and a second diffusion region of the second conductivity type are electrically separated from each other by an element isolation region, and a potential is supplied to the well region. In the semiconductor device having the first-conductivity-type well electrode forming region having a higher concentration than the first-conductivity-type well region, the second-conductivity-type first diffusion region has a plurality of locations extending in the first direction. The plurality of extended regions from the first connection holes arranged in the second direction orthogonal to the first direction to the external connection terminal in the region other than the plurality of extended regions. Inside from the second connection hole located inside And a second diffusion region of the second conductivity type, at least a part of which is present between the plurality of extended regions adjacent to each other of the first diffusion region. In addition, the first diffusion region of the second conductivity type has a plurality of extending in the first direction, the second connection arranged in the plurality of extended regions. The holes are connected to the external connection terminals, and the first connection holes arranged in the second direction orthogonal to the first direction in regions other than the plurality of extended regions are connected to the internal circuits by conductive layers. The second diffusion region of the second conductivity type is characterized in that at least a part thereof is present between the plurality of extended regions adjacent to each other of the first diffusion region, and The second diffusion region of the second conductivity type has an annular shape around the periphery. Having a first diffusion region of the second conductivity type, the first diffusion region of the second conductivity type of the annular, from the first connection hole arranged in a first direction along one side of the region. An external connection terminal, which faces the first connection hole with the second diffusion region and the element isolation region of the second conductivity type interposed therebetween and is arranged in a second direction orthogonal to the first direction. The second connection hole is connected to the internal circuit by a conductive layer.

[0006]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1, 2, 3, 4, 5, 6, and 7.

FIG. 1 is an overall view of a semiconductor device according to the present invention. In the semiconductor device according to the present invention, an input / output circuit and a power supply circuit connected to the outside of the device are provided in a peripheral region 102 on the surface of a semiconductor substrate 101. , And has a logic circuit in a region 103 inside thereof.

FIG. 2 is a plan view of the electrostatic protection circuit in the input / output circuit of the semiconductor device according to the first embodiment of the present invention, in which the P-type well region is present on the entire surface shown in FIG. The N type diffusion region 201 has two convex portions, and the conductivity of the lowermost layer made of Al, W, Ti, polycrystalline Si, etc. from the connection hole 211 in the region other than the convex portion of the N type diffusion region 201. Connected to the external connection terminal through the layer 221;
Connection hole 213 arranged in the convex portion of N type diffusion region 201
To the internal circuit via the lowermost conductive layer 223. The N-type diffusion region 202 is formed so that at least a part thereof exists between the convex portions of the N-type diffusion region 201, and the connection hole 212 for connecting the substrate and the lowermost conductive layer and the lowermost layer. The conductive layer 222, the connection hole 214 for connecting the lowermost conductive layer and the upper conductive layer, and the upper conductive layer 224 are connected to the ground terminal. The element isolation region 203, which is an insulating layer, is formed between the N-type diffusion regions 201 and 202 and electrically isolates the two. According to the protection circuit having such a configuration, when a high voltage such as static electricity from the outside of the device is applied, the breakdown of the diode between the N-type diffusion region 201 and the P-type well region triggers the N-type diffusion region 201. Diffusion region 201, P-type well region,
The lateral bipolar configured by the three regions of the N-type diffusion region 202 operates, and from the ground terminal to the outside of the device,
It emits excessive current due to the application of static electricity. Also, the connection hole 2
Since the resistance component of the N-type diffusion region 201 is loaded between 11 and 213, the diode between the N-type diffusion region 201 and the P-type well region is connected in parallel with the lateral bipolar in the internal circuit. A higher voltage is applied than the diode, and the lateral bipolar operates reliably.

FIG. 3 is a plan view of an electrostatic protection circuit in an input / output circuit in a semiconductor device according to a second embodiment of the present invention, in which a P-type well region is present on the entire surface shown in FIG. The electrostatic protection circuit shown in FIG. 3 has a plurality of electrostatic protection circuits in the input / output circuit of the semiconductor device of the first embodiment shown in FIG. It is a connection. N type diffusion region 3
01 has a plurality of protrusions, and the connection hole 311 in the region other than the protrusions of the N-type diffusion region 301 is connected via the lowermost conductive layer 321 made of Al, W, Ti, polycrystalline Si or the like. It is connected to an external connection terminal and is connected to an internal circuit through a connection hole 313 arranged in the convex portion of the N type diffusion region 301 through the lowermost conductive layer 323. The N type diffusion region 302 is
At least a part of the N-type diffusion region 301 is formed between the adjacent convex portions, and the connection hole 312 connects the substrate and the lowermost conductive layer, and the lowermost conductive layer 322. , The lowermost conductive layer and the upper conductive layer are connected to each other, and the upper conductive layer 324 is connected to the ground terminal. Element isolation region 30 which is an insulating layer
3 is formed between the N type diffusion regions 301 and 302,
The two are electrically separated. According to the protection circuit having such a configuration, when a high voltage such as static electricity is applied from the outside of the device, the breakdown of the diode between the N-type diffusion region 301 and the P-type well region is used as a trigger.
The lateral bipolar configured by the three regions of the diffusion region 301 of the type, the P-type well region, and the diffusion region 302 of the N type operates, and an excessive current due to the application of static electricity is discharged from the ground terminal to the outside of the device. Further, since the resistance component of the N-type diffusion region 301 is loaded between the connection holes 311, 313,
The diode between the N type diffusion region 301 and the P type well region receives a higher voltage than the diode connected in parallel with the lateral bipolar in the internal circuit, and the lateral bipolar operates reliably.

FIG. 4 is a plan view of the electrostatic protection circuit in the input / output circuit of the semiconductor device according to the third embodiment of the present invention, in which the P-type well region exists over the entire surface shown in FIG. The static electricity protection circuit shown in FIG. 4 is obtained by changing the wiring of the static electricity protection circuit in the input / output circuit of the semiconductor device according to the first embodiment shown in FIG. The N-type diffusion region 401 has two convex portions and is connected to an external connection terminal through the connection hole 411 arranged in the convex portion of the N-type diffusion region 401 via the lowermost conductive layer 421. From the connection hole 413 in the area other than the convex portion of the diffusion area 401 of
It is connected to the internal circuit through the lowermost conductive layer 423 made of l, W, Ti, polycrystalline Si or the like. The N-type diffusion region 402 is formed so that at least a part thereof exists between the convex portions of the N-type diffusion region 401, and the connection hole 412 for connecting the substrate and the lowermost conductive layer and the lowermost layer. The conductive layer 422, the connection hole 414 for connecting the lowermost conductive layer and the upper conductive layer, and the upper conductive layer 424 are connected to the ground terminal. Element isolation region 403 which is an insulating layer
Is formed between the N type diffusion regions 401 and 402, and electrically separates the two. According to the protection circuit having such a structure, when a high voltage such as static electricity is applied from the outside of the device, the breakdown of the diode between the N-type diffusion region 401 and the P-type well region is used as a trigger, and the N-type diffusion region 401 is triggered. Diffusion region 401, P-type well region, N-type diffusion region 4
The lateral bipolar configured by the three regions 02 operates and discharges an excessive current due to the application of static electricity from the ground terminal to the outside of the device. Further, since the resistance component of the N type diffusion region 401 is loaded between the connection holes 411 and 413, N
The diode between the diffusion region 401 of the mold and the P-type well region receives a higher voltage than the diode connected in parallel with the lateral bipolar in the internal circuit, and the lateral bipolar operates reliably.

FIG. 5 is a plan view of the electrostatic protection circuit in the input / output circuit of the semiconductor device according to the fourth embodiment of the present invention, in which the P-type well region exists on the entire surface shown in FIG. The electrostatic protection circuit shown in FIG. 5 is obtained by changing the wiring of the electrostatic protection circuit in the input / output circuit of the semiconductor device of the second embodiment shown in FIG. The N-type diffusion region 501 has a plurality of protrusions, and the Al from the connection hole 511 arranged in the protrusion of the N-type diffusion region 501 is Al,
The lowermost conductive layer 52 made of W, Ti, polycrystalline Si, or the like
N-type diffusion region 5 connected to the external connection terminal via 1
The connection hole 513 in the region other than the convex portion 01 is connected to the internal circuit through the lowermost conductive layer 523. The N-type diffusion region 502 is formed so that at least a part thereof exists between the adjacent convex portions of the N-type diffusion region 501, and the connection hole 512 for connecting the substrate and the lowermost conductive layer, and The lowermost conductive layer 522, the connection hole 514 connecting the lowermost conductive layer and the upper conductive layer, and the upper conductive layer 524 are connected to the ground terminal. The element isolation region 503, which is an insulating layer, is formed between the N type diffusion regions 501 and 502, and electrically isolates the two. According to the protection circuit having such a configuration, when a high voltage such as static electricity is applied from the outside of the device, the breakdown of the diode between the N-type diffusion region 501 and the P-type well region triggers an N-type diffusion region 501. Diffusion region 501, P-type well region,
The lateral bipolar configured by the three regions of the N-type diffusion region 502 operates, and from the ground terminal to the outside of the device,
It emits excessive current due to the application of static electricity. Also, the connection hole 5
Since the resistance component of the N-type diffusion region 501 is loaded between 11 and 513, the diode between the N-type diffusion region 501 and the P-type well region is connected in parallel with the lateral bipolar in the internal circuit. A higher voltage is applied than the diode, and the lateral bipolar operates reliably.

FIG. 6 is a plan view of an electrostatic protection circuit in an input / output circuit in a semiconductor device according to a fifth embodiment of the present invention, in which a P-type well region is present on the entire surface shown in FIG. The ring-shaped N-type diffusion region 601 has the connection hole 61.
1 to Al, W, Ti, polycrystalline Si, etc., which are connected to the external connection terminals by the lowermost conductive layer 621, and the connection hole 611.
Connection hole 61 arranged in a region facing the position where
3 to the lowermost conductive layer 623 to connect to the internal circuit. The N type diffusion region 602 is an annular N type diffusion region 6
It is surrounded by 01 and is electrically separated from the ring-shaped N-type diffusion region 601 by the element isolation region 603, and the connection hole 612, the lowermost conductive layer 622, and the lowermost conductive layer and the upper part. Connection hole 614 for connecting to the conductive layer
And is connected to the ground terminal via the conductive layer 624 on the upper side. According to the protection circuit having such a configuration, when a high voltage such as static electricity is applied from the outside of the device, the breakdown of the diode between the ring-shaped N-type diffusion region 601 and the P-type well region is used as a trigger. The lateral bipolar configured by the three regions of the N-type diffusion region 601, the P-type well region, and the N-type diffusion region 602 operates and discharges an excessive current due to the application of static electricity from the ground terminal to the outside of the device. Further, since the resistance component of the N-type diffusion region 601 is loaded between the connection holes 611 and 613, the diode between the N-type diffusion region 601 and the P-type well region has a lateral bipolar structure in the internal circuit. A higher voltage is applied than the diodes connected in parallel, and the lateral bipolar operates reliably.

FIG. 7 is a plan view of the electrostatic protection circuit in the input / output circuit of the semiconductor device according to the sixth embodiment of the present invention, in which the P-type well region exists on the entire surface shown in FIG. In the protection circuit shown in FIG. 7, the static electricity protection circuit in the input / output circuit of the semiconductor device of the fifth embodiment shown in FIG. 6 has a common area where the connection hole of the N type diffusion area 601 does not exist. , Which are connected in series. The N-type diffusion region 701 is formed from the connection hole 711 from Al, W, T
i, connected to the external connection terminal by the lowermost conductive layer 721 such as polycrystalline Si, and connected to the internal circuit by the lowermost conductive layer 723 from the connection hole 713 arranged in a region facing the position where the connection hole 711 exists. Connected. The plurality of N-type diffusion regions 702 are surrounded by N-type diffusion regions 701, respectively, and are electrically separated from the N-type diffusion regions 701 by the element isolation regions 703, so that the connection holes 712 are formed.
The lowermost conductive layer 722, the connection hole 714 for connecting the lowermost conductive layer and the upper conductive layer, and the upper conductive layer 724 are connected to the ground terminal. According to the protection circuit having such a configuration, when a high voltage such as static electricity is applied from the outside of the device, the ring-shaped N-type diffusion region 701 is formed.
The breakdown of the diode between the P-type well region and the P-type well region triggers the operation of the lateral bipolar formed by the three regions of the N-type diffusion region 701, the P-type well region and the N-type diffusion region 702, and the ground terminal. More excessive current is emitted to the outside of the device due to the application of static electricity. Further, since the resistance component of the N-type diffusion region 701 is loaded between the connection holes 711 and 713, the diode between the N-type diffusion region 701 and the P-type well region has a lateral bipolar structure in the internal circuit. A higher voltage is applied than the diodes connected in parallel, and the lateral bipolar operates reliably.

[0014]

According to the structure of the electrostatic protection circuit as described above, it is possible to reliably operate the lateral bipolar closest to the external connection terminal without disposing a resistor separately. As compared with the input / output circuit in the conventional semiconductor device having the same protection capability, the electrostatic breakdown voltage can be improved without lowering the degree of integration. Further, the number of steps of the semiconductor device is not increased and the steps are not complicated by adopting the present invention.

[Brief description of drawings]

FIG. 1 is an overall view of a semiconductor device according to the present invention.

FIG. 2 is a plan view of an electrostatic protection circuit in a semiconductor device which is a first embodiment according to the present invention.

FIG. 3 is a plan view of an electrostatic protection circuit in a semiconductor device that is a second embodiment according to the present invention.

FIG. 4 is a plan view of an electrostatic protection circuit in a semiconductor device which is a third embodiment according to the present invention.

FIG. 5 is a plan view of an electrostatic protection circuit in a semiconductor device according to a fourth embodiment of the present invention.

FIG. 6 is a plan view of an electrostatic protection circuit in a semiconductor device which is a fifth embodiment of the present invention.

FIG. 7 is a plan view of an electrostatic protection circuit in a semiconductor device which is a sixth embodiment according to the present invention.

FIG. 8 is a cross-sectional view of an electrostatic protection circuit in a semiconductor device according to a conventional technique.

FIG. 9 is a circuit diagram around an electrostatic protection circuit in a semiconductor device according to a conventional technique.

[Explanation of symbols]

 101: Semiconductor substrate 102: Input / output circuit area 103: Logic circuit area 201: N type diffusion area 202: N type diffusion area 203: Element isolation area 211: Connection hole between the substrate and the lowermost conductive layer 212: Substrate Hole between the substrate and the lowermost conductive layer 213: connection hole between the substrate and the lowermost conductive layer 214: connection hole between the lowermost conductive layer and the upper conductive layer 221: the lowermost conductive layer 222: the lowermost layer Conductive layer 223: bottom conductive layer 224: upper conductive layer 301: N type diffusion region 302: N type diffusion region 303: element isolation region 311: connection hole between substrate and bottom conductive layer 312: Connection hole between substrate and bottom conductive layer 313: Connection hole between substrate and bottom conductive layer 314: Connection hole between bottom conductive layer and top conductive layer 321: Bottom conductive layer 322: Max Lower conductive layer 323: bottom Conductive layer 324: upper conductive layer 401: N-type diffusion region 402: N-type diffusion region 403: element isolation region 411: connection hole between substrate and lowermost conductive layer 412: substrate and lowermost conductive layer Connection hole with 413: Connection hole between substrate and lowermost conductive layer 414: Connection hole with lowermost conductive layer and upper conductive layer 421: Lowermost conductive layer 422: Lowermost conductive layer 423: Lowest Lower conductive layer 424: Upper conductive layer 501: N-type diffusion region 502: N-type diffusion region 503: Element isolation region 511: Connection hole between substrate and lowermost conductive layer 512: Conductivity of substrate and lowermost layer Connection hole with layer 513: Connection hole between substrate and lowermost conductive layer 514: Connection hole between lowermost conductive layer and upper conductive layer 521: Lowermost conductive layer 522: Lowermost conductive layer 523: Lowermost conductive layer 524: Upper conductive layer 6 01: N-type diffusion region 602: N-type diffusion region 603: Element isolation region 611: Connection hole between substrate and lowermost conductive layer 612: Connection hole between substrate and lowermost conductive layer 613: Substrate and maximum Connection hole with lower conductive layer 614: Connection hole between lowermost conductive layer and upper conductive layer 621: Lower conductive layer 622: Lower conductive layer 623: Lower conductive layer 624: Upper conductive Layer 701: N-type diffusion region 702: N-type diffusion region 703: Element isolation region 711: Connection hole between substrate and lowermost conductive layer 712: Connection hole between substrate and lowermost conductive layer 713: Substrate and Connection hole with lowermost conductive layer 714: Connection hole between lowermost conductive layer and upper conductive layer 721: Lowermost conductive layer 722: Lowermost conductive layer 723: Lowermost conductive layer 724: Upper Conductive layer 801: N type diffusion region 802: N Diffusion region 803: P-type well region 804: P-type well electrode formation region 811: External connection terminal 812: Ground power supply terminal 813: Ground power supply terminal 821: Diode 822: Lateral bipolar 823: Resistance of P-type well region Component 901: External connection terminal 902: Ground power supply terminal 903: Resistance component of resistor 904: Resistance component of P-type well region 905: Resistance component of P-type well region 910: Lateral bipolar 911: Diode 912: Diode 920: Internal circuit

Claims (3)

[Claims] 1. An input / output circuit for input / output interface with an external device, wherein a first conductivity type well region in the input / output circuit is provided with a second diffusion type first diffusion region and the second conductivity type. The second diffusion region of the second conductivity type electrically separated from the first diffusion region of the type by the element isolation region, and the first conductivity type well region for supplying a potential to the well region, In a semiconductor device having a high-concentration first-conductivity-type well electrode formation region, the second diffusion-type first diffusion region is extended at a plurality of locations in the first direction,
The first connection holes arranged in the second direction orthogonal to the first direction in regions other than the plurality of extended regions to the external connection terminals are arranged in the plurality of extended regions. The second diffusion region of the second conductivity type is connected to the internal circuit from the second connection hole by a conductive layer, and at least a part of the second diffusion region of the second conductivity type is adjacent to the plurality of the first diffusion regions. A semiconductor device characterized by being present between extended regions. 2. An input / output circuit for input / output interface with an external device is provided, wherein a first conductivity type well region in the input / output circuit has a second diffusion type first diffusion region and the second conductivity type. The second diffusion region of the second conductivity type electrically separated from the first diffusion region of the type by the element isolation region, and the first conductivity type well region for supplying a potential to the well region, In a semiconductor device having a high-concentration first-conductivity-type well electrode formation region, the second diffusion-type first diffusion region is extended at a plurality of locations in the first direction,
From the second connection holes arranged in the plurality of extended regions to the external connection terminals, the second connection holes are arranged in a region other than the plurality of extended regions in a second direction orthogonal to the first direction. Is connected to the internal circuit from the first connection hole by a conductive layer, respectively, the second diffusion region of the second conductivity type, at least a portion thereof, the plurality of adjacent first diffusion region of the plurality of A semiconductor device characterized by being present between extended regions. 3. An input / output circuit for input / output interfacing with an external device, wherein a first conductivity type well region in the input / output circuit is provided with a second diffusion type first diffusion region and the second conductivity type. The second diffusion region of the second conductivity type electrically separated from the first diffusion region of the type by the element isolation region, and the first conductivity type well region for supplying a potential to the well region, In a semiconductor device having a high-concentration first conductivity type well electrode formation region, the second conductivity type second diffusion region has a ring-shaped second conductivity type first diffusion region in the periphery thereof, The second diffusion region of the first diffusion region of the first connection hole from the first connection hole arranged in the first direction along one side of the region to the external connection terminal, the first connection hole and the second conductivity type. Type second conductivity type opposed to each other with the second diffusion region and the element isolation region of the mold sandwiched therebetween. A semiconductor device, each of which is connected to an internal circuit from a second connection hole arranged in the first diffusion region of the semiconductor device by a conductive layer.