JPH09205768A - Synchronous rectifier circuit - Google Patents

Synchronous rectifier circuit

Info

Publication number
JPH09205768A
JPH09205768A JP1065296A JP1065296A JPH09205768A JP H09205768 A JPH09205768 A JP H09205768A JP 1065296 A JP1065296 A JP 1065296A JP 1065296 A JP1065296 A JP 1065296A JP H09205768 A JPH09205768 A JP H09205768A
Authority
JP
Japan
Prior art keywords
voltage
mosfet
transformer
terminal
rectifying
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1065296A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Watanabe
一芳 渡辺
Minoru Hirata
稔 平田
Shinichi Kuwabara
真一 桑原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Hitachi Information Technology Co Ltd
Original Assignee
Hitachi Ltd
Hitachi Communication Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Communication Systems Inc filed Critical Hitachi Ltd
Priority to JP1065296A priority Critical patent/JPH09205768A/en
Publication of JPH09205768A publication Critical patent/JPH09205768A/en
Pending legal-status Critical Current

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  • Rectifiers (AREA)
  • Dc-Dc Converters (AREA)

Abstract

PROBLEM TO BE SOLVED: To stably operate a converter by conducting a MOSFET for rectification only when the voltage at the control terminal of a control circuit installed to the gate terminal of the MOSFET is higher than the voltage at the output terminal. SOLUTION: An output voltage stabilizing control circuit 6 constantly maintains the output voltage Vo across terminals 11 and 12. When an electric current continuously flows to a choke coil 9, the waveform of the voltage Vs across the terminals 14 and 17 of the secondary winding of a transformer 5 becomes rectangular. The transformer 5 generates a voltage Vs (Vs=Ns/Np×Vi, where Ns/Np and Vi respectively represent the winding ratio and primary-side input voltage of the transformer 5) from the secondary side. A forward voltage is applied to the parasitic diode 15 of a MOSFET 7 and the potentials at the drain and source becomes equal to each other. When the current flowing to the choke coil 9 becomes zero, the conduction of a commutation-side diode 8 is completed and the bias voltage Vd between the MOSFET control terminal 14 and the terminal 12 rises, resulting in the turning off of the MOSFET 7. Therefore, the occurrence of an excessively large current and an excessively high voltage can be prevented.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は整流用MOSFET
同期整流コンバータの改良に関することで、特にコンバ
ータの正常動作維持に関する。
TECHNICAL FIELD The present invention relates to a rectifying MOSFET.
The present invention relates to improvement of a synchronous rectification converter, and particularly to maintaining normal operation of the converter.

【0002】[0002]

【従来の技術】図4に示すようなDC・DCコンバータ
等の電圧変換回路において、主スイッチ4は、出力端子
11の電圧が一定に保たれるようパルス幅変調された出
力電圧安定化制御回路6からの信号により駆動される。
主スイッチ4の動作と同期してトランス5の1次巻線間
には矩形波状の電圧が加わって、トランスの作用により
2次巻線側にも矩形波状の電圧が発生する。これをMO
SFET7とダイオード8から成る整流素子、チョーク
コイル9、コンデンサ10から成る平滑回路によって整
流・平滑し、平均化された電圧を得る。MOSFET7
とダイオード8はそれぞれ主スイッチ4がオン状態の
時、オフ状態の時に対応して導通する。
2. Description of the Related Art In a voltage conversion circuit such as a DC / DC converter as shown in FIG. 4, a main switch 4 is an output voltage stabilization control circuit whose pulse width is modulated so that the voltage of an output terminal 11 is kept constant. Driven by the signal from 6.
A rectangular wave voltage is applied between the primary windings of the transformer 5 in synchronization with the operation of the main switch 4, and a rectangular wave voltage is also generated on the secondary winding side by the action of the transformer. This is MO
A smoothing circuit including a rectifying element including the SFET 7 and the diode 8, a choke coil 9, and a capacitor 10 rectifies and smoothes the voltage to obtain an averaged voltage. MOSFET7
And the diode 8 respectively conduct when the main switch 4 is in the on state and in the off state.

【0003】[0003]

【発明が解決しようとする課題】ここで整流素子として
用いている整流用MOSFET7の制御は、トランス5
の2次巻線間に現れる電圧に同期して行われる。直流電
源1の変動や出力端子11につながる負荷の変動等によ
り出力端子11の電圧が上昇し、これを検出する安定化
制御回路6からの信号が主スイッチ4の停止を指示する
と、チョークコイル9の電流は徐々に減少し、この電流
がゼロ付近になると転流用ダイオード8の導通も終了す
る。すると、出力コンデンサ10に蓄積された電荷によ
り維持される出力端子11の電圧によって、整流用MO
SFET7をオンにするようなバイアス電圧がゲート・
ソース間に発生し、出力端子11からトランス5の2次
側に向かっての逆方向電流が発生する。この逆方向電流
はトランス5とチョークコイル9を異常に励磁してつい
には飽和状態に至って、MOSFET7や主スイッチ4
に過大電流が流る。またトランスリセット時には、異常
に励磁されたトランスが持つエネルギによって、主スイ
ッチや整流用MOSFETに過大電圧が加わる場合があ
る。
The rectifying MOSFET 7 used as the rectifying element is controlled by the transformer 5 as follows.
Is performed in synchronization with the voltage appearing between the secondary windings of the. When the voltage of the output terminal 11 rises due to the fluctuation of the DC power supply 1 or the fluctuation of the load connected to the output terminal 11, and the signal from the stabilization control circuit 6 that detects this causes the main switch 4 to stop, the choke coil 9 Current gradually decreases, and when the current becomes close to zero, the conduction of the commutation diode 8 also ends. Then, by the voltage of the output terminal 11 maintained by the charges accumulated in the output capacitor 10, the rectifying MO
A bias voltage that turns on SFET7
A reverse current is generated between the sources and flows from the output terminal 11 to the secondary side of the transformer 5. This reverse current abnormally excites the transformer 5 and the choke coil 9 and finally reaches a saturation state, and the MOSFET 7 and the main switch 4
Excessive current flows to. Further, when the transformer is reset, an excessive voltage may be applied to the main switch and the rectifying MOSFET due to the energy of the transformer that is abnormally excited.

【0004】この問題点に対して、前記整流用MOSF
ETが必要外にオン状態となることを防止し、入力電圧
の変動や出力端子につながる負荷の変動等に対してもM
OSFET7や主スイッチ4に負担をかけず、安定に動
作するコンバータを提供する。
To solve this problem, the rectifying MOSF is used.
ET is prevented from being turned on unnecessarily, and M is applied to fluctuations in the input voltage and fluctuations in the load connected to the output terminal.
Provide a converter that operates stably without imposing a burden on the OSFET 7 and the main switch 4.

【0005】[0005]

【課題を解決するための手段】上記の課題を達成するた
めに、本発明の実施形態は図1に示すような、整流用M
OSFET7のゲート端子に制御回路13を設け、この
端点を新たな整流用MOSFET7の制御端子14とす
る。制御回路13は、出力端子11の電圧よりも制御端
子14の電圧が高いことを条件として導通状態になり、
この導通状態と同期して前記整流用MOSFETが制御
されることを特徴とする。これにより整流用MOSFE
T7がオン状態となるのは、チョークコイル9の電流が
出力端子11に向かって増加する電流が流れるときに限
定され、前述の逆方向電流は発生しないことになる。
In order to achieve the above-mentioned object, an embodiment of the present invention has a rectifying M as shown in FIG.
The control circuit 13 is provided at the gate terminal of the OSFET 7, and this end point is used as the control terminal 14 of the new rectifying MOSFET 7. The control circuit 13 becomes conductive on condition that the voltage of the control terminal 14 is higher than the voltage of the output terminal 11,
The rectifying MOSFET is controlled in synchronization with the conductive state. This allows rectifying MOSFE
T7 is turned on only when the current of the choke coil 9 increases toward the output terminal 11, and the reverse current described above does not occur.

【0006】図1において取り付けた制御回路13は整
流用MOSFET7がオン状態になる制御端子14の電
圧を引き上げ、同期動作の乱れを除去する。
The control circuit 13 attached in FIG. 1 raises the voltage of the control terminal 14 at which the rectifying MOSFET 7 is turned on to eliminate the disturbance of the synchronous operation.

【0007】[0007]

【発明の実施の形態】図2は本発明を1石式フォワード
コンバータにて実施した回路例であり、制御回路として
ツェナーダイオード18を用いた場合である。ツェナー
ダイオード18はある一定の電圧以上にて導通する性質
を持つため、整流用MOSFET7がオン状態になる制
御端子14の電圧を引き上げる効果がある。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an example of a circuit in which the present invention is implemented in a one-stone type forward converter, in which a Zener diode 18 is used as a control circuit. Since the Zener diode 18 has a property of conducting at a certain voltage or more, it has an effect of raising the voltage of the control terminal 14 at which the rectifying MOSFET 7 is turned on.

【0008】出力端子電圧Vo(11,12端子間電
圧)は出力電圧安定化制御回路6により一定に保たれて
いる。チョークコイル9の電流が連続して流れている場
合には、トランス5の2次巻線間の電圧Vs(14、1
7端子間電圧)は矩形波状であり、トランス5の巻線比
を1次側:2次側=Np:Ns、1次側入力電圧(2,
3端子間電圧)をViとすると、 Vs=Ns/Np×Vi の電圧が発生する。整流用MOSFET7の寄生ダイオ
ード15には順方向電圧が加わってこれが導通するた
め、整流用MOSFET7のドレイン・ソース間の電位
はほぼ等しくなり、従って整流用MOSFET制御端子
14のバイアス電圧Vd(14,12端子間電圧)はV
sに等しい。フォワード式コンバータでは、主スイッチ
4がオンの時Vdは出力電圧Voよりも高く、ツェナー
ダイオード18を取付け後の整流用MOSFET7がオ
ン状態となる条件のVd>Voを満たすので、従来のツ
ェナーダイオードを取り付けていない場合と整流用MO
SFET7の動作は等しい。
The output terminal voltage Vo (voltage between terminals 11 and 12) is kept constant by the output voltage stabilization control circuit 6. When the current of the choke coil 9 continuously flows, the voltage Vs (14, 1,
The voltage between the 7 terminals is a rectangular wave, and the winding ratio of the transformer 5 is set to the primary side: the secondary side = Np: Ns, the primary side input voltage (2,
When the voltage between the three terminals) is Vi, a voltage of Vs = Ns / Np × Vi is generated. Since a forward voltage is applied to the parasitic diode 15 of the rectifying MOSFET 7 to make it conductive, the potential between the drain and source of the rectifying MOSFET 7 becomes substantially equal, and therefore the bias voltage Vd (14, 12) of the rectifying MOSFET control terminal 14 is made. The voltage between terminals is V
equal to s. In the forward converter, Vd is higher than the output voltage Vo when the main switch 4 is on, and Vd> Vo, which is the condition for turning on the rectifying MOSFET 7 after the zener diode 18 is attached, satisfies the conventional zener diode. MO not installed and rectifying MO
The operation of SFET 7 is equal.

【0009】一方、チョークコイル9の電流がゼロにな
れば、転流側ダイオード8の導通も終了し、整流用MO
SFET制御端子14のバイアス電圧Vd(14,12
端子間電圧)は上昇する。しかし、ツェナーダイオード
18の作用により整流用MOSFET7がオン状態とな
る条件はVd>Voであり、チョークコイル9に逆方向
電流が流れ得る状態で整流用MOSFET7がオンにな
ることはない。
On the other hand, when the current of the choke coil 9 becomes zero, the conduction of the commutation side diode 8 also ends, and the rectifying MO
Bias voltage Vd (14, 12) of the SFET control terminal 14
The voltage between terminals) rises. However, the condition that the rectifying MOSFET 7 is turned on by the action of the Zener diode 18 is Vd> Vo, and the rectifying MOSFET 7 is not turned on in the state where a reverse current can flow in the choke coil 9.

【0010】抵抗16は、ツェナーダイオード18にツ
ェナー電圧以下の電圧が加わったときの微少な漏れ電流
に対して整流用MOSFET7を確実にオフ状態とする
と共に、軽負荷時にトランス5と主スイッチMOSFE
T4の出力容量による共振によってトランス5の2次側
に発生する振動する電圧波形により整流用MOSFET
7がオン状態になった場合に対して、整流用MOSFE
Tのゲート・ソース間の寄生容量に蓄積された電荷を放
出して速やかにこれをオフ状態にさせる効果がある。
The resistor 16 surely turns off the rectifying MOSFET 7 against a minute leakage current when a voltage equal to or lower than the Zener voltage is applied to the Zener diode 18, and at the time of light load, the transformer 5 and the main switch MOSFE.
Rectification MOSFET due to an oscillating voltage waveform generated on the secondary side of the transformer 5 due to resonance caused by the output capacitance of T4.
For the case where 7 is turned on, rectifying MOSFE
There is an effect that the charge accumulated in the parasitic capacitance between the gate and the source of T is discharged to quickly turn it off.

【0011】図3は本発明を1石式フォワードコンバー
タにて実施した回路例であり、制御回路としてnチャネ
ル型のMOSFET19を用いた場合である。MOSF
ET19は整流用MOSFET制御端子14のバイアス
電圧Vd(14,12端子間電圧)を抵抗20,21に
よって分圧されるMOSFET19のゲート端子に加わ
る電圧により制御される。Vd>Vo時にMOSFET
19がオン状態になるように抵抗20,21の値を定め
れば、前述の前記制御回路としてツェナーダイオードを
用いた場合と整流用MOSFETの動作内容は同一であ
る。
FIG. 3 shows an example of a circuit in which the present invention is implemented in a one-stone type forward converter, in which an n-channel MOSFET 19 is used as a control circuit. MOSF
The ET 19 is controlled by a voltage applied to the gate terminal of the MOSFET 19 that divides the bias voltage Vd (voltage between terminals 14 and 12) of the rectifying MOSFET control terminal 14 by the resistors 20 and 21. MOSFET when Vd> Vo
If the values of the resistors 20 and 21 are determined so that 19 is turned on, the operation content of the rectifying MOSFET is the same as that when the Zener diode is used as the control circuit.

【0012】[0012]

【発明の効果】本発明によればチョークコイルの逆方向
電流は防止されて、トランスとチョークコイルが異常に
励磁されることは無くなる。これにより、主スイッチや
整流用MOSFETの過大電流を防止し、トランスリセ
ット時も主スイッチや整流用MOSFETに過大電圧が
加わることなくコンバータは安定に動作可能となる。
According to the present invention, the reverse current of the choke coil is prevented so that the transformer and the choke coil are not abnormally excited. As a result, an excessive current in the main switch and the rectifying MOSFET is prevented, and the converter can operate stably without applying an excessive voltage to the main switch and the rectifying MOSFET even when the transformer is reset.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の同期整流コンバータの実施例の回路
図。
FIG. 1 is a circuit diagram of an embodiment of a synchronous rectification converter of the present invention.

【図2】本発明の同期整流コンバータの実施例の半導体
回路図。
FIG. 2 is a semiconductor circuit diagram of an embodiment of the synchronous rectification converter of the present invention.

【図3】本発明の同期整流コンバータの実施例の半導体
回路図。
FIG. 3 is a semiconductor circuit diagram of an embodiment of a synchronous rectification converter of the present invention.

【図4】従来の同期整流コンバータの実施例の半導体回
路図。
FIG. 4 is a semiconductor circuit diagram of an example of a conventional synchronous rectification converter.

【符号の説明】[Explanation of symbols]

1…直流電源、 2…直流電源入力端子、 3…入力側グラウンド端子、 4…主スイッチ、 5…トランス、 6…出力電圧安定化制御回路、 7…同期整流用n型MOSFET、 8…ダイオード、 9…チョークコイル、 10…コンデンサ、 11…出力端子、 12…出力側グラウンド端子、 13…整流用MOSFET制御用回路、 14…整流用MOSFET制御端子、 15…MOSFETの寄生ダイオード。 1 ... DC power supply, 2 ... DC power supply input terminal, 3 ... Input side ground terminal, 4 ... Main switch, 5 ... Transformer, 6 ... Output voltage stabilization control circuit, 7 ... Synchronous rectification n-type MOSFET, 8 ... Diode, 9 ... Choke coil, 10 ... Capacitor, 11 ... Output terminal, 12 ... Output side ground terminal, 13 ... Rectification MOSFET control circuit, 14 ... Rectification MOSFET control terminal, 15 ... MOSFET parasitic diode.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 桑原 真一 神奈川県横浜市戸塚区戸塚町180番地日立 通信システム株式会社内 ─────────────────────────────────────────────────── --- Continuation of the front page (72) Inventor Shinichi Kuwahara 180 Totsuka-cho, Totsuka-ku, Yokohama-shi, Kanagawa Hitachi Communication Systems Co., Ltd.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】直流電圧をスイッチング素子により矩形波
パルスに変換してトランスの1次側に加えると前記トラ
ンスの2次側に現れる電圧を利用して整流用MOSFE
Tの制御を行うコンバータ回路において、出力電圧より
も2次側電圧が高い時に前記整流用MOSFETがオン
状態になるように設定された制御用回路を整流用MOS
FETのゲート端子に接続したことを特徴とする同期整
流回路。
1. A rectifying MOSFE utilizing the voltage appearing on the secondary side of the transformer when a DC voltage is converted into a rectangular wave pulse by a switching element and applied to the primary side of the transformer.
In a converter circuit for controlling T, a rectifying MOS is used as a control circuit set so that the rectifying MOSFET is turned on when the secondary voltage is higher than the output voltage.
A synchronous rectification circuit characterized by being connected to a gate terminal of an FET.
【請求項2】前記整流用MOSFETの制御用回路とし
てツェナーダイオードを用いた請求項1に記載の同期整
流回路。
2. The synchronous rectification circuit according to claim 1, wherein a Zener diode is used as a control circuit for the rectification MOSFET.
【請求項3】前記整流用MOSFETの制御用回路とし
てnチャネル型MOSFETを用いた請求項1に記載の
同期整流回路。
3. The synchronous rectification circuit according to claim 1, wherein an n-channel MOSFET is used as a control circuit for the rectification MOSFET.
JP1065296A 1996-01-25 1996-01-25 Synchronous rectifier circuit Pending JPH09205768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1065296A JPH09205768A (en) 1996-01-25 1996-01-25 Synchronous rectifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1065296A JPH09205768A (en) 1996-01-25 1996-01-25 Synchronous rectifier circuit

Publications (1)

Publication Number Publication Date
JPH09205768A true JPH09205768A (en) 1997-08-05

Family

ID=11756163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1065296A Pending JPH09205768A (en) 1996-01-25 1996-01-25 Synchronous rectifier circuit

Country Status (1)

Country Link
JP (1) JPH09205768A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000048301A1 (en) * 1999-02-09 2000-08-17 Ntt Data Corporation Power supply
US6717635B2 (en) * 2000-06-29 2004-04-06 Hitachi, Ltd. Liquid crystal display device with a light guide having random v-shaped dots
WO2018135119A1 (en) * 2017-01-23 2018-07-26 Ntn株式会社 Switching power supply

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000048301A1 (en) * 1999-02-09 2000-08-17 Ntt Data Corporation Power supply
US6717635B2 (en) * 2000-06-29 2004-04-06 Hitachi, Ltd. Liquid crystal display device with a light guide having random v-shaped dots
WO2018135119A1 (en) * 2017-01-23 2018-07-26 Ntn株式会社 Switching power supply

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