JPH09205589A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image pickup device in which the dynamic range is expanded without generating fixed pattern noise resulting from unevenness of saturated charge amounts Qs of each picture element. SOLUTION: Each light receiving section 1 is divided into two light receiving areas 12a, 12b whose sensitivity differs from each other, among signal charges read from the two light receiving areas 12a, 12b of each light receiving section 1, signal charges of the light receiving areas with the same sensitivity in adjacent light receiving sections are mixed in vertical transfer registers 2-1-2-n and the mixed charges are transferred vertically and the signal charges in the light receiving areas with different sensitivity are transferred separately horizontally while being distributed to two horizontal transfer registers 3, 4 by a distribution transfer gate 5, the charges are converted into a signal voltage by charge detection sections 6, 7 and the converted voltage is fed to an external signal processing circuit 30, in which the signal with higher sensitivity is clipped and the resulting signal is added to a signal at a lower sensitivity to obtain a video signal output.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a so-called wide dynamic range CCD (Charge Coupled Device) having a wide dynamic range with respect to an optical input.
ce) A solid-state imaging device.

[0002]

2. Description of the Related Art In a CCD solid-state image pickup device, after signal charges photoelectrically converted and accumulated in each pixel (light receiving portion) two-dimensionally arranged in a matrix overflow from the pixel, a signal output based on this signal charge is output. Is constant, a signal output corresponding to the amount of incident light above the saturation level of the pixel cannot be obtained, and therefore the dynamic range for the optical input is narrow.

In order to expand this dynamic range, as shown in FIG. 18, two types of pixels having different sensitivities,
For example, the high-sensitivity pixels 101 and the low-sensitivity pixels 102 are alternately arranged adjacent to each other in the vertical direction, and the signal charges of the high-sensitivity pixels 101 are read out to the vertical transfer register 103 after a limiter is applied in the pixels. In 103, the signal charges of the high sensitivity pixel 101 and the signal charges of the low sensitivity pixel 102 are mixed and then vertically transferred, and further horizontally transferred by the horizontal transfer register 104 and supplied to the charge detection unit 105, where an electrical signal is generated. There is a solid-state image pickup device having a configuration in which the data is converted into the image data and output through the buffer 106 (see, for example, Japanese Patent Laid-Open No. 3-117281).

In such a CCD solid-state image pickup device, when the amount of incident light exceeds a certain amount, the signal charge of the high-sensitivity pixel 101 is subject to a limiter.
By mixing the signal charge of 1 and the signal charge of the low-sensitivity pixel 102, the polygonal line approximation input / output characteristics shown in FIG. 19 are obtained, and thereby a wide dynamic range is realized.

[0005]

However, in the conventional CCD solid-state image pickup device having the above-mentioned structure in which the limiter is applied to each pixel in the high-sensitivity pixel 101, the overflow characteristic varies from pixel to pixel in reality. Since the unevenness of the saturated charge amount Qs of each pixel is large, an offset occurs in the input / output characteristics of the polygonal line approximation as shown in FIG. Therefore, when the incident light amount is such that the high-sensitivity pixel 101 is saturated, there is a problem that fixed pattern noise (fixed pattern unevenness) occurs in the image due to large unevenness of the saturated charge amount Qs of each pixel.

Therefore, according to the present invention, the saturated charge amount Q of each pixel is
An object of the present invention is to provide a solid-state imaging device capable of expanding a dynamic range without generating fixed pattern noise due to unevenness of s.

[0007]

A solid-state image pickup device according to the present invention is composed of a plurality of light-receiving regions which are at least divided into two by a channel stop region, have independent openings, and have different sensitivities, and are two-dimensionally arranged in a matrix. Of the plurality of light receiving portions arranged, and among the signal charges read from each of the plurality of light receiving regions that are arranged in each vertical row of the plurality of light receiving portions, A plurality of vertical transfer registers that mix and vertically transfer the signal charges of the light-receiving areas of the same sensitivity, and receive the signal charges of the light-receiving areas of different sensitivities that are sequentially transferred by the plurality of vertical transfer registers separately and horizontally. A plurality of horizontal transfer registers for transferring, and a plurality of charge detection units for detecting the signal charges transferred by the plurality of horizontal transfer registers and converting the signal charges into electric signals Among the output signals of the plurality of charge detection units, at least the output signal based on the signal charge other than the signal charge of the light receiving region of the minimum sensitivity is clipped, and based on the clipped signal and the signal charge of the light receiving regions of other sensitivities. And a signal processing circuit for adding and outputting the output signal.

In the solid-state image pickup device having the above-described structure, the sensitivities of the plurality of light receiving regions of the respective light receiving portions are different from each other, so that the amount of charges photoelectrically converted in each light receiving region is different for the same incident light. From these light receiving portions, the signal charges of each of the plurality of light receiving regions are read out to the vertical transfer register for each light receiving portion. Of the read signal charges, the signal charges in the light receiving regions of the same sensitivity of the adjacent light receiving sections are mixed in the vertical transfer register and then transferred vertically, and further received by the plurality of horizontal transfer registers with different sensitivities. The signals are distributed corresponding to the regions and horizontally transferred separately, and converted into electric signals by the charge detection unit. Then, in the signal processing circuit, among the output signals of the charge detection unit, at least the output signal based on the signal charge other than the signal charge of the light-receiving region of the minimum sensitivity is clipped, and then the signal charge of the light-receiving region of another sensitivity is clipped. Is added to the output signal.

Another solid-state image pickup device according to the present invention comprises a plurality of light receiving regions which are at least divided into two by a channel stop region, have openings independently of each other, and have different sensitivities, and which are two-dimensionally arranged in a matrix. One light receiving section, and among the signal charges arranged in each vertical row of the plurality of light receiving sections and read out from each of the plurality of light receiving areas for each light receiving section, light reception of the same sensitivity of adjacent light receiving sections A plurality of vertical transfer registers that mix the signal charges of the regions and perform vertical transfer, and a plurality of vertical transfer registers that separately receive the signal charges of the light receiving regions with different sensitivities that are sequentially transferred by the plurality of vertical transfer registers and horizontally transfer the signal charges. Of the horizontal transfer registers and the signal charges transferred by the plurality of horizontal transfer registers other than the signal charges of at least the light receiving region of the minimum sensitivity. Clip has a configuration and an output unit for outputting by mixing the signal charges of the light receiving region of the clip signal charges and other sensitivity.

In the other solid-state image pickup device having the above-mentioned structure, as in the case of the solid-state image pickup device described above, among the signal charges read from each of the plurality of light-receiving regions for each light-receiving part, the light-receiving part adjacent to each other receives light. The signal charges in the light-receiving areas having the same sensitivity are mixed in the vertical transfer registers and then transferred vertically, and further distributed to a plurality of horizontal transfer registers corresponding to the light-receiving areas having different sensitivities and separately transferred horizontally. Then, in the output section, at least the signal charges other than the signal charges in the light-receiving region having the minimum sensitivity are clipped among the horizontally transferred signal charges, and then mixed with the signal charges in the light-receiving regions having other sensitivities.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention. In FIG. 1, a plurality of light receiving portions (pixels) 1 for converting incident light into signal charges having a charge amount corresponding to the light amount and accumulating the signal charges are arranged in a matrix.
It is arranged three-dimensionally. These light receiving portions 1 are composed of, for example, two light receiving regions 12a and 12b divided into two by a channel stop region 11.

In these two light receiving regions 12a and 12b,
As shown in FIG. 2, an opening 13 for taking in incident light is provided.
a and 13b are provided independently. Openings 13a, 13
The opening areas Sa and Sb of b are different from each other.
<Sb is set. As a result, the light receiving region 12b having a larger opening area receives a larger amount of light with respect to the same incident light, so that the light receiving region 12b has higher sensitivity than the light receiving region 12a. Further, by disposing the on-chip lens 14 only on the light receiving region 12b on the high sensitivity side, the difference in sensitivity is further increased.

In this example, the two light receiving regions 12a,
In order to make the sensitivity of 12b different, openings 13a, 13b
The opening areas Sa and Sb are made different from each other, and the on-chip lens 14 is arranged only on the side with higher sensitivity.
It is possible to give a difference in sensitivity between the two light receiving regions 12a and 12b only by making the opening areas Sa and Sb different or by disposing the on-chip lens 14 on only one of them. Further, a color filter is arranged on the two light receiving regions 12a and 12b so that the transmittance of each color filter is different, or the film thickness of the laminated film on the two light receiving regions 12a and 12b is changed so that the transmittance is different. It is also possible to give a difference in sensitivity to the two light receiving regions 12a and 12b by changing the setting.

For each light receiving section 1 having the above-mentioned structure, n vertical transfer registers 2-1 to 2-n are arranged for each vertical column. The plane pattern of the vertical transfer registers 2-1 to 2-n is shown in FIG.
FIG. 4 shows the cross section along line XX ′. In FIGS. 3 and 4, a channel stop region 22 is formed along the transfer channel 21. Further, above the transfer channel 21, a polysilicon (1Poly, 2Po) layer of the first layer, the second layer, and the third layer is formed via a gate insulating film (SiO ₂ ) 23.
The transfer electrodes 24, 25, and 26 made of (ly, 3Poly) are repeatedly arranged in the transfer direction in the order of transfer electrode 24 → transfer electrode 26 → transfer electrode 25.

The vertical transfer registers 2-1 to 2-n having the above structure
Are driven by, for example, 6-phase vertical transfer clocks φV1 to φV6. This 6-phase vertical transfer clock φV1
φV6 is a unit of three transfer electrodes 24, 26, 25 provided corresponding to one light-receiving unit 1 and two adjacent pixels in the vertical transfer direction are paired. Given as.

That is, the first corresponding to one of the light receiving portions 1
The vertical transfer clock φV1 of the first phase is applied to the transfer electrode 24 of the layer.
However, the vertical transfer clock φV2 of the second phase is applied to the transfer electrode 26 of the third layer, and the vertical transfer clock φV3 of the third phase is applied to the transfer electrode 25 of the second layer.
The vertical transfer clock φV4 of the fourth phase is applied to the transfer electrode 24 of the first layer, the vertical transfer clock φV5 of the fifth phase is applied to the transfer electrode 26 of the third layer, and the transfer electrode 25 of the second layer corresponding to The vertical transfer clock φV6 of the sixth phase is applied. The vertical transfer clocks .phi.V1 to .phi.V6 have three-valued levels, which allows the three transfer electrodes 24, 25, 26 to be transferred.
The signal charge can be read out from any of the electrodes.

In the vertical transfer registers 2-1 to 2-n, among the signal charges read in sequence from each of the two light receiving regions 12a and 12b for each light receiving portion 1, the adjacent light receiving portions having the same sensitivity are detected. The signal charges in the light receiving region are mixed with each other. At this time, the signal charges in the light receiving regions with different sensitivities are
The vertical transfer registers 2-1 to 2-n are alternately arranged. Then, the vertical transfer registers 2-1 to 2-n transfer the mixed signal charges in the vertical direction while sequentially shifting them in a part of the horizontal blanking period. Read out this signal charge,
Specific operations of the mixing and vertical transfer will be described in detail later.

Two light receiving regions 12a and 12b having different sensitivities are provided in front of the transfer direction of the vertical transfer registers 2-1 to 2-n.
Two horizontal transfer registers 3 and 4 are arranged in correspondence with. These two horizontal transfer registers 3 and 4 are driven by two-phase horizontal transfer clocks φH1 and φH2, and are transferred in order from the vertical transfer registers 2-1 to 2-n for one line of a light receiving area having different sensitivities. The signal charges are separately received and sequentially transferred in the horizontal direction in the horizontal scanning period after the horizontal blanking period.

For example, in the horizontal transfer register 3 on the side of the vertical transfer registers 2-1 to 2-n, signals for two pixels obtained by mixing the signal charges of the low-sensitivity light receiving regions 12a of the adjacent light receiving sections 1 are obtained. The charges are sequentially transferred, and the other horizontal transfer register 4 sequentially transfers the signal charges of two pixels obtained by mixing the signal charges of the high-sensitivity light receiving regions 12b of the adjacent light receiving units 1. The signal charges are distributed to the two horizontal transfer registers 3 and 4 by
It is performed by the distribution transfer gate 5 arranged in between.

That is, as shown in FIG. 5, the signal charges transferred from the vertical transfer registers 2-1 to 2-n to one horizontal transfer register 3 pass through the channel region 51 controlled by the distribution transfer gate 5. And is transferred to the other horizontal transfer register 4. The distribution transfer gate 5 is open / close controlled by a distribution gate pulse φHHG. A channel stop portion 52 is formed on both sides of the channel region 51 to prevent charge transfer from the corresponding horizontal transfer register 3 to the horizontal transfer register 4.

Specifically, in FIG. 5, when the signal charge for the low-sensitivity light receiving area 12a is indicated by a circle and the signal charge for the high-sensitivity light receiving area 12b is indicated by a ●, the signal charge is indicated by a circle. When transferred from the vertical transfer registers 2-1 to 2-n to the horizontal transfer register 3, the horizontal transfer is performed in the horizontal transfer register 3 as it is. On the other hand, when the signal charge  is transferred from the vertical transfer registers 2-1 to 2-n to the horizontal transfer register 3, it is further transferred to the horizontal transfer register 4 via the channel region 51 by the distribution transfer gate 5, and is directly transferred to the horizontal transfer register. 4 is transferred horizontally.

At the ends of the transfer destinations of the horizontal transfer registers 3 and 4, charge detecting units 6 and 7 having a floating diffusion amplifier configuration are provided, respectively. The charge detectors 6 and 7 detect the signal charges horizontally transferred by the horizontal transfer registers 3 and 4 and convert the signal charges into a signal voltage. These two signal voltages are output to the outside as signal outputs OUT1 and OUT2 via the buffers 8 and 9. The timing generator 10 generates various timing signals such as the 6-phase vertical transfer clocks φV1 to φV6, the 2-phase horizontal transfer clocks φH1 and φH2, and the distribution gate pulse φHHG.

Of the two signal outputs OUT1 and OUT2, the signal output OUT1 is a signal voltage based on the signal charge of the low sensitivity light receiving region 12a, and the signal output OUT2 is a signal voltage based on the signal charge of the high sensitivity light receiving region 12b. Is. The signal outputs OUT1 and OUT2 are supplied to the external signal processing circuit 30. FIG. 6 shows an example of a specific circuit configuration of the signal processing circuit 30.

In FIG. 6, the signal output OUT1 is sampled and held by the sample and hold (S / H) circuit 31, and then sliced at a predetermined slice level E1 by the slice circuit 32. The output signal of the slice circuit 32 is amplified by the video amplifier 33 and becomes one input of the adder 34. The signal output OUT2 is sampled and held by the sample and hold circuit 35, and the clip circuit 3
After being clipped to a predetermined clip level E2 at 6, it becomes the other input of the adder 34. The adder 34 adds both the input signals to obtain a video output signal. FIG. 7 shows the characteristics of the video output signal with respect to the amount of incident light.

As described above, the highly sensitive light receiving region 12b
Output signal based on the signal charge of a predetermined clip level E
After being clipped to 2, it is added with an output signal based on the signal charge of the low-sensitivity light receiving region 12a sliced at a predetermined slice level E1 and amplified by the video amplifier 33, and is derived as a video output. Since the output signal based on the signal charge of the high-sensitivity light receiving region 12b is clipped at the common clip level E2, it is possible to suppress the occurrence of the fixed pattern unevenness in the image due to the characteristic variation between pixels. .

In the pixel arrangement, each light receiving portion 1 is divided into two, and low sensitivity light receiving areas 12a and high sensitivity light receiving areas 12b are alternately arranged in the vertical transfer direction. The CCD solid-state imaging device according to FIG.
As shown in FIG. 8, the high sensitivity pixel 101 and the low sensitivity pixel 10
This is conceptually the same as the conventional CCD solid-state imaging device having a configuration in which 2 and 2 are alternately arranged in the vertical transfer direction. However, the present embodiment is characterized by the configuration in which one light receiving portion (pixel) 1 is divided by the channel stop region 11.

As described above, one light receiving portion 1 is divided by the channel stop region 11, and the low sensitivity light receiving regions 12a and the high sensitivity light receiving regions 12b are alternately arranged in the vertical transfer direction. Fine processing of pixels becomes possible. This makes it possible to increase the number of pixels of the CCD solid-state imaging device and reduce the size thereof.

Further, by mixing the signal charges of the light receiving regions having the same sensitivity between two pixels (light receiving portions) adjacent to each other in the vertical transfer direction, the resolution in the vertical direction is reduced to half. The field reading and the frame reading can be realized.

The specific operations of reading, mixing and vertical transfer of the signal charges from the two light receiving regions 12a and 12b will be described below for the case of field reading and the case of frame reading. In the vertical transfer registers 2-1 to 2-n shown in FIG. 3, the 6-phase vertical transfer clock φ
V1 to φV6 have three-valued levels as described above. That is, three levels of a high level (hereinafter referred to as “H” level), an intermediate level (hereinafter referred to as “M” level), and a low level (hereinafter referred to as “L” level) are taken. The signal charges can be read from any of the transfer electrodes 24, 25, and 26.

First, the operation of the odd field in the field reading will be described with reference to the timing chart of FIG. 8 and the operation explanatory diagram of FIG. First,
Vertical transfer clock φV in the vertical blanking period
When 3 and φV6 become the “H” level, the potential under the transfer electrode 25 of the second layer becomes deep in each of the two adjacent pixels, so that the signal charge accumulated in the highly sensitive light receiving region 12b (in the figure, The circles (the same applies hereinafter) are read out under the transfer electrode 25 (t = t1). At this time,
Vertical transfer clocks φV1, φV2, φV4 and φV5
Are both at "L" level.

After that, the vertical transfer clocks φV3 and φV4
And .phi.V5 sequentially transit to "L" level through "M" level. That is, the vertical transfer clock φV3 is “H”.
The level transits to the "M" level, and after a certain period of time, transits to the "L" level. Next, the vertical transfer clock φV
4 shifts from the "L" level to the "M" level within the "M" level period of the vertical transfer clock φV3, and further shifts to the "L" level after a predetermined time. Subsequently, the vertical transfer clock φV5 transits from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV4, and further transits to the “L” level after a predetermined time.

Thus, the vertical transfer clocks φV3 and φ
V4 and φV5 go through “M” level in order to “L”
By changing to the level, the vertical transfer clock φV3
The signal charges under the transfer electrode 25 to which is applied are vertically transferred. At this time, since the vertical transfer clock φV6 is continuously at the “M” level, the vertical transfer clock φV5
At the transition from "M" level to "L" level (t =
At t2), the signal charges transferred from below the transfer electrode 25 to which the vertical transfer clock φV3 is applied are transferred to below the transfer electrode 25 to which the vertical transfer clock φV6 is applied, so that high voltage is generated between two adjacent pixels. The signal charges on the sensitivity side are mixed with each other.

Next, the vertical transfer clocks φV2 and φV
When “4” becomes the “H” level, the potential under the transfer electrode 26 of one of the third layers and the transfer electrode 24 of the other first layer of the two pixels becomes deep, so that the light is accumulated in the low-sensitivity light receiving region 12 a. A signal charge (indicated by an X mark in the figure and the same applies hereinafter) is read out under the transfer electrodes 26 and 24 (t = t).
3). At this time, the vertical transfer clocks φV1, φV3 and φV5 are all at the “L” level, and the vertical transfer clock φV6 is at the “M” level.

After that, the vertical transfer clocks φV2 and φ
V3 sequentially transits to the "M" level and then to the "L" level. That is, the vertical transfer clock φV2 transits from the "H" level to the "M" level, and further transits to the "L" level after a fixed time. Next, the vertical transfer clock φV3 transits from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV2, and further transits to the “L” level after a fixed time.

In this way, the vertical transfer clocks φV2 and φV3 sequentially transit to the “L” level via the “M” level, so that the signal charges under the transfer electrode 26 to which the vertical transfer clock φV2 is applied. Transferred vertically. At this time, since the vertical transfer clock φV4 continues to be at the “M” level, when the vertical transfer clock φV3 transits from the “M” level to the “L” level (t = t4),
The signal charge transferred from below the transfer electrode 26 to which the vertical transfer clock φV2 is applied is transferred to below the transfer electrode 24 to which the vertical transfer clock φV4 is applied, so that the signal on the low sensitivity side between the two adjacent pixels. The charges are mixed together.

In this state, the signal charges of the light-receiving regions of the same sensitivity mixed in the two adjacent pixels in the vertical direction, that is, the signal charges on the high sensitivity side and the signal charges on the low sensitivity side ×
And will be alternately arranged for each line. After that, the line transfer period starts and vertical transfer is performed.
In FIG. 1, the signal charge x on the low sensitivity side is transferred to the horizontal transfer register 3 and the signal charge ◯ on the high sensitivity side is transferred to the horizontal transfer register 4 via the horizontal transfer register 3 and the distribution transfer gate 5 in line units. And then transferred horizontally.

Next, the operation of the even field in the field reading will be described with reference to the timing chart of FIG. 10 and the operation explanatory diagram of FIG.
Vertical transfer clock φV in the vertical blanking period
When 3 and φV6 become the “H” level, the potential under the transfer electrode 25 of the second layer becomes deeper in each of two adjacent pixels, so that the signal charge accumulated in the highly sensitive light receiving region 12b is transferred. Read under (t = t
5). At this time, the vertical transfer clocks φV1, φV2, φ
Both V4 and φV5 are at "L" level.

After that, the vertical transfer clocks φV6 and φV1
And φV2 sequentially transit to the “M” level and then to the “L” level. That is, the vertical transfer clock φV6 is “H”.
The level transits to the "M" level, and after a certain period of time, transits to the "L" level. Next, the vertical transfer clock φV
1 shifts from the "L" level to the "M" level within the "M" level period of the vertical transfer clock φV6, and further shifts to the "L" level after a predetermined time. Subsequently, the vertical transfer clock φV2 transitions from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV1, and further transits to the “L” level after a certain period of time.

Thus, the vertical transfer clocks φV6 and φ
V1 and φV2 go through “M” level in order to “L”
By transitioning to the level, the signal charge under the transfer electrode 25 to which the vertical transfer clock φV6 is applied is vertically transferred. At this time, since the vertical transfer clock φV3 is continuously at the “M” level, the vertical transfer clock φV2
At the transition from "M" level to "L" level (t =
At t6), the signal charges transferred from below the transfer electrode 25 to which the vertical transfer clock φV6 is applied are transferred to below the transfer electrode 25 to which the vertical transfer clock φV3 is applied, so that a combination different from the case of the odd field is obtained. In, the signal charges on the high sensitivity side are mixed between two adjacent pixels.

Next, the vertical transfer clocks φV1 and φV
5 becomes "H" level, the transfer electrode 24 of one first layer and the transfer electrode 26 of the other third layer of two adjacent pixels are adjacent to each other.
Since the potential below is deepened, the signal charges accumulated in the low-sensitivity light receiving region 12a are read out below the transfer electrodes 24 and 26 (t = t7). At this time, vertical transfer clocks .phi.V2, .phi.V4 and .phi.V6 are all at "L" level, and vertical transfer clock .phi.V3 is at "M" level.

After that, the vertical transfer clocks φV5 and φ
V6 sequentially transits to the "M" level and then to the "L" level. That is, the vertical transfer clock φV5 transits from the "H" level to the "M" level, and further transits to the "L" level after a fixed time. Next, the vertical transfer clock φV6 transits from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV5, and further transits to the “L” level after a predetermined time.

As described above, the vertical transfer clocks φV5 and φV6 sequentially transit to the “L” level via the “M” level, so that the signal charge under the transfer electrode 26 to which the vertical transfer clock φV5 is applied is changed. Transferred vertically. At this time, since the vertical transfer clock φV1 is continuously at the “M” level, when the vertical transfer clock φV6 transits from the “M” level to the “L” level (t = t8),
The signal charges transferred from below the transfer electrode 26 to which the vertical transfer clock φV5 is applied are transferred to below the transfer electrode 24 to which the vertical transfer clock φV1 is applied, so that the adjacent 2 in a combination different from the case of the odd field. Signal charges on the low sensitivity side are mixed between pixels. After that, the line shift period starts, and vertical transfer and horizontal transfer are performed as in the case of odd fields.

Next, the operation of the odd field in frame reading will be described with reference to the timing chart of FIG. 12 and the operation explanatory diagram of FIG. First, in the vertical blanking period, when the vertical transfer clock φV6 becomes the “H” level, the potential under the second-layer transfer electrodes 25 of every other pixel in the vertical direction becomes deeper, so that the high-sensitivity light receiving region 12b is formed. The accumulated signal charges are read out below the transfer electrode 25 every other pixel (t = t1). At this time, the vertical transfer clocks φV1 to φV
Both V5 are at "L" level.

After that, the vertical transfer clocks φV6 and φV1
And φV2 sequentially transit to the “M” level and then to the “L” level. That is, the vertical transfer clock φV6 is “H”.
The level transits to the “M” level, and further transits to the “L” level after a fixed time. Next, the vertical transfer clock φV
1 shifts from the "L" level to the "M" level within the "M" level period of the vertical transfer clock φV6, and further shifts to the "L" level after a predetermined time. Subsequently, the vertical transfer clock φV2 transitions from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV1, and further transits to the “L” level after a certain period of time.

In this way, the vertical transfer clocks φV6 and φ
V1 and φV2 go through “M” level in order to “L”
Vertical transfer clock φV6
The signal charges under the transfer electrode 25 to which is applied are vertically transferred. At this time, since the vertical transfer clock φV3 is at the “M” level, when the vertical transfer clock φV2 changes from the “M” level to the “L” level (t = t2),
The signal charges transferred from below the transfer electrode 25 to which the vertical transfer clock φV6 is applied are transferred to below the transfer electrode 25 to which the vertical transfer clock φV3 is applied and are accumulated there.

Next, when the vertical transfer clock .phi.V5 becomes "H" level, the high-sensitivity light-receiving region 12 read out previously.
Since the potential under the transfer electrode 26 of the third layer of the pixel of b becomes deep, the signal charge accumulated in the low-sensitivity light receiving region 12a of the pixel is read out under the transfer electrode 26 (t = t3). At this time, the vertical transfer clocks φV1, φ
Both V2 and φV4 are at “L” level, and the vertical transfer clocks φV3 and φV6 are both at “M” level.

When the vertical transfer clock φV5 becomes "M" level, the potential below the transfer electrode 26 to which the vertical transfer clock φV5 is applied and the potential below the transfer electrode 25 to which the vertical transfer clock φV6 is applied are the same. Therefore, the signal charge x read out from the low-sensitivity light receiving region 12a becomes the level,
Stored under 5. Then, the vertical transfer clock φV5
Becomes "L" level, the potential under the transfer electrode 26 becomes shallow, and the signal charge of the low-sensitivity light receiving region 12a ×
Are stored under the transfer electrode 25 (t = t4).

In this state, 1 in the vertical direction.
The high-sensitivity-side signal charges ◯ and the low-sensitivity-side signal charges × read out for each pixel are alternately arranged for each line. After that, the line transfer period starts and vertical transfer is performed. In FIG. 1, the signal charge x on the low sensitivity side is transferred to the horizontal transfer register 3 and the signal charge ◯ on the high sensitivity side is transferred to the horizontal transfer register 4 via the horizontal transfer register 3 and the distribution transfer gate 5 in line units. Is
After that, it is transferred horizontally.

Next, the operation of the even field in the frame reading will be described with reference to the timing chart of FIG. 14 and the operation explanatory diagram of FIG. First, in the vertical blanking period, when the vertical transfer clock φV3 becomes “H” level, the potential under the transfer electrode 25 of the second layer of the pixel shifted by one line from the case of the odd field becomes deep, so that the sensitivity is high. The signal charges accumulated in the light receiving region 12b are read out below the transfer electrode 25 every other pixel (t = t5). At this time, the vertical transfer clocks φV1, φV2, φV4, φV5 and φV6 are all at the “L” level.

After that, the vertical transfer clocks φV3 and φV4
And .phi.V5 sequentially transit to "L" level through "M" level. That is, the vertical transfer clock φV3 is “H”.
The level transits to the "M" level, and after a certain period of time, transits to the "L" level. Next, the vertical transfer clock φV
4 shifts from the "L" level to the "M" level within the "M" level period of the vertical transfer clock φV3, and further shifts to the "L" level after a predetermined time. Subsequently, the vertical transfer clock φV5 transits from the “L” level to the “M” level within the “M” level period of the vertical transfer clock φV4, and further transits to the “L” level after a predetermined time.

Thus, the vertical transfer clocks φV3, φ
V4 and φV5 go through “M” level in order to “L”
By changing to the level, the vertical transfer clock φV3
The signal charges under the transfer electrode 25 to which is applied are vertically transferred. At this time, since the vertical transfer clock φV6 is at the “M” level, when the vertical transfer clock φV5 transits from the “M” level to the “L” level (t = t6),
The signal charges transferred from below the transfer electrode 25 to which the vertical transfer clock φV3 is applied are transferred to below the transfer electrode 25 to which the vertical transfer clock φV6 is applied, and are accumulated there.

Next, when the vertical transfer clock .phi.V2 becomes "H" level, the high-sensitivity light-receiving region 12 read previously.
Since the potential under the transfer electrode 26 of the third layer of the pixel of b becomes deep, the signal charge accumulated in the low-sensitivity light receiving region 12a of the pixel is read out under the transfer electrode 26 (t = t7). At this time, the vertical transfer clocks φV1, φ
Both V4 and φV5 are at “L” level, and the vertical transfer clocks φV3 and φV6 are both at “M” level.

When the vertical transfer clock φV2 becomes "M" level, the potential below the transfer electrode 26 to which the vertical transfer clock φV2 is applied and the potential below the transfer electrode 25 to which the vertical transfer clock φV3 is applied are the same. Therefore, the signal charge x read out from the low-sensitivity light receiving region 12a becomes the level,
Stored under 5. Then, the vertical transfer clock φV2
Becomes "L" level, the potential under the transfer electrode 26 becomes shallow, and the signal charge of the low-sensitivity light receiving region 12a ×
Are stored under the transfer electrode 25 (t = t8). Or later,
In the line shift period, vertical transfer and horizontal transfer are performed as in the case of odd fields.

FIG. 16 is a schematic block diagram showing another embodiment of the present invention. In the figure, the same parts as those in FIG. 1 are designated by the same reference numerals. In FIG. 16, 2 in matrix form
Each of the light receiving parts 1 arranged in a dimension is composed of two light receiving regions 12a and 12b having different sensitivities, and among the signal charges read from the two light receiving regions 12a and 12b of each light receiving part 1, they are adjacent to each other. The signals of the light-receiving areas of the light-receiving unit having the same sensitivity are mixed in the vertical transfer registers 2-1 to 2-n and vertically transferred, and are also distributed to the two horizontal transfer registers 3 and 4 by the distribution transfer gate 5 and separately. The configuration up to the horizontal transfer to is exactly the same as in the case of the previous embodiment.

The following points are different from the above embodiment. That is, in the present embodiment, the limiter 61 is provided beside the output end of the horizontal transfer register 7 that horizontally transfers the signal charges of the high-sensitivity light receiving region 12b, and the two horizontal transfer registers 3 and 4 are provided. The charge detector 62 and the buffer 63 are commonly provided. The charge detection unit 62 has, for example, a floating diffusion amplifier configuration, and has a low-sensitivity light receiving region 12a horizontally transferred by the horizontal transfer register 3.
And the signal charges of the high-sensitivity light-receiving region 12b horizontally transferred by the horizontal transfer register 4 and clipped by the limiter 61, and both signal charges are mixed and converted into a signal voltage for output.

FIG. 17 shows an example of a concrete structure of the limiter 61 in a section taken along the line YY 'of FIG. In FIG. 17, the horizontal CCD channel 65 is formed by the N-type impurity layer formed on the surface side of the P-type well region 64, and the horizontal transfer electrode 67 is arranged on the horizontal CCD channel 65 via the gate insulating film 66. The output end of the horizontal transfer register 4 is configured. The adjacent the output end of the horizontal transfer register 4, N ^- overflow barrier 68 and the drain 69 of N-type impurity layer made of type impurity layer is provided, the overflow barrier 68 and the drain 6
A limiter 61 is composed of 9. Drain 6
A predetermined DC voltage E0 is applied to 9.

In the limiter 61 having the above structure, the overflow barrier 68 is changed depending on the concentration of the N ^-- type impurity layer.
The height of the potential of is determined, and the height of this potential becomes the clip level. Then, in the horizontal transfer register 4, when the signal charges of the high-sensitivity light-receiving region 12b are sequentially transferred and accumulated in the packet beside the limiter 61, if the amount of the charges exceeds the clip level, the excess charges are charged. Is discarded into the drain 69, and a limiter is applied to the signal charge in the highly sensitive light receiving region 12b. In FIG. 17, the transfer direction of the horizontal transfer register 4 is a direction perpendicular to the paper surface.

As described above, the CCD according to this embodiment
In the solid-state imaging device, two light receiving regions 1 are provided for each light receiving unit 1.
Of the signal charges read from each of 2a and 12b,
The signals of the light-receiving areas of the same sensitivity of the adjacent light-receiving sections are mixed in the vertical transfer registers 2-1 to 2-n and vertically transferred, and are distributed to the two horizontal transfer registers 3 and 4 by the distribution transfer gate 5. And separately horizontally transfer the signal charges in the high-sensitivity light receiving region 12b.
Then, the floating diffusion capacitance of the charge detection unit 62 is mixed with the signal charge of the low-sensitivity light-receiving region 12a, so that a common limiter for each signal charge of the high-sensitivity light-receiving region 12b is obtained. 61
Since the limiter is applied in, it is possible to suppress the occurrence of unevenness of the fixed pattern in the image due to the characteristic variation between pixels.

In the present embodiment, the limiter 61 is used to limit the signal charge of the highly sensitive light receiving area 12b in the horizontal transfer register 7; however, the highly sensitive light receiving area is provided in the charge detecting portion 62. It is also possible to apply a limiter to the signal charge of 12b.

That is, two horizontal transfer registers 3 and 4
To the charge detection unit 62, the signal charges of the low-sensitivity light-receiving region 12a and the signal charges of the high-sensitivity light-receiving region 12b are alternately transferred in a form in which the high-sensitivity side is preceded by the charge detection unit 62. Then, as a reset pulse for resetting the floating diffusion capacitance, a ternary level including a clamp level is set, and at the clamp level, the high-sensitivity side signal charge transferred earlier from the horizontal transfer register 4 is clipped. The signal charge on the low sensitivity side transferred from the horizontal transfer register 3 may be mixed, converted into a signal voltage, and output.

In each of the above embodiments, the case where each light receiving portion 1 is divided into two light receiving regions having different sensitivities has been described, but the present invention is not limited to two divisions.
It is also possible to divide it into three or more light receiving regions having different sensitivities. In this case, since the horizontal transfer register also needs to separately transfer the signal charges corresponding to the respective sensitivities, the number corresponding to the number of divisions of the light receiving region is required. In addition, the limiter may be applied to at least signal charges other than the signal charges in the light-receiving region having the minimum sensitivity or signals based on the signal charges.

[0062]

As described above, according to the present invention,
Each light receiving part is divided into a plurality of light receiving regions with different sensitivities, and among the signal charges read from each of the plurality of light receiving regions for each light receiving part, the signal charges of the light receiving regions of the same sensitivity of the adjacent light receiving parts are Are mixed in the vertical transfer register for vertical transfer, and the signal charges in the light-receiving areas with different sensitivities are separately transferred horizontally in a plurality of horizontal transfer registers. , Or by clipping the signal based on it, and by mixing or adding the signal charge of the light-receiving area of other sensitivity or the signal based on it, and outputting it, each signal charge on the high sensitivity side or the signal based on it On the other hand, since the clamp is performed at the common clamp level, the fixed pattern noise caused by the unevenness of the saturated charge amount Qs of each pixel is not generated. It becomes possible to expand the dynamic range.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention.

FIG. 2 is a schematic configuration diagram showing an example of a configuration of a light receiving unit.

FIG. 3 is a plan pattern diagram showing an example of a configuration of a vertical transfer register.

FIG. 4 is a sectional view taken along line XX ′ of FIG.

FIG. 5 is a schematic configuration diagram showing an example of a distribution transfer gate.

FIG. 6 is a block diagram showing an example of a signal processing circuit.

FIG. 7 is an input / output characteristic diagram according to the present embodiment.

FIG. 8 is a timing chart of odd fields in field reading.

FIG. 9 is an explanatory diagram of an odd field operation in field reading.

FIG. 10 is a timing chart of even fields in field reading.

FIG. 11 is an explanatory diagram of an even field operation in field reading.

FIG. 12 is a timing chart of odd fields in frame reading.

FIG. 13 is an explanatory diagram of an odd field operation in frame reading.

FIG. 14 is a timing chart of even fields in frame reading.

FIG. 15 is an explanatory diagram of an even field operation in frame reading.

FIG. 16 is a schematic configuration diagram showing another embodiment of the present invention.

FIG. 17 is a sectional view showing an example of the configuration of a limiter (FIG. 16).
3 is a sectional view taken along line YY ′ in FIG.

FIG. 18 is a schematic configuration diagram showing a conventional example.

FIG. 19 is an input / output characteristic diagram of a polygonal line approximation.

FIG. 20 is an input / output characteristic diagram when an offset occurs.

[Explanation of symbols]

1 Light receiving part (pixel) 2-1 to 2-n Vertical transfer register 3,4 Horizontal transfer register 5 Distribution transfer gate 6,7 Charge detection part 10 Timing generator 11 Channel stop area 12a Low sensitivity light receiving area 12b High sensitivity light receiving Region 21 Transfer channel 24, 25, 26 Transfer electrode 30 Signal processing circuit

Claims (3)

[Claims] 1. A plurality of light receiving portions which are at least divided into two by a channel stop region, each of which has an opening independently and which has different sensitivities, and which are two-dimensionally arranged in a matrix, Of the signal charges arranged in each vertical row of the individual light receiving sections and read out from each of the plurality of light receiving areas for each light receiving section, the signal charges of the light receiving areas of the same sensitivity of the adjacent light receiving sections are mixed. A plurality of vertical transfer registers for performing vertical transfer, and a plurality of horizontal transfer registers for separately receiving and horizontally transferring signal charges of light receiving regions having different sensitivities which are sequentially transferred by the plurality of vertical transfer registers, A plurality of charge detection units that detect the signal charges transferred by the plurality of horizontal transfer registers and convert the signal charges into electric signals, and output signals of the plurality of charge detection units. Then, signal processing for clipping at least an output signal based on a signal charge other than the signal charge of the light-receiving region of the minimum sensitivity, and adding the clipped signal and an output signal based on the signal charge of the light-receiving region of another sensitivity to output A solid-state imaging device comprising: a circuit. 2. A plurality of light receiving portions which are at least divided into two by a channel stop region, each of which has an opening independently of each other and which has different sensitivities, and which are two-dimensionally arranged in a matrix, Of the signal charges arranged in each vertical row of the individual light receiving sections and read out from each of the plurality of light receiving areas for each light receiving section, the signal charges of the light receiving areas of the same sensitivity of the adjacent light receiving sections are mixed. A plurality of vertical transfer registers for performing vertical transfer, and a plurality of horizontal transfer registers for separately receiving and horizontally transferring signal charges of light receiving regions having different sensitivities which are sequentially transferred by the plurality of vertical transfer registers, Of the signal charges transferred by the plurality of horizontal transfer registers, at least the signal charges other than the signal charges in the light receiving area of the minimum sensitivity are clipped, and this clip is clipped. A solid-state imaging device, comprising: an output unit that mixes and outputs the signal charge that has been blocked and the signal charge of a light receiving region having another sensitivity. 3. The single limiter for clipping the signal charges other than the signal charges of at least the light receiving region of the minimum sensitivity among the signal charges transferred by the plurality of horizontal transfer registers, and the limiter. 3. The solid-state image pickup device according to claim 2, wherein the solid-state imaging device comprises a single charge detection unit that mixes the signal charges clipped by the signal charges with the signal charges in the light-receiving region of another sensitivity and converts the mixed signal charges into an electric signal. .