JPH09200622A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption and to decrease number of output terminals of a timing generating section by using a horizontal transfer clock driving a horizontal transfer register so as to generate a reset gate clock. SOLUTION: The device is provided with a reset gate clock generating section 10 configured with a differentiation circuit consisting of a capacitor C and a resistor R and an undershoot component elimination diode D for the differentiation circuit output signal connected in parallel with the differentiation circuit. Then a timing generating circuit T does not generate a reset gate clock ϕRG to a charge detection section 5 formed on a board S but a horizontal transfer clock ϕH1 generated from the circuit 7 is used to obtain a required waveform from the generating section 10. That is, as an output terminal of the circuit 7, no clock ϕRG is required and the generating section 10 is provided in the vicinity of the board S not to require wiring of a long wire for transmission of the clock ϕRG even when the circuit and the board S are apart.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device having a charge detection unit for sequentially converting signal charges transferred by a horizontal transfer register into voltage signals.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram for explaining a conventional solid-state image pickup device. That is, in the conventional solid-state imaging device, the plurality of photoelectric conversion units 1 are arranged in a matrix in the row direction (vertical direction) and the column direction (horizontal direction), and the vertical transfer register 2 is arranged for each of these vertical columns. The image pickup area 3 is thus configured.

Further, a horizontal transfer register 4 is provided on the lower side of the image pickup area 3 in the figure, and serves to send the charges transferred from each vertical transfer register 2 to the charge detection section 5. The charge detection unit 5 has, for example, a floating diffusion configuration, and sequentially converts the charges transferred from the horizontal transfer register 4 into a voltage signal and passes the voltage signal to the output amplifier 6. The image pickup area 3, the horizontal transfer register 4, the charge detector 5, and the output amplifier 6 are formed on a predetermined substrate S.

The light incident on the image pickup region 3 is converted into a signal charge by the photoelectric conversion unit 1 according to the amount of the light and stored.
The vertical transfer register 2 is transfer-driven by four-phase transfer clocks of φV1, φV2, φV3, and φV4 sent from the timing generation circuit 7 ′. As a result, the signal charges read out by the vertical transfer register 2 are sequentially transferred in the vertical direction for each part corresponding to one scanning line in a part of the horizontal blanking period.

The signal charges corresponding to one scanning line sequentially transferred by the plurality of vertical transfer registers 2 are sequentially transferred in the horizontal direction by the horizontal transfer register 4. The horizontal transfer register 4 has two-phase horizontal transfer clocks φH1 and φH2.
Transfer driven by.

The charge detector 5 arranged at the end of the horizontal transfer register 4 converts the signal charges sequentially transferred from the horizontal transfer register 4 into a predetermined voltage signal. In the floating diffusion configuration which is the charge detection unit 5, the signal charge sent from the horizontal transfer register 4 is received by the floating diffusion unit and taken out as a voltage signal, and based on the reset gate clock φRG sent from the timing generation circuit 7 ′. The signal charge accumulated in the floating diffusion portion is sent to the reset drain portion. As a result, the floating diffusion portion is reset.

[0007]

However, such a solid-state image pickup device has the following problems. That is, in the conventional solid-state image pickup device, it is necessary to generate the reset gate clock φRG for the floating diffusion configuration, which is the charge detection unit, by the timing generation circuit, and the reset gate clock φRG.
A wire is required for sending the signal from the timing generation circuit to the substrate on which the charge detection unit is formed.

Therefore, this causes an increase in power consumption of the timing generation circuit, and in particular, when the timing generation circuit and the substrate are arranged apart from each other, there is a problem that a long wiring must be routed. .

Therefore, an object of the present invention is to provide a solid-state image pickup device capable of reducing the power consumption of the timing generation circuit and simplifying the wiring from the timing generation circuit to the substrate.

[0010]

SUMMARY OF THE INVENTION The present invention is a solid-state image pickup device which is made to achieve the above object. That is, according to the present invention, a plurality of photoelectric conversion units for accumulating signal charges according to the amount of incident light are arranged in a matrix in the vertical direction and the horizontal direction, and a vertical transfer register for transferring the signal charges is arranged for each vertical column. Image pickup area, a horizontal transfer register that transfers the signal charge transferred from the vertical transfer register in the horizontal direction by a predetermined horizontal transfer clock, and the signal charge transferred by the horizontal transfer register in the order of voltage signals. And a reset gate clock generation unit that generates a reset gate clock for resetting signal charges sent to the charge detection unit based on a horizontal transfer clock.

In such a solid-state image pickup device, since the reset gate clock generation unit generates the reset gate clock by using the horizontal transfer clock for driving the transfer of the horizontal transfer register, the timing generation unit uses the timing generation unit. There is no need to generate a reset gate clock. Further, this eliminates the need for wiring of the reset gate clock sent from the timing generation section to the charge detection section.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a solid-state image pickup device of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram illustrating a first embodiment of a solid-state imaging device of the present invention. That is, the solid-state imaging device according to the first embodiment has a plurality of photoelectric conversion units 1 arranged in a matrix in a row direction (vertical direction) and a column direction (horizontal direction), and a plurality of photoelectric conversion units 1 arranged in each vertical column. Vertical transfer register 2
The image pickup area 3 is formed by the above, and the horizontal transfer register 4 is provided on the lower side of the image pickup area 3 in the figure, and the charge detection portion 5 and the output amplifier 6 are provided at the ends thereof. .

The image pickup area 3, the horizontal transfer register 4, the charge detection section 5, and the output amplifier 6 are formed on a predetermined substrate S. Further, in the solid-state imaging device according to the present embodiment, the vertical transfer clocks φV1, φV2, φV3, and φV4 for driving the vertical transfer register 2 in four phases, and the horizontal transfer clock φH1 for driving the horizontal transfer register 4 in two phases, The timing generation circuit 7 that generates φH2 is connected to the substrate S via a predetermined wiring.

In the solid-state image pickup device according to the first embodiment,
A characteristic is that a reset gate clock φRG formed on the substrate S to the charge detection unit 5 is generated by using a horizontal transfer clock φH1 output from the timing generation circuit 7 is there.

As the reset gate clock generator 10, a differentiation circuit composed of a capacitor C and a resistor R is used. A diode D is provided in parallel with the resistor R of the differentiating circuit in order to remove the undershoot component of the signal output from the differentiating circuit described later.

Here, in the floating diffusion configuration which is the charge detection unit 5, the transfer of the signal charges to the floating diffusion unit and the reset gate clock φRG for resetting the signal charges accumulated in the floating diffusion unit will be described. .

FIG. 2 is a schematic diagram showing a cross-sectional structure of the horizontal transfer register 4 and the charge detection section 5 having a floating diffusion structure. This horizontal transfer register 4
Are formed on the p ^- type well region provided on the n-type substrate S, and the wirings for applying the horizontal transfer clocks φH1 and φH2 for performing the two-phase driving are alternately provided. There is.

Further, the charge detection section 5 of the horizontal transfer register 4
A wiring for applying the horizontal output gate clock HOG is provided on the side. Further, the charge detection section 5 includes a floating diffusion section FD and a reset drain section R.
D and D are provided, and a wiring for applying the reset gate clock φRG is provided between them.

FIG. 3 is a diagram showing ideal timings of various clocks, and FIG. 4 is a diagram showing potential profiles of the horizontal transfer register 4 and the charge detection section 5. In addition,
Each potential profile of ~ in Fig. 4 is
This corresponds to the timings 1 to 3 shown in FIG.

That is, at the timing shown in FIG.
The reset gate clock φRG becomes Low, and the floating diffusion portion FD shown in FIG. 4 becomes a reset level including some reset feedthrough.

Next, at the timing shown in FIG. 3, since the horizontal transfer clock φH1 becomes Low, φH1
The signal charge floats from the storage area to which
The data is transferred to the diffusion unit FD. At this time, the output potential changes according to the amount of signal charges transferred to the floating diffusion portion FD.

Next, at the timing shown in FIG. 3, the reset gate clock φRG becomes High, and the signal charge of the floating diffusion portion FD is sent to the reset drain portion RD. That is, this is the reset state. Then, at the timing shown in FIG. 3, the reset gate clock φRG becomes Low. In addition,
The charges returned to the floating diffusion portion FD at this timing become reset feedthrough.

Conventionally, the reset gate clock φRG is generated by the timing generation circuit 7'shown in FIG. 7 and sent to the charge detection portion 5 of the substrate S through a predetermined wiring. In the first embodiment, as described above, the reset gate clock φRG is not generated by the timing generation circuit 7 shown in FIG. 1, but the horizontal transfer clock φH1 for driving the horizontal transfer register 4 is used. Are generated by a differentiating circuit which is the reset gate clock generator 10.

FIG. 5 shows the reset gate clock φ for the horizontal transfer clock φH1 when this differentiating circuit is used.
It is a figure which shows the waveform of RG. When obtaining this waveform,
One end of the resistor R (see FIG. 1) of the differentiating circuit is connected to an arbitrary DC bias, and the reset gate clock φRG is clamped to the average value. Further, this waveform is a simulation result when the amplitude of the horizontal transfer clock φH1 is 5 V, both the rising time and the falling time are 5 ns, and the capacitance of the capacitor C (see FIG. 1) is 5 pF.

As shown in the waveform of FIG. 5, the reset gate clock φRG obtained by the differentiating circuit using the horizontal transfer clock φH1 rises with the rise of the horizontal transfer clock φH1 and then gradually decreases. Further, the undershoot component of the reset gate clock φRG due to the fall of the horizontal transfer clock φH1 is removed by the diode D connected in parallel with the resistor R of the differentiating circuit shown in FIG.

In this simulation result, the amplitude of the reset gate clock φRG is about 2.8V. The reset gate clock φR shown in FIG.
In G, an undershoot component of about 0.5 V remains and appears as an undershoot of several tens of mV in the output waveform, but since it is a short time, the CDS operation of clamping the original signal charge is possible.

As described above, by providing the reset gate clock generator 10 using a simple differentiating circuit as shown in FIG. 1, the horizontal transfer clock can be generated without generating the reset gate clock φRG in the timing generating circuit 7. It is possible to obtain the required waveform by using φH1.

That is, it is not necessary to provide the reset gate clock φRG for the output terminal of the timing generation circuit 7, and by providing the reset gate clock generation unit 10 near the substrate S, the timing generation circuit 7 Even if the substrate S is distant from the substrate S, it is not necessary to lay out the long wiring necessary for sending the reset gate clock φRG.

Next, the second solid-state image pickup device of the present invention
An embodiment will be described. FIG. 6 is a configuration diagram illustrating a solid-state imaging device according to the second embodiment. The solid-state imaging device according to the second embodiment has a photoelectric conversion unit 1 arranged in a matrix.
And an image pickup area 3 composed of vertical transfer registers 2 arranged along a vertical column, a horizontal transfer register 4, a charge detection unit 5, an output amplifier 6, and a timing generation circuit 7, as in the first embodiment. However, the difference is that the reset gate clock generation unit 10 is built in the substrate S forming the imaging region 3 and the like.

That is, since the reset gate clock generator 10 shown in FIG. 1 has a simple structure in which a differentiating circuit using a capacitor C and a resistor R and a diode D are connected to the differentiating circuit, these are arranged on a substrate S. It can also be formed as a pattern. By thus incorporating the reset gate clock generation unit 10 in the substrate S, the substrate S
Since it is not necessary to provide a terminal for the reset gate clock φRG, it is possible to reduce the number of terminals.

Further, in the second embodiment, since the reset gate clock generator 10 is built in the substrate S,
The number of wirings between the timing generation circuit 7 and the substrate S can be reduced, and the wirings can be simplified especially when the timing generation circuit 7 and the substrate S need to be provided separately from each other such as an endoscope. It will be possible.

In each of the above-described embodiments, the example in which the differentiating circuit including the capacitor C and the resistor R is used as the reset gate clock generating section 10 is shown, but a differentiating circuit including elements other than the capacitor C and the resistor R is used. You may use. The same applies to the diode D for removing the undershoot component even if a unidirectional element other than the diode D is used.

[0033]

As described above, the solid-state imaging device according to the present invention has the following effects. That is, in the present invention, since the reset gate clock is generated using the horizontal transfer clock that drives the horizontal transfer register,
It is not necessary to generate the reset gate clock in the timing generation unit, so that it is possible to reduce power consumption and output terminals of the timing generation unit.

Further, by providing the reset gate clock generating section near the substrate, wiring for the reset gate clock between the timing generating section and the substrate becomes unnecessary.
Furthermore, by incorporating the reset gate clock generation unit in the substrate, it is not necessary to provide a reset gate clock input terminal on the substrate side, and it is possible to reduce the number of terminals on the substrate side and simplify wiring.

[Brief description of drawings]

FIG. 1 is a configuration diagram illustrating a first embodiment of the present invention.

FIG. 2 is a schematic diagram showing a cross-sectional structure.

FIG. 3 is a diagram showing clock timing.

FIG. 4 is a diagram showing a potential profile.

FIG. 5 is a diagram showing a waveform of a reset gate clock φRG with respect to a horizontal transfer clock φH1.

FIG. 6 is a configuration diagram illustrating a second embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a conventional example.

[Explanation of symbols]

1 Photoelectric Conversion Section 2 Vertical Transfer Register 3 Imaging Area 4 Horizontal Transfer Register 5 Charge Detection Section 6 Output Amplifier 7 Timing Generation Circuit 10 Reset Gate Clock Generation Section C Capacitor D Diode R Resistance S
substrate

Claims (3)

[Claims] 1. A plurality of photoelectric conversion units for accumulating signal charges according to the amount of incident light are arranged in a matrix in the vertical and horizontal directions, and a vertical transfer register for transferring the signal charges is arranged for each vertical column. Image pickup area, a horizontal transfer register that transfers the signal charges transferred from the vertical transfer register along a horizontal direction by a predetermined horizontal transfer clock, and the signal charges transferred by the horizontal transfer register in sequence. A charge detection unit for converting into a voltage signal; and a reset gate clock generation unit for generating a reset gate clock for resetting the signal charge sent to the charge detection unit based on the horizontal transfer clock. A characteristic solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein a differentiating circuit is used as the reset gate clock generator. 3. The reset gate clock generation unit comprises:
3. The solid-state imaging device according to claim 2, further comprising a unidirectional element for removing an undershoot component in a reset gate clock pulse output from the differentiating circuit.