JPH09199562A - Quality inspection method of silicon wafer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable quickly estimating fraction defective at a low cost as compared with the case measuring a practical oxide film withstand voltage, and with high precision as compared with the conventional simple method, by forming an oxide film, by thermal oxidation, on a washed surface subjected to mirror finish and counting the number of COP's which have appeared in the process. SOLUTION: After a silicon single crystal stick is grown, a wafer having a specified width is cut out from the single crystal stick, and the surface of the wafer is mirror finished and washed. An oxide film is formed on the surface by thermal oxidation, the number of COP's which have appeared in the process is counted, and the crystal quality is estimated. As to the condition of thermal oxidation, it is preferable that the width of the oxide film is set to be 7-40nm in dry oxygen atmosphere at 800-1100 deg.C. Thereby close positive correlation shown in a figure exists between the density of the COP's which have appeared after the oxide film is formed and that of oxide film withstand voltage deterioration factors, so that the oxide film withstand voltage can be indirectly estimated on the basis of the counting value of the COP's.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a quality of a silicon wafer, and more particularly to a method for indirectly evaluating a dielectric strength voltage characteristic (oxide film breakdown voltage) of an oxide film formed on a surface of a silicon wafer.

[0002]

2. Description of the Related Art Conventionally, in order to evaluate the quality of a silicon wafer, the surface of a wafer cut out from a silicon single crystal ingot to a predetermined thickness is mirror-finished, and then the surface of the wafer is MOS-coated.
A method of producing a type semiconductor element and evaluating the electrical characteristics thereof has been adopted.

As a simple method for evaluating the quality of a silicon wafer, the surface of the wafer is selectively etched with a mixed solution of K ₂ Cr ₂ O ₂ , hydrofluoric acid and water, and the number of ripple patterns appearing on the surface is measured. There is also known a method of evaluating crystal quality from the result of counting the sum of the number of etch pits without ripples (see Japanese Patent Laid-Open No. 6-177220).

On the other hand, on the surface of the silicon wafer, SCl
After cleaning, micro pits and COP (Crystal Originated)
Particle: A type of etch pit) is formed. In the as-recieved wafer, this COP density has no clear relationship with the oxide film withstand voltage, but the density of the COP and the density of the deterioration factor of the oxide film withstand voltage appearing in one repeated cleaning. It has been revealed that there is a very strong correlation between the two (1993, Autumn Meeting of the Applied Physics Society of Japan,
P. 303, 29a-HA-8). Therefore, a method of indirectly evaluating the oxide film breakdown voltage has been adopted from the density of COPs appearing on the wafer surface by one-time repeated cleaning.

[0005]

However, in the above-mentioned prior art, the evaluation method based on the electrical characteristics of the MOS-type semiconductor element requires the time and effort required for manufacturing the MOS-type semiconductor element and the evaluation step associated therewith, and Expensive equipment was required for evaluation. Further, in the etching method using a mixed solution of K ₂ Cr ₂ O ₂ , hydrofluoric acid and water, the formation of etch pits without ripples is easily affected by the state of the wafer surface and the etching solution, and reproducibility is poor. In order to observe the etch pits, it was necessary to strictly control the etching solution and the wafer surface. Moreover, since K ₂ Cr ₂ O ₂ is harmful, there was a problem in working. Furthermore, in the evaluation method based on the density of COP by repeated cleaning, it is necessary to measure the density of COP that appears every cleaning, and the work is very complicated.

The present invention is intended to solve the above-mentioned problems of the prior art, and its main purpose is to quickly and inexpensively as compared with the case of measuring an actual oxide film breakdown voltage.
Another object of the present invention is to provide a silicon wafer quality inspection method capable of predicting a defective rate safely and with high accuracy as compared with a conventional simple method.

[0007]

In order to achieve such an object, in the present invention, after growing a silicon single crystal ingot, a wafer having a predetermined thickness is cut out from the single crystal ingot and The surface is mirror-finished and then washed, and an oxide film is formed on the surface by thermal oxidation.
It was decided to evaluate the crystal quality by counting the number of samples.

In particular, the present invention utilizes a strong correlation between the COP density and the oxide film breakdown voltage obtained by forming an oxide film on the surface of an as recieved wafer, rather than the conventional repeated cleaning method. The oxide film breakdown voltage is evaluated based on the COP density.

In the present invention, the area is 0.2 m.
A gate oxide film with a thickness of m ^{2 to} 50 mm ² and a thickness of 7 nm to 40 nm was formed on a silicon wafer, and a DC voltage was applied between the phosphorus-doped polysilicon electrode formed on the oxide film and the silicon single crystal substrate. At that time, the current density is 1 mA / c
The case where the electric field strength applied to the oxide film when the gate current started to flow m ² or more was less than 8 MV / cm was regarded as poor, and the case where the electric field strength at this time was 8 MV / cm or more was regarded as good.

The condition of thermal oxidation in the present invention is 80
In a dry oxygen atmosphere at 0 ° C to 1100 ° C, the oxide film thickness is set to 7
It is preferably set to nm to 40 nm. By setting the thermal oxidation conditions in this way, the COP on the wafer surface can be observed more easily and accurately.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in more detail. First, a wafer is cut out from a silicon single crystal ingot grown under various conditions by the Czochralski (CZ) method. After polishing the surface of this wafer, the oxide film breakdown voltage was measured and thermal oxidation was performed. Among the COPs appearing on the surface, the density (number / cm ² ) of COPs having a size larger than 0.11 μm was measured by a known foreign matter inspection device. The thermal oxidation is performed in a dry oxygen atmosphere at 1000 ° C,
The film thickness was 25 nm.

FIG. 1 is a cross-sectional view of a MOS semiconductor mounted on a silicon wafer used for evaluation of oxide film breakdown voltage.
A silicon oxide film 2 is formed on a silicon wafer 1, and a two-layer gate electrode 5 having a diameter of 5 mm and made of aluminum 3 as an upper layer and polycrystalline silicon 4 as a lower layer is formed on the silicon oxide film 2.
Are formed.

The breakdown voltage of the oxide film was evaluated by the voltage rumbing method. In FIG. 1, the voltage-rambling method is to apply a DC voltage of a polarity, in which a large number of carriers are injected from the substrate silicon, between the aluminum layer 3 and the back electrode and to make the voltage stepwise with respect to time. It is a way to increase. According to the present invention, the voltage increase per step of the voltage rumbing method is 0.25 MV / cm in terms of electric field, the holding time is 200 ms / step, and the current density flowing through the silicon oxide film 2 in FIG. 0.0μ
The oxide film breakdown voltage of the silicon single crystal was evaluated by the ratio (C mode ratio) to the total number of the MOS type semiconductors showing an average electric field applied to the silicon oxide film 2 of 8.0 MV / cm or more at A / cm ² . . When the C-mode ratio was 60% or more, the oxide film breakdown voltage was evaluated as good.

CO on the wafer surface obtained by the above method
A plot of the P density and the oxide film withstand voltage failure rate is shown in FIG.
And a scatter plot with little data variation as shown in FIG. 3 was obtained. Here, FIG. 2 shows the relationship between the density of the COP before the oxidation and the density of the oxide film withstand voltage deterioration factor. From this, the density of the COP on the wafer surface before the oxide film formation and the density of the oxide film withstand voltage deterioration factor are shown. It can be seen that there is no clear correlation between and. On the other hand, from FIG. 3 showing the relationship between the COP density after oxidation and the density of the oxide film withstand voltage deterioration factor, from the density of the COP appearing on the wafer surface after the oxide film formation and the density of the oxide film withstand voltage deterioration factor, , There is a strong positive correlation. From the above, it can be seen that the method of the present invention can indirectly evaluate the oxide film breakdown voltage based on the COP count value.

[0015]

As described above, according to the present invention, when inspecting micro defects in a silicon single crystal, an oxide film is formed on the surface of a silicon wafer having a mirror finish, and the number of COPs appearing on the wafer surface is counted. By doing so, it is possible to evaluate the breakdown voltage of the oxide film of the silicon single crystal, so that it is possible to safely and inexpensively predict the defective rate with higher efficiency and accuracy as compared with the conventional evaluation method.

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a MOS diode mounted to evaluate withstand voltage characteristics of a silicon single crystal insulating oxide film by a conventional method.

FIG. 2 is a scatter diagram showing the relationship between the COP and the density of the oxide film withstand voltage deterioration factor for a wafer before oxidation.

FIG. 3 is a scatter diagram showing the relationship between the COP and the density of the oxide film withstand voltage deterioration factor for an oxidized wafer.

[Explanation of symbols]

 1 Silicon Single Crystal 2 Insulating Oxide Film 3 Aluminum Film 4 Polycrystalline Silicon 5 Two Layer Gate Electrode

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuto Kawakami 1618 Ida, Nakahara-ku, Kawasaki City Nippon Steel Corp. Technology Development Division

Claims (1)

[Claims] 1. After growing a silicon single crystal ingot, a wafer having a predetermined thickness is cut out from the single crystal ingot, the surface of the wafer is mirror-finished and washed, and the surface is oxidized by thermal oxidation. A COP (Crystal Originated Particl) that appears when a film is formed
A quality inspection method for a silicon wafer, which comprises evaluating the crystal quality by counting the number of e).