JPH09198882A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten time required for writing operation as a whole to allow eliminating of any unnecessary verifying lead in the storing of multi-valued information. SOLUTION: This apparatus performs a multi-valued storing of data 'i' (i=0, 1, 2) with three memory states held in one memory cell. In this case, the apparatus is also provided with a plurality of data circuits to temporarily store data for controlling the writing operation state of a plurality of memory cells in an array, a write verifying circuit to verify the writing state of the plurality of memory cells and a (i)th data batch verifying circuit to perform a batch detection of whether the memory cell to write the data 'i' thereinto reaches the memory status of the data '1'' or not. With the batch detection that the memory cell to write the data '1' thereinto reaches the memory status of the data '1', no write verifying operation is done for the data '1' in the further write verifying operation when writing and write verifying operation are continued until the plurality of memory cells reach the specified writing status.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM),
In particular, the present invention relates to an EEPROM that performs multivalued storage in which one memory cell stores more than one bit of information.

[0002]

2. Description of the Related Art As one of the EEPROMs, a NAND type EEPROM capable of high integration is known. This is to connect a plurality of memory cells in series so that their sources and drains are shared by adjacent ones and to connect them to a bit line as one unit. The memory cell usually has a FETMOS structure in which a charge storage layer and a control gate are stacked. The memory cell array is integrated and formed in a p-type well formed on a p-type substrate or an n-type substrate. The drain side of the NAND cell is connected to the bit line via the select gate, and the source side is also connected to the common source line via the select gate. The control gates of the memory cells are continuously arranged in the row direction to form word lines.

The operation of this NAND cell type EEPROM is as follows. Data writing is performed in order from the memory cell farthest from the bit line. A high voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and an intermediate voltage Vppm (= 1 is applied to the control gate and the select gate of the memory cell on the bit line side from that.
0V) is applied, and 0V is applied to the bit line according to the data.
Alternatively, an intermediate voltage Vm (= about 8V) is applied. When 0V is applied to the bit line, the potential is transferred to the drain of the selected memory cell, and electrons are injected into the charge storage layer.
As a result, the threshold value of the selected memory cell shifts in the positive direction. This state is, for example, "1". When Vm is applied to the bit line, electron injection does not effectively occur, so the threshold value does not change and remains negative. This state is an erased state and is "0". Data writing is simultaneously performed on memory cells sharing a control gate.

Data erasing is simultaneously performed on all the memory cells in the NAND cell. That is, all the control gates are set to 0V and the p-type well is set to 20V. At this time, the selection gate, the bit line and the source line are also set to 20V. As a result, in all memory cells, the electrons in the charge storage layer are emitted to the p-type well, and the threshold value shifts in the negative direction.

For data reading, the control gates of the selected memory cells are set to 0V, and the control gates and selection gates of the other memory cells are set to the power supply potential Vcc (for example, 5V).
Is performed by detecting whether or not a current flows in the selected memory cell.

Due to the restriction of read operation, the threshold value after writing "1" must be controlled between 0V and Vcc. Therefore, write verify is performed,
Only the memory cells for which "1" write is insufficient are detected and "1"
The rewrite data is set so that the rewrite is performed only to the memory cells in which the write is insufficient (per-bit verification). A memory cell in which "1" is insufficiently written is detected by setting the selected control gate to, for example, 0.5 V (verify voltage) and reading (verify read).

That is, if the threshold of the memory cell has a margin with respect to 0V and is not more than 0.5V, a current flows through the selected memory cell, and it is detected that "1" write is insufficient. Since a current naturally flows in a memory cell that is set to the "0" write state, a circuit called a verify circuit that compensates the current flowing through the memory cell is provided so that this memory cell is not mistakenly recognized as insufficient "1" write. The write verify is executed at high speed by this verify circuit.

By repeating the write operation and the write verify to write data, the write time is optimized for each memory cell, and the threshold value after "1" write is controlled between 0V and Vcc. It

Such a NAND cell type EEPROM
So, for example, the state after writing is “0”, “1”, “2”
A multi-valued memory cell that stores three or more data is proposed. In this case, for example, the threshold value is negative in the "0" write state, the threshold value is 0V to 1/2 Vcc in the "1" write state, and the threshold value is 1/2 Vcc to Vcc in the "2" write state. To do.

Conventionally, a write and a verify read operation for checking whether writing has been sufficiently performed for this type of three-valued memory cell are shown in FIG. In the write operation, after the write voltage (Vpp) is applied to the control gates of the memory cells, it is sequentially verified whether the “2” write is sufficiently performed.
A second cycle of verify read is performed to check whether the cycle and "1" writing have been sufficiently performed. A write pulse is applied to a memory cell in which writing is insufficient. In this way, the verify read first cycle, the verify read second cycle, and the rewriting are repeated until all the memory cells are sufficiently written.

The procedure of this write operation is the same for a four-valued memory cell as shown in FIG. 20, and in the verify read operation after writing, the verify read first cycle for checking whether "3" writing has been sufficiently performed. ,
A verify read second cycle for checking whether "2" writing is sufficiently performed and a verify read third cycle for checking whether "1" writing is sufficiently performed are sequentially performed.

However, this type of multi-value memorable E
The EPROM has the following problems in writing. That is, for example, in a ternary memory cell, first, "1" write with a small write threshold value is sufficiently performed, and then "2" write is sufficiently performed. Therefore, in the conventional writing method, after all the memory cells in which "1" is written are sufficiently written,
Until the "2" write is completed, the verify read second cycle for checking whether the unnecessary "1" write is sufficient is performed. Therefore, there is a problem that the verify read time becomes long and the entire write operation takes a long time.

For example, in a 4-level memory cell, first, "1" write with a small write threshold value is sufficiently performed, then "2" write is sufficiently performed, and then "3" write is sufficiently performed. Done. Therefore, in the conventional write method, after all the memory cells to be written "1" are sufficiently written, unnecessary "1" write is performed until "2" write and "3" write are completed. The second cycle of verify read is performed to check whether it is sufficient. Then, after all the memory cells in which "2" writing is performed are sufficiently written, a second verify read cycle is performed to check whether unnecessary "3" writing is sufficient until "3" writing is completed. As a result, there is a problem that the verify read time becomes long and the time of the entire write operation is long.

[0014]

As described above, the conventional N
In the case where multi-value storage is performed in the AND cell type EEPROM and the verify circuit performs the verify write for each bit, during verify read, for example, two verify read cycles are performed in a three-valued memory cell until all data is written. In the 4-level memory cell, three verify read cycles are performed. As a result, there is a problem that the verify read time is long and the time of the entire write operation is long.

The present invention has been made in consideration of the above circumstances, and an object thereof is to eliminate unnecessary verify read when storing multi-valued information and to improve the entire write operation. An object of the present invention is to provide an EEPROM capable of shortening the time required for.

[0016]

Means for Solving the Problems (Structure) In order to solve the above problems, the present invention employs the following structure.

(1) A memory cell array in which electrically rewritable memory cells are arranged in a matrix,
By giving one memory cell a plurality of storage states of three or more, arbitrary data “i” (i = 0, 1, ..., N−1; n
A plurality of data circuits for temporarily storing data for controlling a write operation state of a plurality of memory cells in the memory cell array, and the plurality of memory cells. Write verify means for confirming the write state of the data, and an i-th data batch verify circuit for collectively detecting whether or not the memory cells to which the data “i” has been written have reached the storage state of the data “i”. It is characterized by comprising.

(2) A memory cell array in which electrically rewritable memory cells are arranged in a matrix,
By giving one memory cell a plurality of storage states of three or more, arbitrary data “i” (i = 0, 1, ..., N−1; n
A plurality of data circuits for temporarily storing data for controlling a write operation state of a plurality of memory cells in the memory cell array, and the plurality of memory cells. Write verifying means for confirming the write state of the data circuit, and updating the content of the data circuit so as to rewrite only to the memory cell in which the write is insufficient from the content of the data circuit and the write state of the memory cell. Means and an i-th data batch verify circuit for collectively detecting whether or not the memory cells to which the data “i” has been written have reached the storage state of the data “i”. .

(3) In addition to the configuration of (1) above, a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cell are performed by the plurality of memory cells in a predetermined write operation. When the memory cell to which the data “i” is to be written has reached the storage state of the data “i” in the operation of electrically writing data, the i-th data batch verify circuit Is detected collectively, the write verify operation for the data “i” (i-th verify read) is not performed in the subsequent write verify operation. (4) In addition to the configuration of (2) above, the plurality of memory cells perform a predetermined write operation based on the content of the data circuit, a write verify operation for confirming the write state of the memory cell, and a content update of the data circuit. By continuously performing the data write operation until the memory cell to which the data “i” is to be written reaches the storage state of the data “i”, the i-th data batch verification is performed. When the circuits collectively detect, the write verify operation (i-th verify read) for the data “i” is not performed in the subsequent write verify operation.

(5) In addition to the configuration of (3) or (4) above, in the first write verify operation, data "i" (i = 1,
2, to n−1) is performed, i-th verify read is performed from i = 1 to i = n−1 to confirm whether or not the memory cell to which data “i” is stored has been reached. After that, the memory cell to which the data “1” is to be written is
When the first data batch verify circuit collectively detects that the storage state of the data “1” has been reached, the data “i” (i = 2, 3, ..., N−) is executed in the subsequent write verify operation.
1) The i-th verify read is performed from i = 2 to i = n−1 to confirm whether or not the memory cell to be written has reached the storage state of the data “i”, and then the data “2” The memory cell to be written is data "2"
When the second data batch verify circuit collectively detects that the memory state has been reached, the memory cells to which the data “i” (i = 3, 4, ..., N−1) are to be written in the subsequent write verify operation. , I-th verify read for confirming whether the storage state of the data “i” has been reached from i = 3 to i = n−1, and finally the data “i” (i = 1
To n-2), the i-th (i = 1 to n-2) data batch verify circuit collectively detects that the memory cells to which data "i" has been written have reached the storage state of the data "i". It is characterized in that the memory cell to which the data "n-1" is written performs the (n-1) th verify read for confirming whether the memory state of the data "n-1" has been reached.

(6) In addition to the configuration of (1) above, a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cells are performed so that the plurality of memory cells are brought into a predetermined write state. By continuously performing the above operation, when the memory cell to be written has no memory cell to which the data “i” is to be written in the operation of electrically writing data, the i-th data batch verify circuit collectively detects. In the write verify operation, the write verify operation (i-th verify read) for the data “i” is not performed.

(7) In addition to the configuration of (2) above, a write operation based on the contents of the data circuit, a write verify operation for confirming the write state of the memory cell and an update of the contents of the data circuit are performed. Is continuously performed until a predetermined write state is reached, and in the operation of electrically writing data, if there is no memory cell to be written with the data “i” in the memory cell to be written, the i-th data batch When the verify circuit collectively detects, the write verify operation (i-th verify read) for the data “i” is not performed in the write verify operation.

(8) Having a memory cell array in which electrically rewritable memory cells are arranged in a matrix,
By giving one memory cell a plurality of storage states of three or more, arbitrary data “i” (i = 0, 1, ..., N−1; n
In a non-volatile semiconductor memory device for multi-value storage of 3 or more), the first and second data temporarily storing data for controlling a write operation state of a plurality of memory cells in the memory cell array.
Second, ..., Mth (m is a natural number satisfying 2 ^{(m −1)} <n ≦ 2 ^m ) data latch circuits, write verify means for confirming the write states of the plurality of memory cells, and data. It is characterized in that it is provided with an i-th data batch verify circuit for collectively detecting whether or not the memory cells to be written with "i" have reached the storage state of the data "i".

(9) Having a memory cell array in which electrically rewritable memory cells are arranged in a matrix,
By giving one memory cell a plurality of storage states of three or more, arbitrary data “i” (i = 0, 1, ..., N−1; n
In a non-volatile semiconductor memory device for multi-value storage of 3 or more), the first and second data temporarily storing data for controlling a write operation state of a plurality of memory cells in the memory cell array.
The second, ..., The m-th (m is a natural number that satisfies 2 ^{(m −1)} <n ≦ 2 ^m ) data latch circuit, write verify means for confirming the write state of the plurality of memory cells, and Means for updating the contents of the data latch circuit so that rewriting is performed only to the memory cells that are insufficiently written from the contents of the data circuit and the written state of the memory cell, and the memory cell to which the data "i" is written However, an i-th data batch verify circuit for collectively detecting whether or not the storage state of the data “i” has been reached is provided.

(10) In addition to the configuration of (9) above, a write operation based on the content of the data circuit, a write verify operation for confirming the write state of the memory cell and an update of the content of the data circuit are performed. Is continuously performed until a predetermined write state is reached, the memory cell to which the data “i” is to be written reaches the storage state of the data “i” in the electrically writing operation. When the data batch verify circuit detects all the data, the data "i" is detected in the subsequent write verify operation.
It is characterized in that the write verify operation (i-th verify read) with respect to is not performed.

(11) In addition to the configuration of (9) above, a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cell are performed by the plurality of memory cells in a predetermined write operation. When the memory cell to which the data “i” is to be written has reached the storage state of the data “i” in the operation of electrically writing data, the i-th data batch verify circuit Is detected collectively, the write verify operation for the data “i” (i-th verify read) is not performed in the subsequent write verify operation.

(12) In addition to the configuration of (9) or (10) above, in the first write verify operation, data "i (i = 1, 1,
2, ~, n-1) "is to be written to a memory cell,
The verify read of the i-th (i = 1,2, ..., n-1) for confirming whether the storage state of the data "i (i = 1,2,-, n-1)" has been reached from i = 1 up to i = n-1, n-1
When the first data batch verify circuit collectively detects that the memory cells to which the data “1” is to be written have reached the storage state of the data “1” after performing the verify read once, the subsequent write verify operation is performed. Then, the memory cell to which the data “i (i = 2, 3, ˜, n−1)” is to be written is the data “i (i = 2, 3, ˜, n−).
1) ”i-th (i = 2)
The verification read of 3, to, n-1) is performed from i = 2 to i =
The second data batch verify circuit collectively detects that the memory cells to which the data “2” is to be written have reached the storage state of the data “2” after performing the verify reading n−2 times up to n−1. Then, in the subsequent write verify operation, the data "i (i = 3, 4, ..., N-1)" is written.
The memory cell to which is written is data "i (i =
3,4, ..., n-1) ", i-th (i = 3,4,-, n-1) verify read from i = 3 to i = n-1 is performed. , N−3 times verify read, and finally data “i (i = 1 to n−2)”
The memory cell to which is written is data "i (i = 1
~ N-2) "memory state is reached, the i-th (i = 1 to n-)
When the data batch verify circuit of 2) batch-detects, it is confirmed in the subsequent write verify operation whether the memory cell to which the data “n-1” is to be written has reached the storage state of the data “n-1”. It is characterized in that verify reading of n-1 is performed.

(13) In addition to the configuration of (9) above, a write operation based on the contents of the data circuit, a write verify operation for confirming the write state of the memory cell, and an update of the contents of the data circuit are performed. Is continuously performed until a predetermined write state is reached, and in the operation of electrically writing data, if there is no memory cell to be written with the data “i” in the memory cell to be written, the i-th data batch When the verify circuit collectively detects, the write verify operation (i-th verify read) for the data “i” is not performed in the write verify operation.

(14) In addition to the configuration of (10) above, a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cells are performed to bring the plurality of memory cells into a predetermined write state. By continuously performing the above operation, when the memory cell to be written has no memory cell to which the data “i” is to be written in the operation of electrically writing data, the i-th data batch verify circuit collectively detects. In the write verify operation, the write verify operation (i-th verify read) for the data “i” is not performed.

(Operation) In the present invention, after multi-value data writing is performed, the data batch verify circuit
It is detected whether the write state of each memory cell has reached its desired multi-level level state. Then, if there is a memory cell that has not reached the desired multilevel level, the bit line voltage at the time of writing is output according to the desired write state so that rewriting is performed only to that memory cell. Then, for example, in the case of a ternary memory cell,
When all the memory cells to be written with “1” have been written, in the subsequent verify read, the verify read for checking whether the “1” write is sufficient is omitted, thereby shortening the entire write time. This write operation and verify read are repeated, and when it is confirmed that all the memory cells have reached the desired write state, the data write ends.

For example, in the case of a four-valued memory cell, if all the memory cells to be written with "1" have been written, the verify read for checking whether "1" is sufficiently written is omitted in the subsequent verify read. Further, when all the memory cells to be written with "2" have been written, the "2" verify read is omitted in the subsequent verify read. As described above, by omitting unnecessary verify read, the entire write time is shortened. This writing operation and verify reading are repeated, and when it is confirmed that all the memory cells have reached the desired writing state, the data writing is ended.

As described above, according to the present invention, the write operation is repeated in small increments while checking the progress of the write state, and the data (for example, “1” data in the ternary memory cell) for which writing has been completed is further performed. As a result, data writing can be performed at a high speed by omitting unnecessary verify reading (for example, verify reading for checking whether "1" writing is sufficient for a three-valued memory cell).

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

[Embodiment 1] FIG. 1 shows a first embodiment of the present invention, which is a write operation in the case of a ternary memory cell. After the first writing, a verify read first cycle for checking whether "2" writing is sufficiently performed and a verify read second cycle for checking whether "1" writing is sufficiently performed. If there is a memory cell for which writing is insufficient in the "1" -written memory cells, reprogramming is performed, and the verify read first cycle and the verify read second cycle are performed again. In addition,
In this reprogramming, writing is performed even for a memory cell in which "2" writing is insufficient.

After the memory cells to be written "1" have been sufficiently written, the verify read second cycle for checking whether the "1" writing has been sufficiently performed is no longer necessary. Therefore, as shown in FIG. Until the memory cell for 2 "write is sufficiently written, only" 2 "write and the verify read first cycle for checking whether" 2 "write is sufficient are performed.

As described above, according to this embodiment, after the memory cells to be written with "1" are sufficiently written,
Since the verify read for checking whether the "1" write is sufficient is not performed, the entire write time is significantly shortened.

[Embodiment 2] FIG. 2 shows another embodiment in the case of a ternary memory cell. The difference from the first embodiment is the operation in the case where the memory cell for writing “2” may complete the writing faster than the memory cell for writing “1”.

When writing is completed faster in the "2" write memory cell than in the "1" write memory cell, "2"
After the writing of the write memory cell is completed, the verify read for checking whether "2" is sufficiently written is not performed, and until the memory cell to be written "1" is sufficiently written,
Only the "1" write and the verify read second cycle for checking whether the "1" write is sufficient are performed. Also,
When the writing of the “1” write memory cell is completed faster than that of the “2” write memory cell, “2” is written until the memory cell to be written “2” is sufficiently written, as in the first embodiment. Only the first cycle of the verify read in which writing and "2" writing are sufficient is performed.

As described above, according to the present embodiment, after either the memory cell for writing "1" or the memory cell for writing "2" is sufficiently written, the verification of the memory cell that is sufficiently written is performed. Since no read is performed, the total write time is greatly reduced.

[Third Embodiment] FIG. 3 shows an embodiment in the case of a four-valued memory cell. Also in this case, as in the first embodiment, the entire write time is shortened by omitting unnecessary verify read. That is, after the first writing, the verify read first cycle for checking whether "3" writing is sufficiently performed, the verify read second cycle for checking whether "2" writing is sufficiently performed, and the "1" writing are sufficiently performed. A third verify read cycle is performed to check whether the verification read has been performed.

When there is a memory cell for which writing is not sufficient among the memory cells for which "1" has been written, reprogramming is performed, and the verify read first cycle, verify read second cycle, and verify read third cycle are performed again. In this reprogramming, writing is also performed on the memory cells for which "2" writing is insufficient or for "3" writing insufficient.

After the memory cell to be written with "1" is sufficiently written, the third verify read cycle for checking whether or not "1" is sufficiently written is no longer necessary. Therefore, as shown in FIG. Verify read 1st time for rewriting and checking if "3" writing is sufficient until the memory cell for 2 "writing is sufficiently written.
In the cycle, a second verify read cycle is performed to check whether "2" writing is sufficient.

After the memory cells for "2" programming have been sufficiently programmed, the second verify read cycle for checking whether the "2" programming has been sufficiently performed is no longer performed. That is, as shown in FIG. 3, rewriting and only the first verify read cycle in which it is checked whether "3" writing is sufficient are performed until the memory cells to be written "3" are sufficiently written.

As described above, in the present invention, when multi-valued data (for example, "1", "2", ..., "6", "7") is written almost at the same time, writing is sufficiently performed at the time of verify read. The entire write time can be shortened by not performing the data verify read thereafter. For example, in the case of an eight-valued memory cell, verify read for “1”, “2” ... “7” is performed seven times for the first write operation, and then “2”, “3”, ~,
The verify read is performed 6 times for “7”, and then the verify read is performed 5 times for “3”, “4”, ..., “7”.

As in the second embodiment, for example, if a memory cell of "3" write is first sufficiently written, then "1", "2", "4",
If the verify read is performed 6 times for "5", ..., "7", and then, for example, when the memory cell for "2" write is sufficiently written, "1",
It suffices that the verify read is performed five times for "4", "5", ..., "7".

That is, the number of times of verify read can be reduced every time arbitrary data is sufficiently written, and the write time as a whole can be shortened.

[Embodiment 4] Next, an embodiment in which the present invention is applied to a ternary memory cell of a NAND type EEPROM will be described.

FIG. 4 is a block diagram showing a schematic structure of a NAND cell type EEPROM according to the fourth embodiment of the present invention.

Read / write to the memory cell array 1
A bit line control circuit 2 for controlling a bit line at the time of writing and a word line drive circuit 7 for controlling a word line potential are provided. The bit line control circuit 2 and the word line drive circuit 7 are selected by the column decoder 3 and the row decoder 8, respectively. The bit line control circuit 2 receives the input / output data conversion circuit 5 via the data input / output line (IO line).
And read / write data are exchanged.
The input / output data conversion circuit 5 converts the read multi-valued information of the memory cell into binary information for outputting to the outside, and converts the binary information of the write data input from the outside into the multi-valued information of the memory cell. Convert. In addition, the input / output data conversion circuit 5
Is connected to a data input / output buffer 6 which controls data input / output with the outside. The "1" data write end detection circuit and the data write end detection circuit 4 detect whether the "1" data write is completed and whether all the data are written.

5 and 6 show specific configurations of the memory cell array 1 and the bit line control circuit 2. With the memory cells M1 to M8 and the selection transistors S1 and S2,
Construct a D-type cell. One end of the NAND cell is connected to the bit line BL and the other end is connected to the common source line Vs. Select gates SG1 and SG2, control gates CG1 to C
The G8 is shared by a plurality of NAND cells, and memory cells sharing one control gate form a page.

The memory cell stores data at the threshold value Vt. If Vt is 0 V or less, "0" data, Vt.
Is stored as "1" data when Vt is 0 V or more and 1.5 V or less and "2" data when Vt is 1.5 V or more and the power supply voltage or less. One memory cell has three states, and two memory cells can be combined in nine ways. Of these,
Three combinations of data are stored in two memory cells using eight combinations. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate. The memory cell array 1 is formed on a dedicated p well.

Clock synchronous inverters CI1 and CI2
And CI3 and CI4 form flip-flops respectively and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI1 and CI2 latches "whether" 0 "is written," 1 "or" 2 "is written" as write data information, and the memory cell is ""Holdinformation" 0 "or information" 1 "or" 2 "?" Is latched as read data information. The flip-flop composed of the clock synchronous inverters CI3 and CI4 latches "whether" 1 "is written or" 2 "is written" as write data information, and the memory cell is "2". Whether information is held or "0" or "1" information is held "is latched as read data information.

Of the n-channel MOS transistors, Q
n1 transfers the voltage VPR to the bit line when the precharge signal PRE becomes "H". In Qn2, the bit line connection signal BLC becomes "H" to connect the bit line to the main bit line control circuit. Qn3 to Qn6, Qn9 to Qn12
Selectively transfers the voltages VBLH, VBLM, and VBLL to the bit line according to the data latched by the above flip-flop. Qn7 and Qn8 are flipped when the signals SAC2 and SAC1 become "H", respectively.
Connect the flop and bit line. Qn13 is a flip
It is provided to detect whether or not the data for one page latched in the flop are all the same. Qn14, Qn
15 and Qn16 and Qn17 are column selection signals CSL, respectively.
1, CSL2 becomes "H", and the corresponding flip-flop and the data input / output lines IOA and IOB are selectively connected. Qn13A and Qn13B are data batch detection MOS
It is a transistor, and is provided to detect whether all the memory cells for writing "1" in the same page are sufficiently written.

Next, the EEPROM configured as described above
The operation of will be described with reference to FIGS. FIG. 7 is a read operation timing, FIG. 8 is a write operation timing,
FIG. 9 shows the timing of the verify read operation. In both cases, the case where the control gate CG4 is selected is shown as an example.

<Read Operation> The read operation is executed in two basic cycles as shown in FIG. In the first read cycle, the voltage VPR becomes the power supply voltage Vcc and the bit line is precharged, and the precharge signal PRE becomes "L" and the bit line is floated. Subsequently, the selection gates SG1 and SG2 and the control gates CG1 to CG3 and CG5 to CG8 are set to Vcc. At the same time, the control gate CG4 is set to 1.5V. Only when the Vt of the selected memory cell is 1.5 V or more, that is, only when the data “2” is written, the bit line is held at the “H” level.

After this, the sense activation signals SEN2, SE
N2B is "L", "H", respectively, and latch activation signal L
AT2 and LAT2B are set to "L" and "H", respectively, and the flip-flop composed of the clock synchronous inverters CI3 and CI4 is reset. Signal SAC
2 becomes "H" and clock synchronous inverter CI3,
The flip-flop constituted by CI4 is connected to the bit line, and the sense activation signals SEN2 and SEN2B are first set to "H" and "L" to sense the bit line potential, and then the latch activation signal LAT2. LAT2B becomes "H" and "L" respectively, and the flip-flop composed of the clock synchronous inverters CI3 and CI4
The information ““ 2 ”data,“ 1 ”or“ 0 ”data” ”is latched.

In the second read cycle, the voltage of the selection control gate CG4 is 1.5 compared with the first read cycle.
0V instead of V, signals SEN2, SEN2B,
Signal SEN instead of LAT2, LAT2B, SAC2
The difference is that 1, SEN1B, LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the flip-flop composed of the clock synchronous inverters CI1 and CI2 causes "0" data or "1"
Alternatively, the information “2” data ”is latched. The data written in the memory cell is read by the two read cycles described above. The nodes N1 and N2 of the read latches LAT1 and LAT2 are as shown in (Table 1) below. In Table 1, “H” is Vcc,
"L" is Vss.

[0058]

[Table 1]

<Write Operation> FIG. 8 is a timing chart of the write operation. Write data is transferred from IOA and IOB to the latches LAT1 and LAT2. Node N
The potentials of 1 and N2 are as shown in (Table 2) below.

[0060]

[Table 2]

Prior to data writing, the data in the memory cell is erased, and the threshold Vt of the memory cell is 0 V or less. For erasing, the p-well, the common source line Vs, the selection gates SG1 and SG2 are set to 20 V, and the control gate CG is set.
1 to CG8 is performed with 0V.

In the write operation, first, the precharge signal PRE becomes "L" and the bit line is floated. Select gate SG1 is Vcc, control gates CG1 to
CG8 is set to Vcc. The select gate SG2 is 0V during the write operation. At the same time, the signals VRFY1 and VRFY
2, FIM and FIH become Vcc. In the case of writing "0", since the data is latched in the flip-flop composed of the clock synchronous inverters CI1 and CI2 so that the output of the clock synchronous inverter CI1 becomes "H", the bit line is It is charged by Vcc.
In the case of writing "1" or "2", the bit line is 0V.

Subsequently, the selection gate SG1 and the control gate C
G1 to CG8, signal BLC, signal VRFY1 and voltage VS
A is 10V, voltage VBLH is 8V, voltage VBLM is 1V
Becomes In the case of writing "1", since the data is latched in the flip-flop composed of the clock synchronous inverters CI3 and CI4 so that the output of the clock synchronous inverter CI3 becomes "H", the bit line B
1V is applied to L. The bit line is 0V when "2" is written, and 8V when "0" is written. After that, the selected control gate CG4 is set to 20V.

In the case of "1" or "2" write, electrons are injected into the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate CG4, and the threshold value of the memory cell rises. In the case of "1" writing, the amount of charges to be injected into the charge storage layer of the memory cell must be reduced as compared with "2" writing, so that the bit line BL is set to 1
The potential difference with the control gate CG4 is set to V and is relaxed to 19V. However, it can be implemented without alleviating this potential difference. At the time of writing "0", the threshold voltage of the memory cell is not effectively changed by the bit line voltage 8V.

At the end of the write operation, first, the select gate SG1 and the control gates CG1 to CG8 are set to 0 V, and "0" is set.
The voltage 8V of the bit line BL at the time of writing is reset to 0V with a delay. This is because if this order is reversed, the state of the "2" write operation can be temporarily made and the wrong data will be written when the "0" is written.

<Write Verify Read> After the write operation, the write state of the memory cell is confirmed, and the additional write is performed only to the memory cell in which the write is insufficient, so the verify read is performed. This embodiment is a ternary memory cell, and the timing chart of the verify read operation is shown in FIG.
The outline of the operation is shown in FIG.

During the verify read, the voltage VBLH is Vcc, VBLL is 0V, and FIM is 0V. Prior to verify read, RENDB1 and RENDB2
Is precharged to a constant potential (eg Vcc) and then kept floating.

The first verify read after applying the first write pulse is executed from two basic cycles. This basic cycle is similar to the first read cycle. The difference is that the voltage of the selected control gate CG4 and the signals VRFY1, VRFY2 and FIH are output (V in the verify read first cycle).
RFY1 only).

The signals VRFY1, VRFY2 and FIH are
Select gates SG1 and SG2, control gates CG1 to CG8
Signal SEN1, SEN1 after reset to 0V
B, LAT1, and LAT1B are "L", "H",
It is output before it becomes "L" or "H". In other words,
After the potential of the bit line is determined by the threshold value of the memory cell, before the flip-flop composed of the clock synchronous inverters CI1 and CI2 is reset. The voltage of the selected control gate CG4 is 2V (first cycle), 0.5V (second cycle) corresponding to 1.5V (first cycle) and 0V (second cycle) at the time of reading, It is set high in order to secure a threshold margin of 0.5V.

Here, the clock synchronous inverter CI
1, the data (data1) latched in the flip-flop composed of CI2, the data (data2) latched in the flip-flop composed of the clock synchronous inverters CI3 and CI4, and the selected memory cell The voltage of the bit line BL determined by the threshold value will be described. data1 is “0” write or “1”
Or "2" write "is controlled. When" 0 "is written, Qn3 is" ON ", and when" 1 "or" 2 "is written, Qn6 is" ON ". data2 controls “whether“ 1 ”writing or“ 2 ”writing”,
When writing "1", Qn10 is "ON", "2"
In the case of writing, Qn11 is in the "ON" state.

<Verify Read First Cycle>
In the verify read first cycle at the time of writing "0" data (initial write data is "0"), since the data of the memory cell is "0", the control gate CG4
Becomes 2V, the bit line potential becomes "L" depending on the memory cell. After that, the signal VRFY1 becomes "H", and the bit line BL becomes "H".

In the verify read first cycle at the time of writing "1" data (initial write data is "1"), the data of the memory cell should be "1", so the threshold value of the memory cell is 1.5V. In the following, control gate C
When G4 becomes 2V, the bit line potential becomes "L" depending on the memory cell. After that, the signal VRFY1 becomes “H”, so that “1” is already written and data1 is “0”.
When writing is shown, the bit line BL is "H" ((1) in FIG. 9), otherwise the bit line BL is "L" (in FIG. 9).
(2)).

In the verify read first cycle at the time of writing "2" data (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), control is performed. Gate CG4 is 2
When it becomes V, the bit line potential becomes "L" by the memory cell ((5) in FIG. 9). When the selected memory cell is sufficiently written with “2”, the bit line potential remains “H” even when the control gate CG4 becomes 2V ((3) in FIG. 9).
(Four)). In (3) of FIG. 9, writing “2” is already sufficient and dat
This is the case where a1 indicates "0" writing. In this case, since the signal VRFY1 becomes "H", the voltage VBH
Causes the bit line BL to be recharged.

<Verify Read Second Cycle>
In the second verify read cycle at the time of writing "0" data (initial write data is "0"), the data of the memory cell is "0", so the control gate CG4
Becomes 0.5 V, the bit line potential becomes "L" depending on the memory cell. After that, the signal VRFY1 becomes "H", and the bit line BL becomes "H".

In the verify read second cycle at the time of writing "1" data (initial write data is "1"), if the data of the selected memory cell is not "1"("1" write is insufficient), control is performed. When the gate CG4 becomes 0.5V, the bit line potential becomes "L" by the memory cell ((8) in FIG. 9). Selected memory cell is "1"
When the writing is sufficient, the bit line potential remains “H” even if the control gate CG4 becomes 0.5 V ((6) (7) in FIG. 9). (6) in FIG. 9 is a case where "1" write is already sufficient and data1 indicates "0" write. In this case, since the signal VRFY1 becomes "H",
The bit line BL is recharged by the voltage VBH.

In the second verify read cycle at the time of writing "2" data (initial write data is "2"), the data of the memory cell should be "2", so that the threshold value of the memory cell is 0. If the voltage is 5 V or more, "2" writing is sufficient or not enough, the control gate CG4
The bit line potential remains "H" even when the voltage becomes 0.5 V ((9) (10) in FIG. 9). When the "2" write is insufficient and the threshold voltage of the memory cell is 0.5 V or less, the bit line becomes "L" ((11) in FIG. 9).

After that, the signals VRFY1, VRFY2, F
When IH becomes "H", if "2" write is already sufficient and data1 indicates "0" write, the bit line BL is "H" ((9) in FIG. 9), otherwise the bit line BL.
Is "L" ((10) (11) in FIG. 9).

By this verify read operation, the write data and the rewrite data from the write state of the memory cell are set as shown in (Table 3) below.

[0079]

[Table 3]

As can be seen from (Table 3), "1" writing is performed again only for the memory cells in which "1" writing is insufficient.
The "2" write is performed again only to the memory cells in which the "2" write is insufficient.

Here, since N1 and N2 are both "H" in the memory cell in which "1" is not sufficiently written, Qn13A, Qn
13B is turned "ON", and RENDB2 is discharged from the precharge potential. That is, if there is even one memory cell in which "1" is not sufficiently written, RENDB2 becomes "L". Detecting that RENDB2 is discharged to "L", verify read is performed to check whether "1" write is sufficient in the next verify read (after rewriting).

On the other hand, when all the memory cells to be written "1" are sufficiently written, the node N1 becomes "L" in all columns to which "1" is written, so that Qn13A becomes "O".
FF ”, and as a result, the RENDB2 maintains the precharge potential. Therefore, the“ 1 ”data write completion detection circuit 4 detects that the potential of the RENDB2 does not become“ L ”and remains“ H ”. As a result, as shown in FIGS. 1 and 10, in the next verify read (after rewriting), the verify read for checking whether "1" is sufficiently written is not performed, but only the verify read for checking whether "2" is sufficiently written is performed. .

In the memory cell of "0" write or "2" write, N2 is "L", so Qn13B is "OFF",
RENDB2 is never discharged from the precharge potential. Therefore, all write data is "0" or "2".
In the case of, RENDB2 maintains the "H" level. Also,
In the write data of “0” write, N1 is “L”, N2
Does not have to be "L". That is, the write data for writing "0" may be N1 "L" and N2 "H". In this case, N1 is "L", so Qn13A is "OFF".
However, RENDB2 keeps "H" level, and RENDB2
Does not discharge from the precharge potential.

A state of omitting the verify read for checking whether the "1" write memory cell is sufficiently written will be described with reference to FIG. RENDB when writing “1” is insufficient
Since 2 is "L", rewriting, the first verify read cycle and the second verify read cycle are repeated as shown in FIG.

On the other hand, if all the memory cells to be written "1" are sufficiently written and some of the memory cells to be written "2" are not sufficiently written, RENDB2 is "H" and RENDB1 is "L". In the next verify read (after rewriting), only the verify read that checks whether the "2" write is sufficient is performed without performing the verify read that checks whether the "1" write is sufficient.

When the data writing is sufficient in all the memory cells, Qn13 of all columns are turned off and the signal RENDB1 is turned to "H". RENDB1
Is set to "H", the data write end detection circuit 4
The data write end information is output by the detection by.

As described above, in the present embodiment, the unnecessary verify read operation can be omitted and the writing time can be greatly shortened. Further, in the present embodiment, the operation of omitting the unnecessary verify read is realized only by increasing the number of transistors by 2 as compared with the conventional example. Therefore, the area required for realizing this operation is not increased. small.

The following (Table 4) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0089]

[Table 4]

[Fifth Embodiment] FIG. 11 shows a specific structure of a memory cell array 1 and a bit line control circuit 2 of a NOR cell type EEPROM according to a fifth embodiment of the present invention.

The memory cell M10 alone constitutes a NOR type cell. One end of the NOR type cell is connected to the bit line BL and the other end is connected to the common ground line. The memory cells M sharing one control gate WL form a page. The memory cell stores data at the threshold value Vt, and Vt is V
It is stored as "0" data when it is cc or more, "1" data when Vt is Vcc or less and 2.5V or more, and "2" data when Vt is 2.5V or less and 0V or more.

One memory cell has three states,
Two memory cells can be combined in nine ways. Of these combinations, eight combinations are used to store 3-bit data in two memory cells. In this embodiment, 3-bit data is stored in a set of two adjacent memory cells sharing a control gate.

Clock synchronous inverters CI5 and CI6
And CI7 and CI8 form flip-flops respectively and latch write / read data. They also operate as sense amplifiers. The flip-flop composed of the clock synchronous inverters CI5 and CI6 latches "write" 0 ", write" 1 "or" 2 "" as write data information, and the memory cell reads ""Holdinformation" 0 "or information" 1 "or" 2 "?" Is latched as read data information. The flip-flop composed of the clock synchronous inverters CI7 and CI8 latches "whether" 1 "is written or" 2 "is written" as write data information, and the memory cell is "2". Whether information is held or "0" or "1" information is held "is latched as read data information.

Of the n-channel MOS transistors, Qn
18 is a voltage V when the precharge signal PRE becomes “H”
Transfer PR to bit line. In Qn19, the bit line connection signal BLC becomes "H" to connect the bit line to the main bit line control circuit. Qn20 ~ Qn23, Qn25 ~ Qn28
Selectively transfers the voltages VBLH, VBLM, 0V to the bit line in accordance with the data latched in the above flip-flop. Qn24 and Qn29 connect the flip-flop and the bit line when the signals SAC2 and SAC1 become "H", respectively. Qn30 is provided to detect whether or not the data for one page latched by the flip-flops are all the same. Qn35, Qn36
Is a data batch detection MOS transistor, and is provided to detect whether all the memory cells to be written “1” in the same page are sufficiently written. Q
The column selection signals CSL1 and CSL2 of the n31, Qn32 and Qn33, Qn34 become "H", respectively, to selectively connect the corresponding flip-flops and the data input / output lines IOA, IOB.

Next, the EEPROM configured as described above
The operation will be described with reference to FIGS. FIG. 12 shows a read operation timing, FIG. 13 shows a write operation timing, and FIG. 14 shows a verify read operation timing.

<Read Operation> The read operation is shown in FIG.
It is executed in two basic cycles as shown in. In the first read cycle, the voltage VPR becomes the power supply voltage Vcc and the bit line is precharged, and the precharge signal PRE becomes "L", and the bit line is floated. Subsequently, the control gate WL is set to 2.5V. Only when the Vt of the selected memory cell is 2.5 V or less,
That is, only when the data "2" is written, the bit line becomes "L" level.

After this, the sense activation signals SEN2 and SE
N2B is "L", "H", respectively, and latch activation signal L
AT2 and LAT2B are set to "L" and "H", respectively, and the flip-flop composed of the clock synchronous inverters CI7 and CI8 is reset. Signal SAC
2 becomes "H" and the clock synchronous inverter CI7,
The flip-flop constituted by CI8 is connected to the bit line, and the sense activation signals SEN2 and SEN2B are first set to "H" and "L" to sense the bit line potential, and then the latch activation signal LAT2. The LAT2B becomes "H" and "L", respectively, and the flip-flop composed of the clock synchronous inverters CI7 and CI8,
The information ““ 2 ”data,“ 1 ”or“ 0 ”data” ”is latched.

In the second read cycle, the voltage of the selection control gate WL is 2.5 V with respect to the first read cycle.
Not Vcc, the signals SEN2, SEN2B,
Signal SEN instead of LAT2, LAT2B, SAC2
The difference is that 1, SEN1B, LAT1, LAT1B, and SAC1 are output. Therefore, in the second read cycle, the flip-flop composed of the clock-synchronous inverters CI5 and CI6 reads "0" data or "1" data.
Alternatively, the information “2” data ”is latched. The data written in the memory cell is read by the two read cycles described above.

<Write Operation> Prior to the data write, the data in the memory cell is erased and the threshold value Vt of the memory cell is Vcc or more. Erasing is performed by setting the control gate WL to 20V and the bit line to 0V. Depending on the write data, the flip-flop nodes N1 and N2 in the bit line control circuit of FIG. 11 are as shown in (Table 5) below.

[0100]

[Table 5]

In the write operation, as shown in FIG.
First, the precharge signal PRE becomes "L" and the bit line is floated. Signal VRFY1, VRFY
2, FIM and FIL become Vcc. In the case of writing "0", since the data is latched in the flip-flop composed of the clock synchronous inverters CI5 and CI6 so that the output of the clock synchronous inverter CI5 becomes "H", the bit line is It is 0V. In the case of writing "1" or "2", the bit line is charged to Vcc.

Then, the signals BLC, VRFY2, FI
M, FIL, voltage VSA is 10V, voltage VBLH is 8
V and voltage VBLM become 7V. In the case of writing "1", since the data is latched in the flip-flop composed of the clock synchronous inverters CI7 and CI8 so that the output of the clock synchronous inverter CI7 becomes "H", the bit line BL Is applied with 7V.
The bit line becomes 8V when "2" is written, and 0V when "0" is written. After that, the selected control gate WL is set to -12V.

In the case of writing "1" or "2", electrons are emitted from the charge storage layer of the memory cell due to the potential difference between the bit line BL and the control gate WL, and the threshold value of the memory cell drops. In the case of "1" write, the amount of charge to be discharged from the charge storage layer of the memory cell must be reduced as compared with "2" write, so that the bit line BL is set to 7V and the potential difference from the control gate WL is set. It is relaxed to 19V. At the time of writing "0", the threshold voltage of the memory cell is not effectively changed by the bit line voltage 0V.

<Verify Read Operation> After the write operation, the write state of the memory cell is confirmed, and the additional write is performed only to the memory cell in which the write is insufficient. Therefore, the verify read is performed. A timing chart of the verify read operation is shown in FIG. 14, and an outline of the operation is shown in FIG. During verify read, voltage VBLH is Vcc and FIM is 0V
It is.

Verify read is executed from two basic cycles. This basic cycle is similar to the read cycle. The difference is that the voltage of the selected control gate WL and the signals VRFY1, VRFY2 and FIL are output (only VRFY1 in the first verify read cycle). Signal VRFY1, VRFY2, FI
L is output after the control gate WL is reset to 0V and before the signals SEN1, SEN1B, LAT1, and LAT1B become "L", "H", "L", "H", respectively. In other words, after the potential of the bit line is determined by the threshold value of the memory cell and before the flip-flop composed of the clock synchronous inverters CI5 and CI6 is reset. The voltage of the selected control gate WL is 2.5 V (first cycle) at the time of reading, Vcc
Corresponding to (second cycle), 2V (first cycle),
4V (second cycle), which is set low in order to secure a threshold margin.

Here, the clock synchronous inverter CI
5, the data (data1) latched in the flip-flop composed of CI6 and the data (data2) latched in the flip-flop composed of the clock synchronous inverters CI7 and CI8 and the selected memory cell The voltage of the bit line BL determined by the threshold value will be described. data1 is “0” write or “1”
Or "2" write "is controlled. When" 0 "is written, Qn20 is" ON ", and when" 1 "or" 2 "is written, Qn23 is" ON ". data2 controls “whether“ 1 ”writing or“ 2 ”writing”,
When writing "1", Qn26 is "ON", "2"
In the case of writing, Qn27 is in the "ON" state.

<Verify Read First Cycle>
In the verify read first cycle at the time of writing “0” data (initial write data is “0”), since the data of the memory cell is “0”, the bit line potential is “H” even if the control gate WL becomes 2V. “It remains. After that, the signal VRFY1 becomes "H", so that the bit line B
L becomes "L".

In the verify read first cycle at the time of writing "1" data (initial write data is "1"), the data of the memory cell should be "1", so the threshold value of the memory cell is 2.5V. With the above, the control gate W
Even if L becomes 2V, the bit line potential remains "H". After that, when the signal VRFY1 becomes “H”, the “1” write is already sufficient and the data1 indicates “0” write, the bit line BL is “L” ((2) in FIG. 14).
), Otherwise, the bit line BL is “H” ((1) in FIG. 14)
Becomes

In the verify read first cycle at the time of writing "2" data (initial write data is "2"), if the data of the selected memory cell is not "2"("2" write is insufficient), control is performed. Gate WL is 2V
The bit line potential is still "H" ((3) in FIG. 14).
). When the selected memory cell is sufficiently written with "2", the bit line potential becomes "L" by the memory cell when the control gate WL becomes 2V ((4) (5) in FIG. 14).
In FIG. 14, (5) is a case where "2" write is already sufficient and data1 indicates "0" write. In this case, the signal VRFY1 becomes "H", and the bit line BL is grounded.

<Verify Read Second Cycle>
In the second verify read cycle at the time of writing "0" data (initial write data is "0"), the data of the memory cell is "0", so the control gate CG4
Is 4V, the bit line potential is "H". After that, the signal VRFY1 becomes “H”, and the bit line BL
Becomes "L".

In the verify read second cycle at the time of writing "1" data (initial write data is "1"), if the data of the selected memory cell is not "1"("1" write is insufficient), control is performed. Gate WL is 4V
The bit line potential is still "H" ((6) in FIG. 14).
). When the selected memory cell is sufficiently written with "1", the bit line potential becomes "L" by the memory cell when the control gate WL becomes 4V ((7) (8) in FIG. 14). FIG. 14 (8) shows a case where "1" write is already sufficient and data1 indicates "0" write. In this case, the signal VRFY1 becomes "H", and the bit line BL is grounded.

In the verify read second cycle at the time of writing "2" data (initial write data is "2"), the data of the memory cell is supposed to be "2". If there is enough "2" writing, the bit line potential becomes "L" when the control gate WL becomes 4V ((10) (11) in FIG. 14).
When the "2" write is insufficient and the threshold voltage of the memory cell is 4 V or more, the bit line becomes "H" ((9) in FIG. 14).

After that, the signals VRFY1, VRFY2, F
When IH becomes “H”, “2” write is already sufficient and data1 indicates “0” write, bit line BL is “L” ((11) in FIG. 14), and bit line B is otherwise.
L becomes "H" ((9) (10) in FIG. 14).

By this verify read operation, the write data and the rewrite data from the write state of the memory cell are set as in the above (Table 3) as in the fourth embodiment.

Here, since N1 and N2 are both "H" in the memory cell in which "1" is not sufficiently written, Qn35, Qn36
Becomes "ON", and RENDB2 is discharged from the precharge potential. That is, if there is even one memory cell in which "1" is not sufficiently written, RENDB2 becomes "L". R
Detecting that ENDB2 is discharged to "L",
"1" at the next verify read (after rewriting)
Perform verify read to check if writing is sufficient.

On the other hand, when all the memory cells to be written "1" are sufficiently written, the node N1 becomes "L" in all columns to which "1" is written, so that Qn35 becomes "OF".
Therefore, the RENDB2 keeps the precharge potential. As a result, the "1" data write end detection circuit 4 detects that the RENDB2 potential does not become "L" but keeps the "H" state. As a result, as shown in FIGS. 1 and 10, in the next verify read (after rewriting), the verify read for checking whether "1" is sufficiently written is not performed, but only the verify read for checking whether "2" is sufficiently written is performed. .

In the memory cell of "0" write or "2" write, N2 is "L", so Qn36 is "OFF".
However, RENDB2 is never discharged from the precharge potential. Therefore, RENDB2 maintains the "H" level even when the write data are all "0" or "2".
Further, the write data for writing “0” does not need to be “L” for N1 and “L” for N2. That is, "0"
The write data for writing may be N1 “L” and N2 “H”. In this case, N1 is "L", so Q
n35 turns "OFF", RENDB2 maintains "H" level, and RENDB2 is never discharged from the precharge potential.

A state of omitting the verify read for checking whether the "1" write memory cell is sufficiently written will be described with reference to FIG. RENDB when writing “1” is insufficient
Since 2 is "L", rewriting and the first verify read cycle and the second verify read cycle are repeated as shown in FIG.

On the other hand, if all the memory cells to be written "1" are sufficiently written and some of the memory cells to be written "2" are not sufficiently written, RENDB2 is "H" and RENDB1 is "L". In the next verify read (after rewriting), only the verify read that checks whether the "2" write is sufficient is performed without performing the verify read that checks whether the "1" write is sufficient.

When the data writing is sufficient in all the memory cells, Qn30 of all columns are turned "OFF" and the signal RENDB1 becomes "H". RENDB1
Is set to "H", the data write end detection circuit 4
The data write end information is output by the detection by.

The following (Table 6) shows the potential of each part of the memory cell array at the time of erasing, writing, reading and verify reading.

[0122]

[Table 6]

The circuits shown in FIGS. 6 and 11 can be modified as shown in FIGS. 15 and 16, respectively. In FIG. 15, the n-channel transistors Qn3 and Qn4 shown in FIG. 6 are replaced with p-channel transistors Qp1 and Qp2. In FIG. 16, the n-channel transistors Qn22, Qn23, Qn25 to Qn28 shown in FIG. 11 are replaced with p-channel transistors Qp3 to Qp8. By doing so, it is possible to prevent the transferable voltage from dropping due to the threshold value of the n-channel transistor, and in this example, the voltage VSA may be raised to 8 V at the time of writing, and the breakdown voltage of the transistor forming the circuit is lowered. be able to. VRFY1B in FIG. 15 is an inverted signal of VRFY1 in FIG. 6, and VRFY2B, FILB, and FIMB in FIG. 16 are V in FIG.
These are inversion signals of RFY2, FIL, and FIM.

[Embodiment 6] Like the second embodiment, here, for example, in a ternary memory cell, detection of the end of writing of a memory cell in which "1" is written and completion of writing of a memory cell in which "2" is written are completed. A specific example of the embodiment in which the above detection is performed together will be described.

FIG. 17 shows an embodiment when applied to a NAND type EEPROM, and FIG. 18 shows an embodiment when applied to a NOR type EEPROM. The difference from the fourth and fifth embodiments is that a detection circuit for detecting the end of writing of a memory cell for writing "1" is provided in addition to a detection circuit for detecting the end of writing for a memory cell for writing "1". . In FIG. 17 and FIG. 18, the first data batch detection MOS transistor unit (Qn13A, Qn13B in FIG. 17, Qn35, Qn36 in FIG. 18) is a circuit for detecting the end of writing of the memory cell in which “1” is written. 2 data batch detection MOS transistor unit (Qn13C,
Qn13D, in FIG. 18, Qn37, Qn38) is a circuit for detecting the end of writing of the memory cell in which "2" is written.

The write data of the memory cell may be the same as in the fourth and fifth embodiments. Similar to the fourth and fifth embodiments, RENDB1 is a signal for detecting the end of writing of all data, and RENDB2 is a signal for detecting whether or not a memory cell for writing "1" is sufficiently written.

Then, RENDB4 is a signal for detecting whether or not the memory cell for writing "2" is sufficiently written. The write completion batch detection for the "2" write memory cell is described in the fourth and fifth embodiments.
This may be performed almost in the same manner as the batch completion detection of the "1" write memory cells.

First, prior to collective detection, RENDB4 is precharged to a constant potential. Since N3 is "H" in the memory cell in which "2" is written, the MOS transistor Qn13D (Qn38 in FIG. 18) of FIG. 17 is turned on. As described in the fourth and fifth embodiments, when the "2" write is completed, N1 of the memory cell to which the "2" write is performed becomes "L". Therefore, Qn13C in FIG. 17 (in FIG. 18, Qn37) turns "OFF", and RENDB4 maintains the precharge potential. On the other hand, if "2" is not sufficiently written, "2"
Since N1 of the memory cell to be written is “H”, FIG.
Qn13C (Qn37 in Fig. 18) turns "ON" and REND
B4 is discharged from the precharge potential. On the other hand, since N1 is "L" in the memory cell for writing "0", Qn13C (Qn37 in FIG. 18) of FIG. 17 is turned off, and RENDB4
Keeps the precharge potential. In the memory cell in which "1" is written, N3 is "L" regardless of whether the writing is sufficient or insufficient, so that RENDB4 maintains the precharge potential.

As described above, by detecting RENDB4, it is possible to detect whether the "2" write memory cell has been sufficiently written. The write operation may be outlined as in the second embodiment.

[Embodiment 7] According to the present invention, when data is written to a multi-valued memory cell by a data batch detection MOS transistor unit connected to a bit line control circuit, for example, writing of "1" to a memory cell is completed. Alternatively, it is possible to detect the end of writing of the memory cell in which “2” is written. If this data batch detection MOS transistor unit is used, the first write data is detected and, for example, in a ternary memory cell, "1"
If there is no write data, the verify read of "1" write can be omitted from the beginning.

Explaining with reference to FIG. 17, the RE before inputting the write data to the bit line control circuit.
Precharge NDB2 and RENDB4. afterwards,
Data is loaded into a latch formed of inverters CI1, CI2, CI3, CI4.

When there is no "1" in the write data,
At least one of N1 and N2 becomes "L", and Qn13B
Alternatively, since at least one of Qn13A is turned "OFF", RENDB2 maintains the precharge potential. In the bit line control circuit for write data “1”, the data is latched at N
Since both 1 and N2 become "H", RENDB2 is discharged from the precharge potential.

By detecting the potential of RENDB2 in this way, it is possible to detect whether or not there is "1" write data. When there is no "1" write data, "1" write is performed from the first verify read. It suffices not to perform the verify read that checks whether the operation has been performed sufficiently.

Similarly, it is possible to precharge RENDB4 before data loading, detect the potential of RENDB4 after loading the data of the bit line control circuit, and detect whether or not there is "2" write data. You can In other words, when there is no "2" write data, RENDB4 maintains the precharge potential, and when there is "2" write data, RENDB4 is discharged from the precharge potential. The potential of this RENDB4 may be detected. That is, when RENDB4 is discharged, the verify read for checking whether "2" has been sufficiently written from the first verify read is not performed. By thus omitting unnecessary verify read, the entire write time can be shortened.

The present invention is not limited to the above-described embodiments, and various modifications can be carried out without departing from the scope of the invention. The present invention can be applied to the NAND type EEPROM and the N type EEPROM described in the embodiment.
Not only OR type EEPROM but also AND type (K. Kume et
al.; IEDM Tech. Dig., Dec. 1992, pp.991-993),
DINOR type (S.Kobayashi et al .; ISSCC Tech. Di
g., 1995, pp.122), or virtual ground type array (R. Ceme
a et al .; ISSCC Tech. Dig., 1995, pp.126).

[Embodiment 8] In this embodiment, the four-valued memory cell described in the third embodiment is more concretely described.

The flowchart showing the write operation is the same as that shown in FIG. In the present invention, the entire write time is shortened by omitting unnecessary verify read. That is, after the first write, the verify read first cycle for checking whether "3" writing is sufficiently performed,
A verify read second cycle for checking whether "2" writing is sufficiently performed and a verify read third cycle for checking whether "1" writing is sufficiently performed.

If there is a memory cell in which "1" has been written but the writing is insufficient, reprogramming is performed.
In this reprogramming, writing is also performed on a memory cell for which "2" writing is insufficient or for a "3" writing insufficient memory cell.

After the memory cell to be written "1" is sufficiently written, the third verify read cycle for checking whether the "1" write is sufficiently performed is no longer necessary. Therefore, as shown in FIG. Verify read 1st time for rewriting and checking if "3" writing is sufficient until the memory cell for 2 "writing is sufficiently written.
In the cycle, a second verify read cycle is performed to check whether "2" writing is sufficient.

After the memory cells to be "2" written have been sufficiently written, the second verify read cycle for checking whether the "2" writing has been sufficiently performed is no longer performed. That is, as shown in FIG. 3, rewriting and only the first verify read cycle in which it is checked whether "3" writing is sufficient are performed until the memory cells to be written "3" are sufficiently written.

In the following, the present invention will be described as a NAND type EEPROM.
An embodiment in the case of being applied to the M 4-level memory cell will be described.

FIG. 21 shows the structure of a multi-value storage type EEPROM. A control gate / select gate drive circuit 20 for selecting a memory cell and applying a write voltage and a read voltage to a control gate is provided for a memory cell array 10 configured by arranging memory cells in a matrix. The control gate / select gate drive circuit 20 is connected to the address buffer 50 to receive an address signal.
The data circuit 30 is a circuit for holding write data and reading data in a memory cell.
The data circuit 30 is connected to the data input / output buffer 40 and receives an address signal from the address buffer 50. The data input / output buffer 40 controls data input / output with the outside of the EEPROM.

FIG. 22 shows the memory cell array 10 and the data circuit 30 shown in FIG. Memory cell M
1 to M4 are connected in series to form a NAND type cell. Both ends thereof are connected to the bit line BL and the source line Vs via the selection transistors S1 and S2, respectively. The memory cells M group sharing the control gate CG form a unit called "page", and data is written / read at the same time. In addition, four control gates CG1 to C
A block is formed by the memory cell group connected to G4. The “page” or “block” is selected by the control gate / select gate drive circuit 20. Each bit line BL0A-BL
The data circuits 30-0 to 30-m are connected to the mA and temporarily store the write data to the corresponding memory cells. Since this embodiment has an open bit line arrangement, bit lines BL0B to BLmB are also connected to the data circuit.

FIG. 23 shows the threshold voltage of the memory cell M and four write states (four-level data "0", "1") in the case of storing four values by providing the memory cell M with four write states. , “2”, “3”). The state of data “0” is the same as the state after erasing,
For example, it has a negative threshold. The "1" state is, for example, 0.
It has a threshold between 5V and 0.8V. The "2" state has a threshold value between 1.5V and 1.8V, for example. The "3" state has a threshold value between 2.5V and 2.8V, for example.

The read voltage VCG2R is applied to the control gate CG of the memory cell M to turn the memory cell "ON" or "O".
It is possible to detect "0", "1", "2", "3""in the memory cell data by" FF ". Then, by applying the read voltages VCG3R and VCG1R, the data in the memory cell is completely detected. Read voltage VC
G1R, VCG2R and VCG3R are, for example, 0V, 1V,
It is set to 2V. The voltages VCG1V, VCG2V and VCG3V are called verify voltages, and at the time of data writing, these verify voltages are applied to the control gate to detect the state of the memory cell M and check whether or not sufficient writing has been performed.
For example, they are set to 0.5V, 1.5V, and 2.5V, respectively.

FIG. 24 shows a data circuit. The data circuit includes two latch circuits (a first latch circuit and a second latch circuit). At the time of writing, 2-bit write data is stored in these two latch circuits. At the time of reading, the read four-valued data is stored in the two latch circuits and then output to the outside of the chip via IO1 and IO2.

512 bits (column addresses A0, A1
, A2, ..., A510, A511)
The case of reading will be described as an example.

<Write> First, the write data at the head address A0 is input to and held in the first latch circuit RT1-0. Then, the addresses A1, A2, ..., A
The write data of 254 and A255 is the first latch circuit R.
.., RT1-254, RT1-255 are input and held. And the addresses A256, A257, ...,
The write data of A510 and A511 is input to the second latch circuits RT2-0, RT2-1, ..., RT2-254, RT2-255 and held therein. After that, writing is performed in the memory cell according to the 2-bit write data held in the two latch circuits in the data circuit.

If the data is less than 512 bits, the write data is input to the first latch circuit in the data circuit, but the write data is not input to the second latch circuit. In this case, the writing state of the memory cell is "0" state or "1" with a low threshold value.
The write data may be input to the second latch circuit so that the state becomes the state.

<Reading> The reading procedure is shown in FIG. First, the voltage Vp1 between the "1" state and the "2" state is applied to the word line of the memory cell to be read. When the memory cell is in the conductive state, the memory cell is "0" or "1", and when the memory cell is in the non-conductive state, the memory cell is in the "2" or "3" state. Column address A0, A
The read data corresponding to 1, A2, ..., A254, A255 is held in the first latch circuit.

Next, when Vp2 is applied to the selected word line,
It is known whether the memory cell is in the "3" state, or the "0" or "1" or "2" state. The read data is held in the second latch circuit. During this period, the data held in the first latch circuit (column addresses A0, A1
, A2, ..., A254, A255) are output to the outside of the chip via IO1.

Finally, when Vp3 is applied to the selected word line, it is known whether the memory cell is in the "0" state, or "1" or "2" or "3". As a result, the 2-bit information stored in the memory cell is read. The read data corresponding to the column addresses A256, A257, ..., A510, A511 is held in the second latch circuit. Column addresses A0 and A1 held in the first latch circuit
, A2, ..., A254, A255 are output to the outside of the chip, and then the data corresponding to the column addresses A256, A257, ..., A510, A511 held in the second latch circuit is transferred to the chip via IO2. Output to the outside.

In this read method, the read data can be output to the outside immediately after the data is first sensed and held in the first latch circuit. Therefore, the read time is much shorter than that of the conventional example, and the binary value is binary. It becomes almost the same as the case of the memory cell. That is, in the conventional example, the data is output to the outside of the chip after sensing by changing the word line voltage three times, but in the present embodiment, the data is not read after the memory cell is read by first applying the predetermined read voltage to the word. Since it is output to the outside of the chip, the reading speed is increased.

The operation will be described in detail below with reference to the operation timing chart.

FIG. 26 is a specific example of the data circuit 3.
The present embodiment is configured by taking four-value storage as an example. N-channel MOS transistors Qn21, Qn22, Qn23 and p-channel MOS transistors Qp9, Qp10, Qp11 composed of flip-flop FF1 and n-channel MOS transistors Qn29, Qn30, Qn31 and p-channel MOS
FF composed of transistors Qp16, Qp17, Qp18
2, write / read data is latched. Also,
These also operate as sense amplifiers.

The flip-flops FF1 and FF2 are
"Whether writing" 0 "or writing" 1 ",
"2" write or "3" write "is latched as write data information, and whether the memory cell holds" 0 "information or" 1 "information, "Whether information" 2 "is held or information" 3 "is held" is sensed and latched as read data information.

The data input / output lines IOA and IOB and the flip-flop FF1 are connected to the n-channel MOS transistor Q.
It is connected via n28 and Qn27. Data input / output line IO
C, IOD and flip-flop FF2 are connected via n-channel MOS transistors Qn35, Qn36.

Data input / output lines IOA, IOB, IOC,
The IOD is also connected to the data input / output buffer 4 in FIG. n-channel MOS transistors Qn27, Qn28
The gate of is connected to the output of the column address decoder composed of the NAND logic circuit G3 and the inverter I5. The read data held in the flip-flop FF1 is output to IOA and IOB by activating CENB1. The gates of the n-channel MOS transistors Qn35 and Qn36 are connected to the output of the column address decoder composed of the NAND logic circuit G2 and the inverter I4. The read data held in the flip-flop FF2 is output to IOC and IOD when CENB2 is activated.

N-channel MOS transistors Qn26, Q
n34 equalizes the flip-flops FF1 and FF2 with the signals ECH1 and ECH2 being "H". The n-channel MOS transistors Qn24 and Qn32 are
It controls the connection between the flip-flops FF1 and FF2 and the MOS capacitor Qd1. The n-channel MOS transistors Qn25 and Qn33 are flip-flops FF1 and FF.
2 and the MOS capacitor Qd2 are controlled.

P-channel MOS transistor Qp12C,
The circuit composed of Qp13C is the activation signal VRFYBA.
C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF1.
The circuit composed of the p-channel MOS transistors Qp14C and Qp15C is activated by the activation signal VRFYBBC.
The gate voltage of the MOS capacitor Qd2 is changed according to the data of the flip-flop FF1. p channel M
The circuit composed of the OS transistors Qp12C, Qp19C and Qp20C is changed by the activation signal VRFYBA2C.
The gate voltage of the MOS capacitor Qd1 is changed according to the data of the flip-flops FF1 and FF2.

P channel MOS transistor Qp14C,
The circuit composed of Qp21C and Qp22C has an activation signal V
RFYBB2C changes the gate voltage of the MOS capacitor Qd2 according to the data of the flip-flops FF1 and FF2. The circuit composed of the n-channel MOS transistors Qn1C and Qn2C has an activation signal VRF.
The YBA 1C changes the gate voltage of the MOS capacitor Qd1 according to the data of the flip-flop FF2. n-channel MOS transistor Qn3C, Qn4C
The circuit constituted by M is responsive to the data of the flip-flop FF2 by the activation signal VRFYBB1C.
The gate voltage of the OS capacitor Qd2 is changed.

The MOS capacitors Qd1 and Qd2 are composed of depletion type n-channel MOS transistors and are sufficiently smaller than the bit line capacitance. n channel M
The OS transistor Qn37 is switched to MO by the signal PREA.
The S capacitor Qd1 is charged to the voltage VA. The n-channel MOS transistor Qn38 is set to M by the signal PREB.
The OS capacitor Qd2 is charged to the voltage VB. The n-channel MOS transistors Qn39 and Qn40 are connected to the signal BLC.
The data circuit 30 and the bit line BL are controlled by A and BLCB.
The connection of a and BLb is controlled respectively. n-channel MO
The circuit composed of the S transistors Qn37 and Qn38 also serves as the bit line voltage control circuit.

N-channel MOS transistors Qn7C, Q
The first data batch detection MOS transistor unit composed of n8C detects the end of writing of the memory cell in which "1" is written. The second data batch detection MOS transistor unit composed of the n-channel MOS transistors Qn9C and Qn10C detects the end of writing of the memory cell to which "2" is written.

In the following, the case where the control gate CG2A is selected is shown.

<Read Operation> FIG. 27 shows the read method of this embodiment. First, at time tw1, the voltages VA and VB become 1.8V and 1.5V, respectively, and the bit lines BLa and
BLb becomes 1.8V and 1.5V, respectively. Next, the signals PREA and PREB become "L", and the bit line BL
a and BLb become floating. Then, time tw2
The selected control gate CG2A of the block selected by the control gate / select gate drive circuit 20 is 1V,
The non-selection control gates CG1A, CG3A, CG4A and the selection gates SG1A, SG2A are set to VCC. If the threshold value of the selected memory cell is 1 V or less, the bit line voltage will be lower than 1.5 V. If the threshold value of the selected memory cell is 1 V or more, the bit line voltage remains at 1.8 V. After that, the signals SAN2 and SAP2 become "L" and "H", respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes "H" and are equalized. After that, the signals RV2A and RV2B become "H" at the time t3w. At time tw4, the signals SAN2 and SAP are again displayed.
2 becomes "H" and "L" respectively, so that the node N1
Are sensed and latched. Thus, "whether the data in the memory cell is" 0 "or" 1 "or" 2 "or" 3 "" is sensed by the flip-flop FF2 and the information is latched.

The data held in the flip-flop FF2 is output to the outside of the chip when CENB2 is activated at time tw5.

Next, it is determined whether the threshold value of the memory cell is 0V or higher or 0V or lower. At time tw5, the bit line BLa is set to 1.8V and the dummy bit line BLb is set to 1.5V.
It is precharged to and then floated.
After that, the control gate selected at time tw6 is set to 0V. If the threshold of the selected memory cell is 0V or less,
The bit line voltage will be lower than 1.5V. If the threshold voltage of the selected memory cell is 0 V or higher, the bit line voltage is 1.
It remains at 8V. The signals SAN1 and SAP1 become "L" and "H", respectively, and the flip-flop FF1 is inactivated, and the signal ECH1 becomes "H" and is equalized. After that, the signals RV1A and RV1B become "H" at time tw7. At time tw8, the signals SAN1 and SAP1 become "H" and "L", respectively, so that the voltage of the node N1 is sensed and latched. Now, "the data of the memory cell is" 0 ", or" 1 "or" 2 "or" 3 "
Is sensed by flip-flop FF1,
That information is latched. Flip-flop F at this time
The potentials of the nodes N3C and N5C of F1 and FF2 are as shown in (Table 7) below.

[0168]

[Table 7]

Finally, the data written in the memory cell is "whether" 0 "or" 1 "or" 2 "or" 3 "".
Is sensed. Bit line BLa is 1.8 V at time tw9
Then, the dummy bit line BLb is precharged to 1.5V, and then floated. After that, time tw1
The control gate selected to 0 is brought to 2V. If the threshold of the selected memory cell is less than 2V, the bit line voltage will be less than 1.5V. If the threshold voltage of the selected memory cell is 2V or higher, the bit line voltage remains 1.8V. VRFYBA2C becomes 0V at time tw11.

As can be seen from (Table 7), it is "1" that the node N5C becomes "Low level" and the node N3C becomes "High level" (that is, the node N4C becomes "Low level").
Only for data. Therefore, the p-channel MOS transistors Qp12C, Qp19C, Q only when the data is "1"
p20C turns on, and the node N1 becomes VCC.

After that, the signals SAN1 and SAP1 are set to "L" and "H", respectively, to inactivate the flip-flop FF1, and the signal ECH1 is set to "H" and equalized. After this, at time tw12, the signals RV1A, RV1
B becomes "H". At time tw13, the signals SAN1,
When SAP1 becomes “H” and “L”, respectively, the voltage of the node N1 is sensed and latched. Then, "whether the data in the memory cell is" 0 "," 1 "," 2 ", or" 3 "" is sensed by the flip-flop FF1 and the information is latched.

The data held in the flip-flop FF1 is output to the outside of the chip by activating CENB1 at time tw14.

As a result of the above read operation, the four-valued data are flip-flops FF1, F as shown in (Table 8) below.
Latched to F2.

[0174]

[Table 8]

The threshold distribution of each data in (Table 8) is as follows.

Data "0" ... Threshold value: 0 V or less Data "1" ... Threshold value 0.5 V or more and 0.8 V or less Data "2" ... Threshold value 1.5 V or more 8V or less Data "3" ... Threshold value 2.5V or more and 2.8V or less During reading, the signals VRFYBAC and VRFYBBC are "H", and the signals VRFYBA1C and VRFYBB1C are "L". The voltage Vs is 0V.

Data stored in memory cells, threshold values, data input / output lines IOA, IOB, IOC, IOD
The relationship between the levels output after the reading is shown in Table 8.

<Write Operation> First, write data is loaded into the flip-flops FF1 and FF2. After that, "1" data, "2" data and "3" data are written almost at the same time. Then, verify read is performed to check whether "1" data, "2" data, and "3" data have been sufficiently written, and if there is an insufficiently written memory cell, rewriting is performed. Writing is completed when the write completion detection circuit detects that all memory cells are sufficiently programmed.

In the following, the program will be described first,
Next, the verify read will be described.

(1) Before the program write operation, the input data is converted by the data input / output buffer 4 and input to the data circuit 3.
4-value data and data input / output lines IOA, IOB, IOC,
The IOD relationship is as shown in (Table 9) below.

[0181]

[Table 9]

At this time, assuming that there are 256 data circuits (that is, assuming that the page length is 256), the first 256-bit write data that was input is IOA when the column activation signal CENB1 is "H". , IOB to the flip-flop FF1. When the column activation signal CENB2 is "H", write data of 256 bits or more input from the outside is IOC, IOD.
Via flip-flop FF2.

As can be seen from (Table 8) and (Table 9), IO
Input to the flip-flop 1 via A and IOB,
Regarding the written data, the read data is output to the flip-flop 2 at the time of reading, and then,
It is output to the outside of the chip via IOC and IOD. That is, for the data to which the write data is input from the IOA, the data control may be performed by the data input / output buffer so that the read data is output from the IOD. Similarly,
Regarding the data to which the write data is input from the IOB, the data control may be performed by the data input / output buffer so that the read data is output from the IOC.

On the other hand, flips through IOC and IOD.
The data input to the flop 2 and written is
At the time of reading, read data is output to the flip-flop 1 and then output to the outside of the chip via IOB and IOA. That is, for the data to which the write data is input from the IOC, the data control may be performed by the data input / output buffer so that the read data is output from the IOB. Similarly, for the data to which the write data is input from the IOD, the data input / output buffer may control the data so that the read data is output from the IOA.

The write operation is shown in FIG. At time t1s, the voltage VA becomes the bit line write control voltage 1V and the bit line BLa becomes 1V. n-channel MOS
When the voltage drop corresponding to the threshold value of the transistor Qn39 becomes a problem, the signal BLCA may be boosted. continue,
The signal PRE becomes "L" and the bit line is floated. Next, at time t2s, the signal RV2A is set to 1.5V. As a result, the bit line control voltage 0V is applied to the bit line from the data circuit holding the data "1" or "3". n channel MOS transistor Q
Assuming that the threshold value of n32 is 1V, the n-channel MOS transistor Qn32 is "O" when "0" or "2" is written.
It becomes “ON” when writing FF ”,“ 1 ”or“ 3. ”After that, VRFYBAC becomes 0V at time t3s,
The bit line write control voltage VCC is output to the bit line from the data circuit that holds the data “0” or the data “1”.

Then, at time t1s, VRFYBA2C becomes 0.
The voltage V becomes V, and the data line holding the data “1” outputs the bit line “1” write potential 2V to the bit line via V1. As a result, the bit line for writing “0” is VCC, the bit line for writing “1” is 2V,
The bit line for writing "2" becomes 1V, and the bit line for writing "3" becomes 0V.

At time t4s, the select gate SG1 of the block selected by the control gate / select gate drive circuit 2 is selected.
A, the control gates CG1A to CG4A become VCC. The selection gate SG2A is at 0V. Next, the selected control gate CG2A becomes the high voltage VPP (for example, 20V), and the non-selected control gates CG1A, CG3A, and CG4A become VM (for example, 10V). In the memory cell corresponding to the data circuit holding the data “3”, electrons are injected into the floating gate due to the potential difference between the channel potential of 0 V and VPP of the control gate, and the threshold value rises.

In the memory cell corresponding to the data circuit holding the data "2", electrons are injected into the floating gate due to the potential difference between the channel potential of 1 V and VPP of the control gate, and the threshold value rises. In the memory cell corresponding to the data circuit holding the data “1”, electrons are injected into the floating gate and the threshold value rises due to the potential difference between the channel potential of 2V and VPP of the control gate. "2"
The channel potential in the case of writing is set to 1V and the channel potential in the case of writing "1" is set to 2V because the electron injection amount is "3" when writing data, "2" writing, and "1" writing. In order to reduce the number of cases.

In the memory cell corresponding to the data circuit holding the data "0", the potential difference between the channel potential and VPP of the control gate is small, so that electrons are not effectively injected into the floating gate. Therefore, the threshold value of the memory cell does not change. During the write operation, signals SAN1 and SAN
2, PREB, BLCB are "H", signals SAP1, SA
P2, VRFYBA1C, RV1A, RV1B, RV2
B, ECH1 and ECH2 are "L", and the voltage VB is 0V.

(2) Verify Read After the write operation, it is detected whether or not the write is sufficiently performed (write verify). If the desired threshold value is reached, the data in the data circuit is changed to "0".
If the desired threshold value has not been reached, the data in the data circuit is held and the write operation is performed again. The write operation and the write verify are all "1" write memory cells, "2" write memory cells and "3".
This is repeated until the memory cell to be written reaches a desired threshold value.

However, as shown in FIG. 3, all "1"
When the first data batch detection MOS transistor unit detects that the writing of the memory cell to be written is completed, the "1" verify read is omitted in the subsequent verify read. Similarly, when all the memory cells for writing “2” have been written, the second data batch detection M
When detected by the OS transistor unit, the "2" verify read is omitted in the subsequent verify read.

This write verify operation will be described with reference to FIGS. 29 and 30.

(2-1) "1" Verify Read First, it is detected whether the memory cell in which "1" is written has reached a predetermined threshold value.

At time t1yc, the voltages VA and VB become 1.8 V and 1.5 V, respectively, and the bit lines BLa and BLb.
Are 1.8V and 1.5V, respectively. The signal BLCA,
BLCB becomes "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Q.
The d2 is separated, and the bit lines BLa and BLb become floating. The signals PREA and PREB become "L", and the nodes N1 and N2 which are the gate electrodes of the MOS capacitors Qd1 and Qd2 are brought into a floating state.

Subsequently, the selected control gate CG2A of the block selected by the control gate / selection gate drive circuit 2 is 0.5 V, and the non-selected control gates CG1A, CG
3A, CG4A and select gates SG1A, SG2A are VC
It is set to C. The threshold value of the selected memory cell is 0.5
Below V, the bit line voltage will be below 1.5V. If the threshold value of the selected memory cell is 0.5 V or more, the bit line voltage remains at 1.8 V.

At time t2yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 are separated from the bit line BLb and the MOS capacitor Qd2. After this, at time t3yc, RV1A becomes 1.5V, which is "2".
In the case of writing and in the case of writing "3", the node N1 is discharged to 0V. Signal VRFY at time t4yc
When BA1C becomes “H”, in the data circuit holding the “0” or “2” write data, the n-channel M
The OS transistor Qn2 is "ON", and the node N1
Becomes VCC. As a result, the node N1 becomes VCC when writing "0" or "2" and becomes 0 V when writing "3".

The signals SAN2 and SAP2 become "L" and "H", respectively, to inactivate the flip-flop FF2, and the signal ECH2 becomes "H" and are equalized. Thereafter, the signals RV2A and RV2B become "H". Again, the signals SAN2, SAP2 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t5yc. Thus, only the data circuit holding the "1" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "1" write state.

If the data in the memory cell is "1", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF2. If the data in the memory cell is not "1", the write data is held at "1" by sensing and latching the voltage of the node N2 by the flip-flop FF1.
The write data of the data circuit holding the "0" or "2" or "3" write data is not changed.

The end of writing of the memory cell to which "1" is written is detected by using the first data batch detection MOS transistor unit of FIG. After the "1" verify read, RNDB1 is first pre-charged to VCC, for example. In a data circuit in which "0", "2", or "3" data is latched, at least one of N3C and N6C is "L" (see Table 9), so at least one of n-channel MOS transistors Qn7C and Qn8C is turned off, RN
DB1 does not discharge from the precharge potential.

On the other hand, if there is even one memory cell in which "1" is not sufficiently written, the nodes N3C and N6C of the data circuit are both "H" (see Table 9) and the n-channel M
Both OS transistors Qn7C and Qn8C are turned on, and RND
B1 drops from the precharge potential.

When all the memory cells to be written "1" are sufficiently written, the node N6C becomes "L". Therefore, the data circuits 30-0, 30-1, ..., 30-m-1, 30-m
At least one of the nodes N3C and N6C in the first data batch detection MOS transistor unit therein is turned off. As a result, RNDB1 maintains the precharge potential,
The end of writing "1" is detected. When all the "1" writes are completed, the "1" verify read is omitted in the subsequent verify read.

(2-2) "2" Verify Read As in the "1" verify read, after precharging the bit line and the dummy bit line, the selected control gate CG2A is set to 1.5V. If the threshold value of the selected memory cell is 1.5V or less, the bit line voltage is 1.5V
Lower. The threshold value of the selected memory cell is 1.
If the voltage is 5V or higher, the bit line voltage remains 1.8V.
At time t6yc, the signals BLCA and BLCB are set to "H", and the potentials of the bit lines are transferred to N1 and N2. After that, the signals BLCA and BLCB become "L", and the bit line BLa and the MOS capacitor Qd1 and the bit line BLb and the MOS capacitor Qd2 are disconnected. After this time t
At 7yc, the signal RV2A is set to 1.5V, which is lower than VCC, for example.

When the threshold value of the n-channel MOS transistor Qn32 is 1 V, the n-channel MOS transistor Qn is used in the data circuit holding the "3" write data.
n32 is "ON", and the node N1 is at 0V. In the data circuit holding the "2" write data, when the memory cell is sufficiently written "2", the n-channel MOS transistor Qn32 is "OFF" and the node N
1 is kept above 1.5V. When the "2" write is insufficient, the voltage at the node N1 is 1.5 V or less. Time t8y
When the signal VRFYBAC becomes "L" at c, the p-channel MOS transistor Qp13 is "ON" in the data circuit holding the "0" or "1" write data, and the node N1 becomes VCC.

The signals SAN1 and SAP1 are set to "L" and "H", respectively, to inactivate the flip-flop FF1, and the signal ECH1 is set to "H" and equalized. Thereafter, the signals RV1A and RV1B become "H". Again, the signals SAN1 and SAP1 are "H",
When it becomes "L", the voltage of the node N1 is sensed and latched at time t9yc. With this, only the data circuit holding the "2" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "2" write state.

If the data in the memory cell is "2", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flop FF1. If the data of the memory cell is not “2”, the write data is held at “2” by sensing and latching the voltage of the node N1 with the flip-flop FF1.
The write data of the data circuit holding the "0" or "1" or "3" write data is not changed.

The end of writing of the memory cell to be written "2" is detected by using the second data batch detection MOS transistor unit of FIG. After "2" verify read, RNDB2 is first pre-charged to, for example, VCC. In a data circuit in which "0", "1" or "3" data is latched, at least one of N4C and N5C is "L" (see Table 9), so at least one of n-channel MOS transistors Qn9C and Qn10C is turned off. , RNDB2 does not discharge from the precharge potential.

On the other hand, if there is even one memory cell for which "2" writing is insufficient, the nodes N4C and N5C of the data circuit are both "H" (see Table 9), and the n-channel M
Both the OS transistors Qn9C and Qn10C are turned on, and RN
DB2 drops from the precharge potential. When all the memory cells to be written "2" are sufficiently written, the node N4C becomes "L". Therefore, the data circuits 30-0, 3
Nodes N4C, N5 in the second data batch detection MOS transistor unit in 0-1, ..., 30-m-1, 30-m
At least one of C is turned off. As a result, RNDB2
Keeps the precharge potential, and the end of writing "2" is detected. When all the "2" writing is completed, the "2" verify read is omitted in the subsequent verify read.

(2-3) "3" Verify Read After the bit line and the dummy bit line are precharged at time t10yc, the selected control gate CG2A is 2.5V.
To be. The threshold voltage of the selected memory cell is 2.5V
Below, the bit line voltage will be lower than 1.5V. If the threshold value of the selected memory cell is 2.5 V or more, the bit line voltage remains at 1.8 V.

Thereafter, at time t11yc, the signals BLCA, BL
CB is set to "H", and the potential of the bit line is transferred to N1 and N2. The signals BLCA and BLCB are again set to "L" to disconnect the bit line BLa from the MOS capacitor Qd1 and the bit line BLb from the MOS capacitor Qd2.
After this, when the signal VRFYBAC becomes "L" at time t12yc, in the data circuit in which the "0" or "1" write data is held and the data circuit in which the "2" write is sufficiently performed, The transistor Qp13 is "ON", and the node N1 becomes VCC. Signal SA
N1 and SAP1 are set to "L" and "H", respectively, and the flip-flop FF1 is deactivated, and the signal ECH1 is set to "H" and equalized.

Thereafter, the signals RV1A and RV1B are "H".
Becomes After that, at time t13yc, the signals SAN1 and SAP1 are sent.
Becomes "H" and "L" respectively, the voltage of the node N1 is sensed and latched.

After this, as shown in FIG. 30, conversion of write data is further performed. At time t14yc, signal B
LCA and BLCB are set to "H" and the potential of the bit line is N
1, N2. Again, the signals BLCA, BLCB
Becomes "L", the bit line BLa is disconnected from the MOS capacitor Qd1, and the bit line BLb is disconnected from the MOS capacitor Qd2.

Thereafter, at time t15yc, the signal VRFYBA1
When C becomes "H", in the data circuit in which "0" or "2" write data is held and the data circuit in which "1" write is sufficient, n channel MOS transistor Qn2C
Is "ON", and the node N1 becomes VCC. Signal S
AN2 and SAP2 become "L" and "H", respectively, and the flip-flop FF2 is deactivated, and the signal ECH2
Becomes "H" and is equalized. After this, the signal RV
2A and RV2B become "H". After that, at time t17yc,
When the signals SAN2 and SAP2 become "H" and "L", respectively, the voltage of the node N1 is sensed and latched.

As described above, only the data circuit holding the "3" write data detects whether or not the data of the corresponding memory cell is sufficiently in the "3" write state. If the data in the memory cell is "3", the write data is changed to "0" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. If the data in the memory cell is not "3", the write data is held at "3" by sensing and latching the voltage of the node N1 by the flip-flops FF1 and FF2. The write data of the data circuit holding the "0" or "1" or "2" write data is not changed.

During write-verify, signal VRFYBB
C is "H", signal VRFYBB1C is "L", voltage Vs
Is 0V.

When all the selected memory cells have reached the desired threshold value, the data in the data circuit becomes "0" data. That is, when the writing is completed, the node N4
C and N6C become "L". By detecting this, it is known whether or not all the selected memory cells have reached the desired threshold. The end of writing is detected, for example, in FIG.
Write completion batch detection transistor Qn5C, as in 6,
And Qn6C may be used. After the verify read, VRTC is first precharged to VCC, for example.

If there is even one memory cell in which writing is insufficient, at least one of the nodes N4C and N6C of the data circuit is "H", so that at least one of the n-channel MOS transistors Qn5C and Qn6C is turned on and VRT is turned on.
C decreases from the precharge potential. When all memory cells are sufficiently written, the data circuits 30-0, 30-1, ...,
The nodes N4C and N6C of 30-m-1 and 30-m become "L". As a result, n-channel MOS in all data circuits
Transistors Qn5C and Qn6C are turned off, so VRT
C maintains the precharge potential.

[Embodiment 9] As shown in FIG. 31, it is possible to detect the end of writing of a memory cell in which "3" is written.
FIG. 31 shows the end of the writing of the memory cell in which “3” is written.
This is detected using the third data batch detection MOS transistor unit. After "3" verify read, first R
NDB3 is precharged to VCC, for example. In the data circuit in which "0", "1" or "2" data is latched, at least one of N4C and N6C is "L" (see Table 9), so the n-channel MOS transistor Qn11C is used.
At least one of Qn12C and Qn12C is turned off, and RNDB3 is not discharged from the precharge potential.

On the other hand, if there is even one memory cell for which "3" writing is insufficient, the nodes N4C and N6C of the data circuit are both "H" (see Table 9), and the n-channel M
Both the OS transistors Qn11C and Qn12C are turned on, and R
NDB3 drops from the precharge potential. When all the memory cells to be written in "3" are sufficiently written, the node N4C becomes "L". Therefore, the data circuits 30-0,
Nodes N4C, N in the third data batch detection MOS transistor unit in 30-1, ..., 30-m-1, 30-m
At least one of 6C is turned off. As a result, RNDB
3 keeps the precharge potential, and the end of writing "3" is detected.

When the "3" write is completed before the "1" write or the "2" write, the third data batch detection MOS transistor unit may be provided as in the present embodiment. By using this third data batch detection MOS transistor unit,
The end of writing "3" can be detected. When all the "3" writes are completed, the "3" verify read is omitted in the subsequent verify read.

[Embodiment 10] The write and verify read procedures are not limited to the example of FIG. For example, if the writing of “2” is completed before the writing of “1”,
The second data batch detection MOS transistor unit in FIG. 26 or FIG. 31 detects the end of writing “2”. As a result, the "2" verify read is omitted in the subsequent verify read, and the "1" and "3" writes are performed thereafter.
“1” verify read and “3” verify read may be performed.

As described above, in the present embodiment, by using the write end detection circuit of the predetermined write level, it is possible to detect the write end of the predetermined write level. After the writing of the predetermined writing level is completed, the verification writing of the writing level is omitted, whereby the total writing speed can be increased. Therefore, the write level for detecting the end of writing is highly arbitrary, and the operation timing is also highly arbitrary.

For example, in the embodiment shown in FIG. 3, first, "3" is set.
Verify read is performed in the order of verify read, “2” verify read, and “1” verify read.
"1" verify read, "2" verify read,
The order may be “3” verify read, or “2” verify read, “3” verify read, and “1” verify read.

[0223]

As described above, according to the present invention, when the multi-valued memory cell is written, the verify read of the data which has been sufficiently written at the time of the verify read is not performed thereafter, so that the unnecessary verify is performed. The read can be omitted, the write time can be shortened, and the write speed can be increased.

[Brief description of drawings]

FIG. 1 is a diagram for explaining an outline of a write operation according to a first embodiment.

FIG. 2 is a diagram for explaining an outline of a write operation according to the second embodiment.

FIG. 3 is a diagram for explaining the outline of a write operation according to the third embodiment.

FIG. 4 is an EEPROM according to fourth and fifth embodiments.
FIG. 2 is a block diagram showing a schematic configuration of FIG.

FIG. 5 is a circuit diagram showing a specific configuration of a memory cell array according to a fourth embodiment.

FIG. 6 is a circuit diagram showing a specific configuration of a bit line control circuit according to a fourth embodiment.

FIG. 7 is a timing chart showing a read operation according to the fourth embodiment.

FIG. 8 is a timing chart showing a write operation according to the fourth embodiment.

FIG. 9 is a timing chart showing a verify read operation according to the fourth embodiment.

FIG. 10 is a diagram illustrating an outline of a write operation according to fourth and fifth embodiments.

FIG. 11 is a circuit diagram showing a specific configuration of a bit line control circuit according to a fifth embodiment.

FIG. 12 is a timing chart showing a read operation according to the fifth embodiment.

FIG. 13 is a timing chart showing a write operation according to the fifth embodiment.

FIG. 14 is a timing chart showing a verify read operation according to the fifth embodiment.

FIG. 15 is a circuit diagram showing a configuration of a bit line control circuit according to a fourth embodiment.

FIG. 16 is a circuit diagram showing a configuration of a bit line control circuit according to a fifth embodiment.

FIG. 17 is a circuit diagram showing a specific configuration of a bit line control circuit according to the sixth embodiment.

FIG. 18 is a circuit diagram showing a specific configuration of a bit line control circuit according to a sixth embodiment.

FIG. 19 is a diagram for explaining an outline of a conventional write operation.

FIG. 20 is a diagram for explaining an outline of a conventional write operation.

FIG. 21 is a multi-value storage type EEPR according to an eighth embodiment.
FIG. 2 is a block diagram illustrating a configuration of an OM.

22 is a circuit diagram showing a configuration of a memory cell array and a data circuit of FIG.

FIG. 23 is a diagram showing a threshold distribution of memory cells in the case of storing four values.

FIG. 24 is a block diagram showing a specific configuration of a data circuit.

FIG. 25 is a diagram for explaining the outline of the reading procedure.

FIG. 26 is a circuit diagram showing a specific example of a data circuit.

FIG. 27 is a timing chart for explaining a reading method according to the eighth embodiment.

FIG. 28 is a timing chart for explaining a write operation in the eighth embodiment.

FIG. 29 is a timing chart for explaining a write verify operation according to the eighth embodiment.

FIG. 30 is a timing chart for explaining a write verify operation according to the eighth embodiment.

FIG. 31 is a circuit diagram showing a specific example of a data circuit according to the ninth embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Memory cell array 2 ... Bit line control circuit 3 ... Column decoder 4 ... "1" Data write end detection circuit and data write end detection circuit 5 ... Input / output data conversion circuit 6 ... Data input / output buffer 7 ... Word line drive circuit 8 ... Row decoder 10 ... Memory cell array 20 ... Control gate / select gate drive circuit 30 ... Data circuit 40 ... Data input / output buffer 50 ... Address buffer 60 ... Data control circuit M ... Memory cell S ... Select transistor SG ... Select gate CG ... control gate BL ... bit line Qn ... n-channel MOS transistor Qp ... p-channel MOS transistor Qd ... depletion type n-channel MOS transistor FF ... flip-flop I ... inverter G ... NAND logic circuit

Claims (14)

[Claims] 1. A memory cell array in which electrically rewritable memory cells are arranged in a matrix, and one memory cell has a plurality of storage states of 3 or more, and arbitrary data "i" (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing data, a write verify means for confirming the write state of the plurality of memory cells, and a memory cell to which the data “i” is to be written are the data “i”.
Non-volatile semiconductor memory device comprising: an i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached. 2. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of 3 or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing, a write verify unit for confirming a write state of the plurality of memory cells, and a memory cell for which writing is insufficient based on the contents of the data circuit and the write state of the memory cells. The means for updating the contents of the data circuit and the memory cell to which the data “i” is to be written so that the data “i” is rewritten only
Non-volatile semiconductor memory device comprising: an i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached. 3. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of 3 or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing data, a write verify means for confirming the write state of the plurality of memory cells, and a memory cell to which the data “i” is to be written are the data “i”.
And an i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached, and a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cell, The memory cells to which the data “i” is to be written reach the storage state of the data “i” in the operation of electrically writing the data by continuously performing the plurality of memory cells until the predetermined write state is achieved. Then, when the i-th data batch verify circuit collectively detects, the write verify operation for the data “i” is performed in the subsequent write verify operation (i-th verify read).
Non-volatile semiconductor memory device characterized by not performing. 4. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of 3 or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing, a write verify unit for confirming a write state of the plurality of memory cells, and a memory cell for which writing is insufficient based on the contents of the data circuit and the write state of the memory cells. The means for updating the contents of the data circuit and the memory cell to which the data “i” is to be written so that the data “i” is rewritten only
The i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached, and a write verify operation for confirming the write state of the memory cell and a write operation based on the contents of the data circuit. By continuously updating the contents until the plurality of memory cells reach a predetermined write state,
In the operation of electrically writing data, the memory cell to which the data “i” is to be written is the data “i”.
When the i-th data batch verify circuit collectively detects that the memory state has been reached, the write verify operation for the data “i” (i-th
Verify read) of the non-volatile semiconductor memory device. 5. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of three or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a nonvolatile semiconductor memory device in which multivalued storage is performed and a storage state corresponding to data "0" is an erased state. A plurality of data circuits for temporarily storing data for controlling the write operation state of a plurality of memory cells in the memory cell, a write verifying means for confirming the write state of the plurality of memory cells, and writing data "i". The memory cell to be written is the data "i"
And an i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached, and a write operation based on the contents of the data circuit and a write verify operation for confirming the write state of the memory cell, In the operation of electrically writing data by continuously performing the plurality of memory cells until a predetermined write state is reached, in the first write verify operation, data “i” (i =
1, 2, ..., n-1), i-th verify read for confirming whether or not the memory cell to be written has reached the storage state of the data "i" from i = 1 to i = n-1 After that, when the first data batch verify circuit batch-detects that the memory cell to which the data “1” is to be written has reached the storage state of the data “1”, the data “i” is subsequently written in the write-verify operation. (I = 2, 3, ~, n
-1) is the memory cell to which the data "i" is written
The i-th verify read is performed from i = 2 to i = n−1 to confirm whether or not the storage state of “2” is stored in the memory cell in which the data “2” is to be written. When the second data batch verify circuit collectively detects that the state has been reached, the data "i" (i = 3, 4, ..., N) in the subsequent write verify operation.
-1) is the memory cell to which the data "i" is written
The i-th verify read for confirming whether or not the memory state has been reached is performed from i = 3 to i = n−1, and finally the data “i” (i = 1 to n−2) should be written. When the i-th (i = 1 to n−2) data batch verify circuit collectively detects that the memory cell has reached the storage state of data “i”, the data “n−1” is detected in the subsequent write verify operation. The memory cell to be written is
A nonvolatile semiconductor memory device characterized by performing an (n-1) th verify read for confirming whether or not a storage state of data "n-1" has been reached. 6. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of 3 or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a nonvolatile semiconductor memory device in which multivalued storage is performed and a storage state corresponding to data "0" is an erased state. A plurality of data circuits for temporarily storing data for controlling a write operation state of a plurality of memory cells in the memory, write verify means for confirming a write state of the plurality of memory cells, and contents of the data circuit. A means for updating the contents of the data circuit and data "i" should be written so as to rewrite only the memory cell in which the writing is insufficient from the writing state of the memory cell. Memory cell is data "i"
Data batch verify circuit for collectively detecting whether or not the memory state has been reached, a write operation based on the contents of the data circuit, a write verify operation for confirming the write state of the memory cell, and the data. In the operation of electrically writing data by continuously updating the contents of the circuit until the plurality of memory cells reach a predetermined write state, the data “i” (i =
1, 2, ..., n-1), i-th verify read for confirming whether or not the memory cell to be written has reached the storage state of the data "i" from i = 1 to i = n-1 After that, when the first data batch verify circuit batch-detects that the memory cell to which the data “1” is to be written has reached the storage state of the data “1”, the data “i” is subsequently written in the write-verify operation. (I = 2, 3, ~, n
-1) is the memory cell to which the data "i" is written
The i-th verify read is performed from i = 2 to i = n−1 to confirm whether or not the storage state of “2” is stored in the memory cell in which the data “2” is to be written. When the second data batch verify circuit collectively detects that the state has been reached, the data "i" (i = 3, 4, ..., N) in the subsequent write verify operation.
-1) is the memory cell to which the data "i" is written
The i-th verify read for confirming whether or not the memory state has been reached is performed from i = 3 to i = n−1, and finally the data “i” (i = 1 to n−2) should be written. When the i-th (i = 1 to n−2) data batch verify circuit collectively detects that the memory cell has reached the storage state of data “i”, the data “n−1” is detected in the subsequent write verify operation. The memory cell to be written is
A nonvolatile semiconductor memory device characterized by performing an (n-1) th verify read for confirming whether or not a storage state of data "n-1" has been reached. 7. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of 3 or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing data, a write verify means for confirming the write state of the plurality of memory cells, and a memory cell to which the data “i” is to be written are the data “i”.
The i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached, the write verify operation for confirming the write state of the memory cell is performed by the plurality of write operations based on the contents of the data circuit. By continuously performing the operation until the memory cell of No. 1 is in the predetermined write state, in the operation of electrically writing data, if there is no memory cell to be written with the data “i” among the memory cells to be written,
The non-volatile semiconductor memory device is characterized in that the write verify operation (i-th verify read) for the data "i" is not performed in the write verify operation when the data batch verify circuit of (1) collectively detects. 8. A memory cell array in which electrically rewritable memory cells are arranged in a matrix is provided, and one memory cell is provided with a plurality of storage states of three or more, and arbitrary data "i" is provided. (I = 0, 1, ..., N-1; n is 3 or more) is a non-volatile semiconductor memory device, which stores data for controlling a write operation state of a plurality of memory cells in the memory cell array. A plurality of data circuits for temporarily storing, a write verify unit for confirming a write state of the plurality of memory cells, and a memory cell for which writing is insufficient based on the contents of the data circuit and the write state of the memory cells. The means for updating the contents of the data circuit and the memory cell to which the data “i” is to be written so that the data “i” is rewritten only
The i-th data batch verify circuit for collectively detecting whether or not the memory state has been reached, and a write verify operation for confirming the write state of the memory cell and a write operation based on the contents of the data circuit. By continuously updating the contents until the plurality of memory cells reach a predetermined write state,
In the operation of electrically writing data, when the i-th data batch verify circuit collectively detects that there is no memory cell to be written with the data “i” in the memory cell to be written, the data “i” is written in the write verify operation. A nonvolatile semiconductor memory device characterized in that a write verify operation (i-th verify read) for i ″ is not performed. 9. The data batch verify circuit comprises a data batch detection MOS transistor unit connected to the data circuit, and these data batch detection MOS transistor units are connected in parallel. The non-volatile semiconductor memory device according to claim 1. 10. The data circuit includes a flip-flop circuit, and the data batch detection MOS transistor unit has a plurality of data batch detection MOS transistors each gate of which is connected to one end of the corresponding flip-flop circuit.
MO including a transistor and for batch detection of these data
10. The non-volatile semiconductor memory device according to claim 9, wherein S transistors are connected in series. 11. The memory cell is configured by stacking a charge storage layer and a control gate on a semiconductor layer, and a plurality of memory cells are connected in series to form a NAND cell structure. 9. The nonvolatile semiconductor memory device according to any one of 1 to 8. 12. The memory cell according to claim 1, wherein the memory cell is formed by stacking a charge storage layer and a control gate on a semiconductor layer to form a NOR cell structure. The nonvolatile semiconductor memory device described. 13. The data latch circuit comprises:
The m-th (m is a natural number satisfying 2 ^(m-1) <n ≤ 2 ^m ) pieces are arranged. 14. A memory cell array in which electrically rewritable memory cells are arranged in a matrix.
One memory cell has three or more memory states,
Arbitrary data "i" (i = 0, 1, ~, n-1; n is 3
The above is a non-volatile semiconductor memory device for multi-valued storage, and first, second and second data temporarily store data for controlling a write operation state of a plurality of memory cells in the memory cell array.
..., the m-th (m is a natural number satisfying 2 ^(m-1) <n≤2 ^m ) data latch circuit, write verify means for confirming the write state of the plurality of memory cells, and data "i". A non-volatile semiconductor memory device comprising: an i-th data batch verify circuit for collectively detecting whether or not the memory cells to be written with have reached a storage state of data "i".