JPH09191249A - Frequency deviation correction system - Google Patents
Frequency deviation correction systemInfo
- Publication number
- JPH09191249A JPH09191249A JP8002534A JP253496A JPH09191249A JP H09191249 A JPH09191249 A JP H09191249A JP 8002534 A JP8002534 A JP 8002534A JP 253496 A JP253496 A JP 253496A JP H09191249 A JPH09191249 A JP H09191249A
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency deviation
- deviation
- clock
- master clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
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- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ディジタル回路を
動作させるクロックの発振源の周波数偏差の補正方式に
関する。近年、移動体通信の普及が進み、移動局の電源
電池の使用時間をより長くする為に、回路の低消費電力
化が望まれている。このため、移動局に電力を供給する
容量の高い電池の提案や、移動局のディジタル回路を動
作させるマスタクロックの間欠使用の提案などがある
が、マスタクロック信号源の周波数を低周波数化する事
が、移動局の消費電力の低減に最も効果がある。一般に
低周波数のクロック発振源の周波数安定度は低く悪いの
で、この低周波数のクロック発振源の周波数安定度を高
く良くする必要がある。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of correcting a frequency deviation of a clock oscillation source for operating a digital circuit. In recent years, with the spread of mobile communication, it is desired to reduce the power consumption of a circuit in order to prolong the usage time of a power supply battery of a mobile station. Therefore, there are proposals such as a battery with a high capacity for supplying power to the mobile station and an intermittent use of the master clock for operating the digital circuit of the mobile station.However, it is necessary to lower the frequency of the master clock signal source. However, it is most effective in reducing the power consumption of the mobile station. Generally, the frequency stability of the low-frequency clock oscillation source is low and poor, and therefore the frequency stability of the low-frequency clock oscillation source needs to be high and good.
【０００２】[0002]
【従来の技術】ディジタル回路を動作させる従来のマス
タクロックの生成回路は、図５に示す如く、生成するマ
スタクロックの周波数f より高い周波数nfの高安定なク
ロック信号発振源の出力を、周波数逓分して周波数f の
マスタクロックを得ていた。2. Description of the Related Art As shown in FIG. 5, a conventional master clock generation circuit for operating a digital circuit outputs the output of a highly stable clock signal oscillation source having a frequency nf higher than the frequency f of the master clock to be frequency-multiplied. The master clock of frequency f was obtained by dividing.
【０００３】伝送データのフレーム同期を取る時などの
様に、ディジタル通信においては、クロック発振源とし
て高い周波数安定度が要求される。ところが、ディジタ
ル回路の低消費電力化のために、クロック発振源の周波
数を低くしようとすると、其のクロック発振源の周波数
安定度も低くなってしまう。In digital communication such as when frame synchronization of transmission data is taken, high frequency stability is required as a clock oscillation source. However, if the frequency of the clock oscillation source is reduced in order to reduce the power consumption of the digital circuit, the frequency stability of the clock oscillation source also becomes low.
【０００４】[0004]
【発明が解決しようとする課題】従って、ディジタル回
路の低消費電力化の為のクロック発振源の低周波数化が
出来ず、ディジタル移動体通信では其の移動局の、より
一層の低消費電力化を図られないという問題を生じてい
た。本発明の課題は、一般に周波数安定度の低い低周波
数のクロック信号発振源でも、周波数安定度の高いクロ
ック信号とすることにある。Therefore, the frequency of the clock oscillation source cannot be lowered to reduce the power consumption of the digital circuit, and the power consumption of the mobile station is further reduced in the digital mobile communication. There was a problem that could not be achieved. An object of the present invention is to make a clock signal oscillation source having a high frequency stability even a low-frequency clock signal oscillation source having a low frequency stability in general.
【０００５】[0005]
【課題を解決するための手段】この課題を解決するため
の本発明の基本構成は、図１の原理的な構成図に示され
る。そして図２は其の各部の動作のタイムチャートを示
す。図１の構成図にて(1)はマスタクロックとして使用
される電圧制御発振器VCO 型のクロック発振部であり、
希望の発振周波数f0に対して偏差±Δf 有する周波数f0
±Δf の信号を発振するもの。(2) は周波数計測部であ
り、マスタクロック発振部(1) が生成したマスタクロッ
クa の周波数f0±Δf を計測するもの。(3) は計測制御
部であり、周波数計測部(2) の計測動作を任意の一定時
間t だけ行わせるゲート信号b を生成するもの。(4) は
周波数偏差検出部であり、マスタクロックの周波数の計
測値c を基にし周波数偏差d である±Δf を検出するも
の。(5) は補正値テーブルであり、周波数偏差±Δf を
±０にする補正値e を予め書き込み記憶するもの。(6)
は発振周波数制御部であり、前記周波数偏差±Δf を±
０にする補正値e を周波数制御信号f に変換し、マスタ
クロック発振部(1) が生成したマスタクロックの周波数
f0±Δf の偏差±Δf を０に近づけるように制御するも
のである。The basic configuration of the present invention for solving this problem is shown in the principle configuration diagram of FIG. 2 shows a time chart of the operation of each part thereof. In the configuration diagram of FIG. 1, (1) is a voltage controlled oscillator VCO type clock oscillator used as a master clock,
Frequency f 0 with deviation ± Δf from desired oscillation frequency f 0
A device that oscillates a signal of ± Δf. (2) is a frequency measuring unit that measures the frequency f 0 ± Δf of the master clock a generated by the master clock oscillator (1). (3) is a measurement control unit that generates a gate signal b that causes the frequency measurement unit (2) to perform the measurement operation for an arbitrary fixed time t. (4) is a frequency deviation detection unit that detects ± Δf which is the frequency deviation d based on the measured value c of the frequency of the master clock. (5) is a correction value table in which the correction value e for making the frequency deviation ± Δf ± 0 is written and stored in advance. (6)
Is an oscillation frequency control unit, and the frequency deviation ± Δf is ±
The master clock frequency generated by the master clock oscillator (1) by converting the correction value e to 0 into the frequency control signal f
The deviation ± Δf of f 0 ± Δf is controlled so as to approach 0.
【０００６】本発明では、図２の動作のタイムチャート
に示す如く、 (a)マスタクロックの周波数f0±Δf を
(2)周波数計測部が計測する為に、(3) 計測制御部が時
間ｔ秒の間だけアクティブにする（b)ゲート信号を生成
する。其の周波数計測の終了は前記（b)ゲート信号によ
って制御され、最新の (c)計測値が得られる。この最新
の計測値を基に (4)周波数偏差検出部が検出した周波数
偏差±Δf が０となるｔ秒間に計測した計測結果と前記
最新の (c)計測値との減算処理により、(d) 周波数偏差
である±Δf を検出する。検出される周波数偏差（±Δ
f)の最大値は (1)マスタクロック発振部の周波数f0±Δ
f の安定度±Δf で決定される。いま、最新の (d)周波
数偏差として±Δf2が得られたとすると、(5) 補正値テ
ーブルから周波数偏差±Δf2を０とする情報である (e)
補正値が出力され、(6)発振周波数制御部で (f)周波数
制御信号に変換され、±Δf2が０となる様に (1)マスタ
クロック発振部の発振周波数を制御する。この動作を繰
り返す事で (1)マスタクロック発振部の周波数偏差±Δ
f が小さくなり周波数安定度が高まることになる。In the present invention, as shown in the time chart of the operation of FIG. 2, (a) the frequency f 0 ± Δf of the master clock is
(2) In order for the frequency measurement unit to measure, (3) the measurement control unit activates only for time t seconds, and (b) generates a gate signal. The end of the frequency measurement is controlled by the (b) gate signal, and the latest (c) measured value is obtained. Based on this latest measurement value, (d) by the subtraction processing of the measurement result measured for t seconds when the frequency deviation ± Δf detected by the frequency deviation detection unit becomes 0 and the latest (c) measurement value, (d ) Detect the frequency deviation ± Δf. Frequency deviation detected (± Δ
The maximum value of f) is (1) Master clock oscillator frequency f 0 ± Δ
Determined by the stability of f ± Δf. Now, assuming that the latest (d) frequency deviation ± Δf 2 is obtained, (5) the frequency deviation ± Δf 2 is set to 0 from the correction value table (e)
The correction value is output and converted into (f) the frequency control signal in (6) the oscillation frequency control unit, and (1) the oscillation frequency of the master clock oscillation unit is controlled so that ± Δf 2 becomes 0. By repeating this operation, (1) Frequency deviation of master clock oscillator ± Δ
f becomes small and frequency stability increases.
【０００７】[0007]
【発明の実施の形態】図３は本発明の実施例のクロック
発振源の周波数偏差補正方式の回路構成図であり、発振
周波数f0±Δf のマスタクロック発振部の周波数偏差±
Δf を０にする周波数偏差補正方式の回路構成を示して
いる。図３中、図１に示したものと同一のものは、同一
の記号，番号で示してある。(1) はマスタクロック発振
部であり、例えば水晶振動子(1)-と可変容量ダイオー
ド(1)-をもつ信号発振器として構成され、中心周波数
f0の (a)マスタクロックを発振するが、温度変化, 経年
変化, 電圧や負荷の変動などにより、周波数偏差±Δf
を有するもの。(2) は周波数計測部であり、ｎビットの
カウンタで構成され、(4) 周波数偏差検出部を兼ねて、
ｎビットの計測値f0と周波数偏差±Δf とを出力するも
の。(3) は計測制御部であり、外部要因又は自発的要因
による周期的な起動トリガ(3)-により前記 (2)周波数
計測部に対する被計測クロックの供給を、計測タイマ
(3)-による任意の一定時間t だけゲート信号(3)-(b)
を一方の入力とする ANDゲート(3)-により制御するも
の。(5) は補正値テーブルであり、例えばＲＯＭで構成
され、その最大容量は、ｎビットカウンタの使用時に２
n の容量を有するもの。(6) は発振周波数制御部であ
り、補正値テーブル(5) から読み出した最大ｎビットの
ディジタルの補正値データをアナログの電圧に変換する
D／A 変換器であって、其の変換したアナログの電圧
を、電圧制御発振器 VCO型のマスタクロック発振部(1)
の可変容量ダイオード(1)-に印加し、該マスタクロッ
ク発振部(1) の発振周波数f0±Δf の周波数偏差±Δf
を±０とするものである。FIG. 3 is a circuit configuration diagram of a frequency deviation correction system for a clock oscillation source according to an embodiment of the present invention. Frequency deviation ± of a master clock oscillator with an oscillation frequency f 0 ± Δf
The circuit configuration of the frequency deviation correction method for setting Δf to 0 is shown. In FIG. 3, the same components as those shown in FIG. 1 are designated by the same symbols and numbers. (1) is a master clock oscillator, which is configured as a signal oscillator with a crystal oscillator (1) -and a variable capacitance diode (1)-
f 0 (a) Master clock oscillates, but frequency deviation ± Δf due to temperature changes, aging changes, voltage and load changes, etc.
With. (2) is a frequency measurement unit, which is composed of an n-bit counter, and (4) also functions as a frequency deviation detection unit.
Outputs n-bit measurement value f 0 and frequency deviation ± Δf. (3) is a measurement control unit, which supplies a measured clock to the frequency measurement unit by (3) -the periodic start trigger by an external factor or a spontaneous factor.
Gate signal (3)-(b) for an arbitrary fixed time t by (3)-
One of which is controlled by AND gate (3)-. (5) is a correction value table, which is composed of, for example, a ROM, and its maximum capacity is 2 when the n-bit counter is used.
Those with a capacity of n . (6) is an oscillation frequency control unit, which converts the maximum n-bit digital correction value data read from the correction value table (5) into an analog voltage.
D / A converter that converts the converted analog voltage into a voltage controlled oscillator VCO type master clock oscillator (1)
Applied to the variable capacitance diode (1)-of the master clock oscillator (1) and the frequency deviation of the oscillation frequency f 0 ± Δf ± Δf
Is ± 0.
【０００８】通常の動作は、(3)-の起動トリガによっ
て、(3)-の計測タイマが任意に定めた一定時間t だけ
作動を開始する。この時、ゲート信号(3)-(b) を一方の
入力とする ANDゲート(3)-により、周波数f0±Δf の
(a)マスタクロックが (2)周波数計測部のｎビットカウ
ンタへ供給され、(b) ゲート信号がアクティブな間だ
け、ｎビットカウンタは計数を行う。(b) ゲート信号が
(3)-計測タイマのタイムアウトにより、ノンアクティ
ブとなり、ｎビットカウンタの計数動作は終了し、ｎビ
ットの計数値を出力して停止する。図４のマスタクロッ
クの周波数の計測値と周波数偏差の補正値との関係を示
す図の中の (A)ｎビットカウンタの出力値（計測値) に
示す様に、周波数偏差±Δf ＝±０の時、ｎビットカウ
ンタの出力値が 2n-1 となる様に、該カウンタの開始値
をプリセットすることは容易であり、カウント値 2n-1
を中心周波数f0の値と定める。このｎビットの計数値出
力は、メモリ(5) のアドレスに直接接続され、該メモリ
(5) より出力されるデータをD／A 変換器(6)でアナログ
の電圧に変換し、マスタクロック発振部(1) の可変容量
ダイオード(1)-に印加し、マスタクロック発振部(1)
の発振周波数f0±Δf の周波数偏差±Δf を±０にす
る。いま、図４の(A) に示す様に、ｎビットカウンタの
出力値（計測値) が f(c) であったとする。f(c)は計測
結果であり、中心周波数f0に対して +Ｃppm に相当する
周波数偏差を持っている。この計測結果（ｎビット）が
メモリ(5) のアドレスとなって、 +Ｃppm →０に制御す
る補正用データが出力される。そして (6)発振周波数制
御部を通して (1)マスタクロック発振部の発振周波数f0
＋f(c)が、其の中心周波数f0になる様に制御される。In the normal operation, the activation trigger of (3) -starts the operation of the measurement timer of (3) -for a predetermined time t. At this time, the AND gate (3)-with the gate signal (3)-(b) as one input causes the frequency f 0 ± Δf
(a) The master clock is supplied to (2) the n-bit counter of the frequency measurement unit, and (b) the n-bit counter counts only while the gate signal is active. (b) The gate signal is
(3) -When the measurement timer times out, it becomes non-active, the counting operation of the n-bit counter ends, the n-bit count value is output, and it stops. As shown in (A) n-bit counter output value (measurement value) in the diagram showing the relationship between the master clock frequency measurement value and the frequency deviation correction value in Fig. 4, the frequency deviation ± Δf = ± 0 when, as the output value of the n-bit counter is 2 n-1, it is easy to preset a starting value of the counter, the count value 2 n-1
Is defined as the value of the center frequency f 0 . This n-bit count value output is directly connected to the address of the memory (5),
The data output from (5) is converted into an analog voltage by the D / A converter (6) and applied to the variable-capacitance diode (1)-of the master clock oscillator (1). )
The frequency deviation ± Δf of the oscillation frequency f 0 ± Δf of is set to ± 0. Now, assume that the output value (measured value) of the n-bit counter is f (c), as shown in FIG. f (c) is a measurement result, and has a frequency deviation corresponding to + C ppm with respect to the center frequency f 0 . This measurement result (n bits) becomes the address of the memory (5), and the correction data for controlling + C ppm → 0 is output. And (6) Through the oscillation frequency control unit (1) Oscillation frequency f 0 of the master clock oscillation unit
+ F (c) is controlled so as to have its center frequency f 0 .
【０００９】[0009]
【発明の効果】以上説明した如く、本発明によれば、ク
ロック発振源の周波数偏差が自動的に補正されるので、
低周波数のクロック発振源の周波数偏差でも、自動的に
補正されて低周波数のクロック発振源の周波数の高安定
度化が実現出来て、ディジタル装置の低消費電力化に大
きく寄与する効果が得られる。As described above, according to the present invention, the frequency deviation of the clock oscillation source is automatically corrected.
Even if the frequency deviation of the low-frequency clock oscillation source is corrected, the frequency stability of the low-frequency clock oscillation source can be improved, and the effect of greatly reducing the power consumption of the digital device can be obtained. .
【図１】 本発明の周波数偏差補正方式の原理的な構成
図FIG. 1 is a principle configuration diagram of a frequency deviation correction method of the present invention.
【図２】 本発明の周波数偏差補正方式の動作のタイム
チャートFIG. 2 is a time chart of the operation of the frequency deviation correction method of the present invention.
【図３】 本発明の実施例のマスタクロック発振源の周
波数偏差補正方式の回路構成図FIG. 3 is a circuit configuration diagram of a frequency deviation correction method for a master clock oscillation source according to an embodiment of the present invention.
【図４】 本発明の実施例のマスタクロックの周波数の
計測値と其の周波数偏差の補正値との関係を示す図FIG. 4 is a diagram showing the relationship between the measured value of the frequency of the master clock and the correction value of the frequency deviation thereof according to the embodiment of the present invention.
【図５】 従来のマスタクロックの生成回路の構成図FIG. 5 is a block diagram of a conventional master clock generation circuit.
(1) はマスタクロック発振部、(2) は周波数計測部、
(3) は計測制御部、(4)は周波数偏差検出部、(5) は補
正値テーブル、(6) は発振周波数制御部である。(1) is the master clock oscillator, (2) is the frequency measurement unit,
(3) is a measurement control unit, (4) is a frequency deviation detection unit, (5) is a correction value table, and (6) is an oscillation frequency control unit.
Claims (2)
発振するクロック発振部と、其の発振周波数を計測する
周波数計測部と、其の計測時間を任意に設定する計測制
御部と、其の周波数の計測値より所望周波数からの偏差
を検出する周波数偏差検出部と、其の検出された周波数
偏差を零にする補正値を予め記憶する補正値テーブル
と、其のテーブル出力の周波数偏差の補正値を前記クロ
ック信号発振部の発振周波数を制御し其の周波数偏差を
零にする制御信号に変換する発振周波数制御部とを具え
たことを特徴とする周波数偏差補正方式。1. A clock oscillating unit that oscillates a clock signal of a certain frequency having a deviation, a frequency measuring unit that measures the oscillating frequency, a measurement control unit that arbitrarily sets the measuring time, and A frequency deviation detection unit that detects a deviation from the desired frequency based on the measured frequency value, a correction value table that stores in advance a correction value that makes the detected frequency deviation zero, and a correction of the frequency deviation of the table output. An oscillation frequency control unit for converting a value into a control signal for controlling the oscillation frequency of the clock signal oscillation unit to make the frequency deviation zero.
・低２種類のクロック発振部とし、其の２種類のクロッ
クで動作する装置の短時間の通常時には高い周波数のク
ロック発振部の出力で動作させ、長時間の装置の待機時
には低い周波数のクロック発振部の出力で動作させるこ
とで該装置の低消費電力化を意図する場合でも、常にク
ロックの周波数安定度を良くすることを特徴とする請求
項１記載の周波数偏差補正方式。2. The clock oscillating unit is a clock oscillating unit having two types of high and low oscillating frequencies, and the output of the clock oscillating unit having a high frequency is normally used for a short period of time in a device operating with the two types of clocks. It is characterized in that the frequency stability of the clock is always improved by operating it and operating it with the output of the clock oscillating unit having a low frequency when the apparatus is on standby for a long time, even when it is intended to reduce the power consumption of the apparatus. The frequency deviation correction method according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8002534A JPH09191249A (en) | 1996-01-10 | 1996-01-10 | Frequency deviation correction system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8002534A JPH09191249A (en) | 1996-01-10 | 1996-01-10 | Frequency deviation correction system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09191249A true JPH09191249A (en) | 1997-07-22 |
Family
ID=11532055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8002534A Withdrawn JPH09191249A (en) | 1996-01-10 | 1996-01-10 | Frequency deviation correction system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09191249A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948134A2 (en) * | 1998-04-01 | 1999-10-06 | Sony Corporation | Radio receiver |
| WO2012147156A1 (en) * | 2011-04-26 | 2012-11-01 | 測位衛星技術株式会社 | Navigation signal transmitter and navigation signal generating method |
| JP2015139218A (en) * | 2014-01-20 | 2015-07-30 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Digital phase fixed loop, control method thereof, and ultra low power transceiver using the same |
-
1996
- 1996-01-10 JP JP8002534A patent/JPH09191249A/en not_active Withdrawn
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0948134A2 (en) * | 1998-04-01 | 1999-10-06 | Sony Corporation | Radio receiver |
| EP0948134A3 (en) * | 1998-04-01 | 2003-09-17 | Sony Corporation | Radio receiver |
| WO2012147156A1 (en) * | 2011-04-26 | 2012-11-01 | 測位衛星技術株式会社 | Navigation signal transmitter and navigation signal generating method |
| CN103620443A (en) * | 2011-04-26 | 2014-03-05 | 测位卫星技术株式会社 | Navigation signal transmitter and navigation signal generating method |
| JP5798620B2 (en) * | 2011-04-26 | 2015-10-21 | 測位衛星技術株式会社 | Navigation signal transmitter and navigation signal generation method |
| US9590802B2 (en) | 2011-04-26 | 2017-03-07 | Gnss Technologies Inc. | Navigation signal transmitter and method for generating navigation signal |
| JP2015139218A (en) * | 2014-01-20 | 2015-07-30 | 三星電子株式会社Ｓａｍｓｕｎｇ Ｅｌｅｃｔｒｏｎｉｃｓ Ｃｏ．，Ｌｔｄ． | Digital phase fixed loop, control method thereof, and ultra low power transceiver using the same |
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| A300 | Withdrawal of application because of no request for examination |
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