CN112953514A - Method and device for calibrating Bluetooth clock - Google Patents

Method and device for calibrating Bluetooth clock Download PDF

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CN112953514A
CN112953514A CN202110257281.9A CN202110257281A CN112953514A CN 112953514 A CN112953514 A CN 112953514A CN 202110257281 A CN202110257281 A CN 202110257281A CN 112953514 A CN112953514 A CN 112953514A
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count
frequency
clock
counter
bluetooth chip
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CN112953514B (en
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彭国杰
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Actions Technology Co Ltd
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Actions Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The present disclosure relates to a method and apparatus for calibrating a bluetooth clock, the method comprising: under the condition that the Bluetooth chip is detected to enter a sleep state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting; under the condition that the Bluetooth chip is detected to exit from the sleep state, acquiring the current count of the working clock counter, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the sleep state; the current count is the count of the clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.

Description

Method and device for calibrating Bluetooth clock
Technical Field
The present disclosure relates to the field of bluetooth technology, and in particular, to a method and an apparatus for calibrating a bluetooth clock.
Background
At present, more and more devices are added with a Bluetooth function to realize connection and interaction with mobile phone application programs, and a great number of devices in the devices are powered by batteries, so that the requirements on low power consumption are high. In the bluetooth specification, a low-frequency clock is mainly used for timing in a low-power sleep mode, and the stability of bluetooth connection can be guaranteed only by accurately waking up the clock at a specific time, so that the requirement on precision is high and the precision is required to reach 250 ppm.
In the related art, integer frequency division can be performed on a low-frequency crystal oscillator to obtain a clock meeting the Bluetooth clock precision (3.2kHZ) as an operating clock of a Bluetooth chip, however, the frequency of the low-frequency crystal oscillator used in this way needs to be an integer multiple of 3.2kHZ, and when the frequency of the low-frequency crystal oscillator is not an integer multiple of 3.2kHZ, fractional frequency division needs to be performed on the low-frequency crystal oscillator to obtain the operating clock of the Bluetooth chip, but errors can be introduced by the fractional frequency division, so that the precision of the Bluetooth clock is reduced.
Disclosure of Invention
In order to solve the above problems, the present disclosure provides a method and apparatus for calibrating a bluetooth clock.
In a first aspect, the present disclosure provides a method of calibrating a bluetooth clock, the method comprising: under the condition that a Bluetooth chip is detected to enter a sleep state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit; under the condition that the Bluetooth chip is detected to exit from the sleep state, acquiring the current count of the working clock counter, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the sleep state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
Optionally, when it is detected that the bluetooth chip enters the sleep state, the controlling, according to the clock cycle, a working clock counter of the bluetooth chip to count by dividing a clock signal includes: and controlling a working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit the sleep state.
Optionally, the controlling the working clock counter of the bluetooth chip to count by the frequency-divided clock signal includes: circularly executing a first counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency division circuit and the clock period of the preset low-frequency clock signal; when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; and when the sum value is smaller than the working clock period, taking the sum value as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a wake-up cumulative time difference, where the wake-up cumulative time difference is a cumulative time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the determining, according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits the sleep state, the error duration of the bluetooth chip in the sleep state includes: and determining the error duration of the Bluetooth chip in the dormant state according to the awakening accumulated time difference and the preset timing precision corresponding to the high-frequency clock counter.
Optionally, the updating the current counts of the working clock counter and the high frequency clock counter according to the error duration includes: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the first sum is determined to be greater than or equal to a preset count threshold; updating the current count of the high frequency clock counter to a difference value of the first sum and the preset count threshold in a case where it is determined that the first sum is greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum in a case where it is determined that the first sum is less than the preset count threshold.
Optionally, the controlling the working clock counter of the bluetooth chip to count by the frequency-divided clock signal includes: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; determining a first frequency division number corresponding to a first integer frequency division and a second frequency division number corresponding to a second integer frequency division which form the frequency division clock signal according to the frequency division coefficient; determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the determining the count of the working clock counter according to the count of the division coefficient counter, the phase coefficient, and the count threshold comprises: circularly executing a second counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is determined to be increased by 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge; and under the condition that the counting of the working clock counter is determined not to be added by 1, adding 1 to the counting of the frequency division coefficient counter, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits from the sleep state, the current phase coefficient is a phase coefficient when the bluetooth chip exits from the sleep state, and the error duration includes a first error duration and a second error duration; the determining, according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits the sleep state, the error duration of the bluetooth chip in the sleep state includes: determining the first error duration according to the current frequency division count; and determining the second error time length according to the current phase coefficient.
Optionally, the updating the current counts of the working clock counter and the high frequency clock counter according to the error duration includes: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the second sum is determined to be greater than or equal to a preset count threshold; and updating the current count of the high-frequency clock counter to a difference value between the second sum and the preset count threshold value when the second sum is determined to be greater than or equal to the preset count threshold value, and updating the current count of the high-frequency clock counter to the second sum when the second sum is determined to be less than the preset count threshold value.
In a second aspect, the present disclosure provides an apparatus for calibrating a bluetooth clock, the apparatus comprising: the counting control module is used for acquiring a clock cycle of a preset low-frequency clock signal under the condition that the Bluetooth chip is detected to enter a sleep state, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit; the error duration determining module is used for acquiring the current count of the working clock counter under the condition that the Bluetooth chip is detected to exit the sleep state, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameters of the frequency dividing circuit when the Bluetooth chip exits the sleep state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and the updating module is used for updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
Optionally, the counting control module is specifically configured to: and controlling a working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit the sleep state.
Optionally, the counting control module is further configured to: circularly executing a first counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency division circuit and the clock period of the preset low-frequency clock signal; when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; and when the sum value is smaller than the working clock period, taking the sum value as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a wake-up cumulative time difference, where the wake-up cumulative time difference is a cumulative time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the error duration determination module is further configured to: and determining the error duration of the Bluetooth chip in the dormant state according to the awakening accumulated time difference and the preset timing precision corresponding to the high-frequency clock counter.
Optionally, the update module is specifically configured to: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the first sum is determined to be greater than or equal to a preset count threshold; updating the current count of the high frequency clock counter to a difference value of the first sum and the preset count threshold in a case where it is determined that the first sum is greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum in a case where it is determined that the first sum is less than the preset count threshold.
Optionally, the counting control module is further configured to: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; determining a first frequency division number corresponding to a first integer frequency division and a second frequency division number corresponding to a second integer frequency division which form the frequency division clock signal according to the frequency division coefficient; determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the counting control module is further configured to: circularly executing a second counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is determined to be increased by 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge; and under the condition that the counting of the working clock counter is determined not to be added by 1, adding 1 to the counting of the frequency division coefficient counter, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits from the sleep state, the current phase coefficient is a phase coefficient when the bluetooth chip exits from the sleep state, and the error duration includes a first error duration and a second error duration; the error duration determination module is further configured to: determining the first error duration according to the current frequency division count; and determining the second error time length according to the current phase coefficient.
Optionally, the update module is further configured to: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the second sum is determined to be greater than or equal to a preset count threshold; and updating the current count of the high-frequency clock counter to a difference value between the second sum and the preset count threshold value when the second sum is determined to be greater than or equal to the preset count threshold value, and updating the current count of the high-frequency clock counter to the second sum when the second sum is determined to be less than the preset count threshold value.
According to the technical scheme, under the condition that the Bluetooth chip is detected to enter the sleep state, the clock period of a preset low-frequency clock signal is obtained, the working clock counter of the Bluetooth chip is controlled to count through a frequency division clock signal according to the clock period, the high-frequency clock counter of the Bluetooth chip is controlled to stop counting, and the frequency division clock signal is the clock signal output by the preset low-frequency clock signal through a frequency division circuit; under the condition that the Bluetooth chip is detected to exit from the sleep state, acquiring the current count of the working clock counter, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the sleep state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock. That is to say, after the bluetooth chip enters the sleep state, can maintain the bluetooth clock of bluetooth chip through presetting low frequency clock signal, and the frequency of this preset low frequency clock signal can be the integral multiple of non-3.2 kHZ, to the error that the frequency division arouses, can be according to the timing parameter of frequency division circuit in bluetooth chip sleep state, revise the count of the work clock counter and the high frequency clock counter of this bluetooth chip, calibrate the bluetooth clock, like this, can guarantee the bluetooth clock precision while, maintain the normal work of bluetooth clock.
Additional features and advantages of the disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:
FIG. 1 is a flow chart illustrating a method of calibrating a Bluetooth clock in accordance with an exemplary embodiment;
FIG. 2 is a flow chart illustrating a second method of calibrating a Bluetooth clock in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram of a frequency-division circuit shown in accordance with an exemplary embodiment;
FIG. 4 is a circuit schematic of a Bluetooth clock, shown in accordance with an exemplary embodiment;
FIG. 5 is a flow chart illustrating a third method of calibrating a Bluetooth clock in accordance with one exemplary embodiment;
FIG. 6 is a flow diagram illustrating a method of obtaining a current count of a working clock counter in accordance with an exemplary embodiment;
FIG. 7 is a schematic diagram of another divider circuit shown in accordance with an exemplary embodiment;
fig. 8 is a schematic structural diagram illustrating an apparatus for calibrating a bluetooth clock according to an exemplary embodiment.
Detailed Description
The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.
In the description that follows, the terms "first," "second," and the like are used for descriptive purposes only and are not intended to indicate or imply relative importance nor order to be construed.
First, an application scenario of the present disclosure will be explained. Because the bluetooth clock specified in the bluetooth protocol is a 28-bit counter with a timing precision of 312.5us, a 28-bit counter is usually included in the design, and 1 is added every 312.5us, and in addition, because smaller timing precision is required in the bluetooth transceiving process, a fine counter is usually also included in the design, and 1 is added every 1us or 0.5 us. The requirement of the Bluetooth clock on the clock precision is less than +/-20 ppm in an active mode and less than +/-250 ppm in a sleep mode. In the sleep mode, in order to save power consumption, the high-frequency high-precision clock of the system is turned off, and the low-frequency clock is used for maintaining the normal counting of the Bluetooth clock. Since the timing accuracy of the bluetooth clock is 312.5us, a 3.2KHz clock is required to maintain the normal count of the bluetooth clock.
In the related art, an RC or a low-frequency crystal oscillator of 32kHZ may be subjected to integer frequency division to obtain a clock satisfying the accuracy of a bluetooth clock (3.2kHZ) as an operating clock of a bluetooth chip, but the frequency of the RC or the low-frequency crystal oscillator used in this manner needs to be an integer multiple of 3.2kHZ, and when the frequency of the RC or the low-frequency crystal oscillator is not an integer multiple of 3.2kHZ, the RC or the low-frequency crystal oscillator needs to be subjected to fractional frequency division to obtain the operating clock of the bluetooth chip, but the fractional frequency division may introduce an error, so that the accuracy of the bluetooth clock is low.
In order to solve the existing problems, the present disclosure provides a method and an apparatus for calibrating a bluetooth clock, after a bluetooth chip enters a sleep state, the bluetooth clock of the bluetooth chip can be maintained through a preset low frequency clock signal, the frequency of the preset low frequency clock signal can be an integer multiple of non-3.2 kHZ, for an error caused by frequency division, the count of a working clock counter and a high frequency clock counter of the bluetooth chip can be corrected according to a timing parameter of a frequency division circuit in the sleep state of the bluetooth chip, and the bluetooth clock is calibrated, so that the accuracy of the bluetooth clock can be ensured, and the normal work of the bluetooth clock can be maintained.
The present disclosure is described below with reference to specific examples.
Fig. 1 is a flowchart illustrating a method of calibrating a bluetooth clock, according to an example embodiment, as shown in fig. 1, the method including:
s101, under the condition that the Bluetooth chip is detected to enter a sleep state, acquiring a clock cycle of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting.
The period of the preset low-frequency clock signal can be pre-stored or configurable, the frequency-divided clock signal is a clock signal output by the preset low-frequency clock signal through a frequency-dividing circuit, the working clock counter can be a counter with the timing precision of 312.5us in the bluetooth chip, 1 is added to each 312.5us of the working clock counter, the high-frequency clock counter can be a counter with the timing precision of 1us or 0.5us in the bluetooth chip, 1 is added to each 1us or 0.5us of the high-frequency clock counter, and the count of the high-frequency clock counter is 0-624 when the timing precision of the high-frequency clock counter is 0.5 us; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ.
In this step, after the bluetooth chip enters the sleep state, the high frequency clock counter of the bluetooth chip may be controlled to stop counting in order to reduce the power consumption of the bluetooth chip, and the working clock counter of the bluetooth chip may count through a frequency division clock signal in order to maintain the bluetooth clock of the bluetooth chip.
It should be noted that, considering that the frequencies of the preset low-frequency clock signal may include multiple frequencies, for the preset low-frequency clock signal of the partial frequency, if the divided clock signal cannot be obtained by integer division, the divided clock signal may be obtained by fractional division. Illustratively, when the frequency of the preset low-frequency clock signal is 32.768kHZ, the frequency of the preset low-frequency clock signal is not an integral multiple of 3.2kHZ, and the preset low-frequency clock signal may output the divided clock signal by fractional division.
S102, under the condition that the Bluetooth chip is detected to exit the sleep state, the current count of the working clock counter is obtained, and the error duration of the Bluetooth chip in the sleep state is determined according to the timing parameters of the frequency dividing circuit when the Bluetooth chip exits the sleep state.
The current count is the count of the clock counter when the bluetooth chip exits from the sleep state, the frequency dividing circuit can be determined according to the frequency of the preset low-frequency clock signal, and the frequency dividing circuits corresponding to the preset low-frequency clock signals with different frequencies can be different.
In this step, when the frequency dividing circuit outputs the frequency dividing clock signal every time, the count of the working clock counter of the bluetooth chip may be increased by 1, and since the count of the working clock counter is always accumulated when the bluetooth chip is in the sleep state, the current count of the working clock counter may be obtained when the bluetooth chip exits the sleep state. For example, if the cumulative time difference between the frequency dividing circuit and the accurate target clock reaches the working clock period of the working clock counter, the count of the working clock counter is increased by 1, and if the cumulative time difference between the frequency dividing circuit and the accurate target clock does not reach the working clock period of the working clock counter when the bluetooth chip exits the sleep state, the count of the working clock counter is not increased by 1, where the cumulative time difference is the error of the bluetooth clock.
In order to avoid the error of the bluetooth clock of the bluetooth chip, the error duration of the bluetooth chip in the sleep state can be obtained according to the timing parameter of the frequency dividing circuit. For example, the accumulated time difference of the frequency dividing circuit may be taken as the error duration. It should be noted that, the error durations corresponding to different frequency division circuits are obtained in different manners, which is not limited in this disclosure.
And S103, updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration.
It should be noted that, since the high-frequency clock counter stops counting after the bluetooth chip enters the sleep state, the current count of the high-frequency clock counter may be the count of the high-frequency clock counter before the bluetooth chip enters the sleep state.
In this step, after the error duration is obtained, the current counts of the working clock counter and the high frequency clock counter may be compensated according to the error duration. For example, the error duration may be superimposed on the current counts of the operating clock counter and the high frequency clock counter.
By adopting the method, after the Bluetooth chip enters the sleep state, the Bluetooth clock of the Bluetooth chip can be maintained through the preset low-frequency clock signal, the frequency of the preset low-frequency clock signal can be an integral multiple of non-3.2 kHZ, and for errors caused by frequency division, the counting of the working clock counter and the high-frequency clock counter of the Bluetooth chip can be corrected according to the timing parameters of the frequency division circuit in the sleep state of the Bluetooth chip, so that the Bluetooth clock is calibrated, and the normal working of the Bluetooth clock can be maintained while the Bluetooth clock precision is ensured.
Fig. 2 is a flowchart illustrating a second method of calibrating a bluetooth clock, according to an example embodiment, as shown in fig. 2, the method comprising:
s201, under the condition that the Bluetooth chip is detected to enter the sleep state, acquiring a clock cycle of the preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle and a working clock cycle corresponding to the working clock counter, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting.
The frequency division clock signal is a clock signal output by a preset low-frequency clock signal through a frequency division circuit, the working clock counter can be a counter with timing precision of 312.5us in the Bluetooth chip, 1 is added to the working clock counter every 312.5us, the high-frequency clock counter can be a counter with timing precision of 1us or 0.5us in the Bluetooth chip, 1 is added to the high-frequency clock counter every 1us or 0.5us, and the count of the high-frequency clock counter is 0-624 under the condition that the timing precision of the high-frequency clock counter is 0.5 us; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ. The frequency dividing circuit can be determined according to the frequency of the preset low-frequency clock signal, and the frequency dividing circuits corresponding to the preset low-frequency clock signals with different frequencies can be different.
In this step, the first count determining step may be executed in a loop for the current rising edge of the preset low frequency clock signal until it is detected that the bluetooth chip exits from the sleep state. The first count determining step may include:
s1, acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal;
the accumulated time difference may be accumulated from the time when the bluetooth chip enters the sleep state, and illustratively, the accumulated time difference is 0 at the time when the bluetooth chip enters the sleep state. During the sleep process of the Bluetooth chip, the accumulated time difference can be stored by a time accumulation register.
S2, if the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, and taking the difference between the sum and the working clock period as the new accumulated time difference of the frequency divider circuit, and taking the next rising edge of the current rising edge as the new current rising edge;
after the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal is obtained, the sum may be compared with the working clock period, and in the case that the sum is greater than or equal to the working clock period, indicating that the timing of the frequency dividing circuit has been greater than the working clock period, the count of the working clock counter may be increased by 1.
After adding 1 to the count of the working clock counter, the difference between the sum and the working clock period may be obtained as a new accumulated time difference.
Further, on the next rising edge of the current rising edge of the preset low-frequency clock signal, a new sum of the new accumulated time difference and the clock period of the preset low-frequency clock signal is obtained, and the new sum is compared with the working clock period in the above manner. And in the same way, the operation is executed on each rising edge of the preset low-frequency clock signal until the Bluetooth chip exits the sleep state.
S3, if the sum is less than the working clock period, taking the sum as a new accumulated time difference of the frequency divider circuit, and taking the next rising edge of the current rising edge as a new current rising edge.
And under the condition that the sum value is smaller than the working clock period, the timing of the frequency division circuit does not reach the working clock period, the count of the working clock counter is not increased, only the sum value is used as the new accumulated time difference, and corresponding operation is executed according to the new sum value on the next rising edge of the current rising edge of the preset low-frequency clock signal.
It should be noted that fig. 3 is a schematic diagram of a frequency dividing circuit according to an exemplary embodiment, and as shown in fig. 3, T in the frequency dividing circuitloscFor presetting the clock period, T, of the low-frequency clock signal3p2kFor the working clock cycle, t _ acc is the accumulated time difference, clk _ losc is the predetermined low frequency clock signal, f _3p2k is the count flag, and the frequency divider generates the count flag when the working clock counter can be incremented by 1. The frequency dividing circuit is only an exemplary circuit, and the present disclosure does not limit the structure of the frequency dividing circuit.
S202, under the condition that the Bluetooth chip is detected to exit the sleep state, the current count is determined.
Wherein the current count is a count of the clock counter when the bluetooth chip exits the sleep state.
S203, determining the error duration of the Bluetooth chip in the dormant state according to the awakening accumulated time difference and the preset timing precision corresponding to the high-frequency clock counter.
The timing parameter may include a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state.
In this step, when the bluetooth chip exits from the sleep state, since the wakeup cumulative time difference is smaller than the working clock cycle, the duration of this part is not reflected in the working clock counter of the bluetooth chip, and therefore, after obtaining the current count of the working clock counter, the wakeup cumulative time difference needs to be compensated to the counter.
Considering that the working clock counter counts through the high frequency clock counter after the bluetooth chip exits from the sleep state, the wake-up accumulated time difference can be compensated to the high frequency clock counter, and then the current count of the working clock counter is corrected according to the compensated current count of the high frequency clock counter.
Since there may be various timing accuracies corresponding to the high-frequency clock counter of the bluetooth chip, for example, 0.5us or 1us, when compensating the high-frequency clock counter according to the wake-up accumulated time difference, it is necessary to convert the wake-up accumulated time difference into a unit corresponding to the timing accuracy. Illustratively, the precision of the wake-up accumulated time difference is 1e-15s, when the preset time precision is 0.5us, the wake-up cumulative time difference can be converted by the following formula:
delta＝t_acc/5e8 (1)
wherein, delta is the error duration, and t _ acc is the wakeup accumulation time difference.
It should be noted that division is used in the above formula, which results in a complicated operation process and affects the obtaining efficiency of the error duration, therefore, the present disclosure uses a binary shift method instead of division to calculate the error duration, for example, in the case that the time accumulation register storing the accumulated time difference is 39 bits, the error duration may be approximately expressed as:
Delta≈t_acc/229+t_acc/233+t_acc/237 (2)
and S204, acquiring a first sum of the current count of the high-frequency clock counter and the error duration.
And S205, under the condition that the first sum is determined to be greater than or equal to the preset counting threshold value, updating the current count of the working clock counter to the sum of the current count of the working clock counter and 1.
The preset counting threshold value can be determined according to the timing precision of the high-frequency clock counter and the timing precision of the working clock counter, and the preset counting threshold value is the counting of the high-frequency clock counter when the counting of the working clock counter can be increased by 1. Illustratively, in the case where the timing accuracy of the operating clock counter is 312.5us and the timing accuracy of the high frequency clock counter is 0.5us, the preset count threshold is 624.
In this step, after obtaining the current count of the high-frequency clock counter and the first sum of the error duration, the preset count threshold may be obtained, the first sum is compared with the preset count threshold, when the first sum is greater than or equal to the preset count threshold, it indicates that the count of the working clock counter may be increased by 1, and the current count of the working clock counter is updated to the sum of the current count of the working clock counter and 1. And when the first sum is smaller than the preset counting threshold value, the counting of the working clock counter cannot be increased by 1, and the current counting of the working clock counter is not updated.
And S206, under the condition that the first sum is determined to be larger than or equal to the preset counting threshold, updating the current count of the high-frequency clock counter to be the difference value of the first sum and the preset counting threshold.
In this step, since 1 is added to the count of the operating clock counter when the first sum is greater than or equal to the preset count threshold, the current count of the high frequency clock counter needs to be updated to the difference between the first sum and the preset count threshold.
And S207, under the condition that the first sum is determined to be smaller than the preset counting threshold, updating the current count of the high-frequency clock counter to the first sum.
In this step, when the first sum is smaller than the preset count threshold, it indicates that the count of the working clock counter is not increased by 1, and only the wakeup cumulative time difference needs to be compensated to the high frequency counter, that is, the current count of the high frequency clock counter is updated to the first sum.
It should be noted that, the above steps S204 to S207 may be implemented by a compensation circuit, and the compensation circuit may be designed and implemented by a related art manner, which is not limited in this disclosure. Fig. 4 is a circuit diagram of a bluetooth clock according to an exemplary embodiment, as shown in fig. 4, the circuit includes a frequency dividing circuit and a compensating circuit, after the bluetooth chip enters a sleep state, all circuit operating clocks are a preset low frequency clock clk _ losc, the frequency dividing circuit generates a frequency dividing clock signal f _3p2k, the operating clock counter (bt _ clk counter) counts when f _3p2k is active, and the high frequency clock counter (bit _ cnt counter) stops counting, after the bluetooth chip exits the sleep state, the bt _ clk counter and the bit _ cnt counter are corrected by the compensating circuit.
By adopting the method, after the Bluetooth chip enters the sleep state, the Bluetooth clock of the Bluetooth chip can be maintained through the preset low-frequency clock signal, the current count of the Bluetooth chip when the Bluetooth chip exits the sleep state can be obtained according to the clock period of the preset low-frequency clock signal and the working clock period of the working clock counter of the Bluetooth chip, the awakening accumulated time difference of the Bluetooth chip when the Bluetooth chip exits the sleep state is obtained, the counts of the working clock counter and the high-frequency clock counter of the Bluetooth chip are corrected according to the awakening accumulated time difference, and the Bluetooth clock is calibrated, so that the normal work of the Bluetooth clock can be maintained while the Bluetooth clock precision is ensured.
Fig. 5 is a flowchart illustrating a third method of calibrating a bluetooth clock, according to an example embodiment, as shown in fig. 5, the method including:
s501, under the condition that the Bluetooth chip is detected to enter the sleep state, acquiring a clock cycle of the preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock cycle and a working clock cycle corresponding to the working clock counter, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting.
The frequency-dividing clock signal is a clock signal output by the preset low-frequency clock signal through a frequency-dividing circuit, the working clock counter can be a counter with timing precision of 312.5us in the Bluetooth chip, 1 is added to the working clock counter every 312.5us, the high-frequency clock counter can be a counter with timing precision of 1us or 0.5us in the Bluetooth chip, 1 is added to the high-frequency clock counter every 1us or 0.5us, and the counting of the high-frequency clock counter is 0-624 under the condition that the timing precision of the high-frequency clock counter is 0.5 us; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ. The frequency dividing circuit can be determined according to the frequency of the preset low-frequency clock signal, and the frequency dividing circuits corresponding to the preset low-frequency clock signals with different frequencies can be different.
It should be noted that, the obtaining manner of the clock period of the preset low-frequency clock signal may refer to the obtaining manner of the clock period of the preset low-frequency clock signal in step S201, and is not described herein again.
In this step, controlling the working clock counter of the bluetooth chip to count by dividing the clock signal according to the clock period may include the steps of:
and S1, determining the frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip.
In this step, when the frequency of the preset low-frequency clock signal is not an integral multiple of the bluetooth clock precision (3.2kHZ) of the bluetooth chip, the preset low-frequency clock signal may be divided by a decimal number to obtain the divided clock signal. In fractional division, the division coefficient may be determined according to a clock period of the preset low-frequency clock signal and an operating clock period corresponding to an operating clock counter of the bluetooth chip, for example, in a case where the clock period of the preset low-frequency clock signal is 1/32768s and the operating clock period is 1/3200s, the frequency of the preset low-frequency clock signal is 32.768kHZ, the frequency of the operating clock counter is 3.2kHZ, and the division coefficient may be calculated by the following formula:
Figure BDA0002968028540000171
where div is the division factor, floscFor the frequency of the preset low-frequency clock signal, f3p2kThe frequency of the counter is the operating clock.
And S2, determining a first frequency division number corresponding to the first integer frequency division and a second frequency division number corresponding to the second integer frequency division which form the frequency division clock signal according to the frequency division coefficient.
In this step, after obtaining the frequency division coefficient, the frequency division numbers of the two integer frequency divisions constituting the frequency-divided clock signal may be obtained, and continuing to take the frequency division coefficient of step S502 as an example, in the case that the frequency division coefficient is 10265, the first frequency division number corresponding to the first integer frequency division is 10, the second frequency division number corresponding to the second integer frequency division is 11, and the ratio of the first integer frequency division to the second integer frequency division is 19: 6.
And S3, determining a count threshold corresponding to the frequency division coefficient counter according to the first frequency division number, the second frequency division number and the phase coefficient corresponding to the frequency division clock signal.
Wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal.
In this step, after determining the first division number and the second division number, a count threshold corresponding to a division coefficient counter may be determined according to the first division number, the second division number, and a phase coefficient corresponding to the division clock signal, for example, in the case where the first division number is 10 and the second division number is 11, if the phase coefficient is greater than or equal to 6, the count threshold is 9, and if the phase coefficient is less than 6, the count threshold is 10.
And S4, determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold value.
Wherein, aiming at the current rising edge of the preset low-frequency clock signal, a second counting determination step can be executed in a circulating way until the Bluetooth chip is detected to exit the sleep state, and the second counting determination step comprises the following steps:
s41, determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold;
in the case where the phase coefficient is greater than or equal to 6, it may be determined whether the count of the operating clock counter is increased by 1, based on the count of the division coefficient counter and the count threshold. For example, if the count of the frequency division coefficient counter is equal to the count threshold, the count of the working clock counter is increased by 1, and if the count of the frequency division coefficient counter is smaller than the count threshold, the count of the working clock counter is not increased by 1.
S42, under the condition that the count of the working clock counter is determined to be added with 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge;
after the count of the operating clock counter is increased by 1, the count of the frequency division coefficient counter may be set to 0, and the count of the frequency division coefficient counter and the phase coefficient may be updated according to the frequency division ratio of the frequency division coefficient and the phase coefficient. Illustratively, the division factor is
Figure BDA0002968028540000191
In the case where the phase coefficient is greater than or equal to 6, 6 may be subtracted from the phase coefficient, and the division coefficient is
Figure BDA0002968028540000192
If the phase coefficient is less than 6, 19 may be added to the phase coefficient.
S43, if it is determined that the count of the operation clock counter is not increased by 1, the count of the division coefficient counter is increased by 1, and the next rising edge of the current rising edge is set as a new current rising edge.
FIG. 6 is a flow chart illustrating a method of obtaining a current count of an operational clock counter, as shown in FIG. 6, with a division factor of
Figure BDA0002968028540000193
For example, p _ acc is the phase coefficient, div _ cnt is the count of the frequency division coefficient counter, and bt _ clk is the count of the working clock counter.
It should be noted that the division factor is
Figure BDA0002968028540000194
For example, fig. 7 is a schematic diagram of another frequency divider circuit according to an exemplary embodiment, as shown in fig. 7, div _ cnt in the frequency divider circuit is the count of the frequency divider coefficient counter, p _ acc is the phase coefficient, clk _ losc is the preset low frequency clock signal, f _3p2k is the count flag, and when the working clock counter can be incremented by 1, the frequency divider circuit generates the count flag. The frequency dividing circuit is merely exemplary, and the present disclosure provides a junction to the frequency dividing circuitThe structure is not limited.
S502, determining the first error duration according to the current frequency division count.
In this step, the first error duration may be the number of clock cycles of the preset low frequency clock signal included between the time when the bluetooth chip exits the sleep mode and the time when the working clock counter counts for the last time and adds 1. The first error duration delta _1 can be calculated by the following formula:
delta_1＝div_cnt*Tlosc＝div_cnt*61.03515625 (4)
illustratively, the division factor is
Figure BDA0002968028540000195
In the case of (1), the unit of the first error duration delta _1 ≈ div _ cnt 61.03515625 is 0.5us, and an approximation delta _1 ≈ div _ cnt 61 is taken, and in order to simplify the operation complexity, the first error duration can be calculated by the following formula:
delta_1＝{div_cnt，6'b0}-{div_cnt，1'b0}-div_cnt (5)
where { div _ cnt, 6'b0} indicates that div _ cnt is shifted to the left by 6 bits, and { div _ cnt, 1' b0} indicates that div _ cnt is shifted to the left by 1 bit.
S503, determining the second error duration according to the current phase coefficient.
In this step, the second error duration may be an accumulated error of the frequency-divided clock characterized by the phase coefficient and the frequency of the operating clock counter, exemplarily, where the frequency-divided coefficient is
Figure BDA0002968028540000201
In this case, the second error duration may be calculated by the following formula:
delta_2＝p_acc*Tlosc/25 (6)
the above result is approximated, and delta _2 ≈ p _ acc × 2.5, and in order to simplify the operation complexity, in the case that the phase accumulator corresponding to the phase coefficient has 5 bits, the second error duration may be calculated by the following formula:
delta_2＝{p_acc，1'b0}+p_acc[4:1] (7)
where { p _ acc,1' b0} denotes shifting p _ acc left by 1 bit, p _ acc [4:1] is the 4 th through 1 st bit of data for the phase accumulator.
S504, obtaining an error sum value between the first error duration and the second error duration.
The error sum may be a positive value, i.e., a less clocked portion, or a negative value, i.e., a more clocked portion.
And S505, acquiring a second sum of the current count of the high-frequency clock counter and the error sum.
In this step, in the case where the error sum value is a positive value, the second sum value may be larger than the current count of the high frequency clock counter, and in the case where the error sum value is a negative value, the second sum value may be smaller than the current count of the high frequency clock counter.
And S506, under the condition that the second sum is determined to be larger than or equal to the preset counting threshold value, updating the current count of the working clock counter to the sum of the current count of the working clock counter and 1.
The preset counting threshold value can be determined according to the timing precision of the high-frequency clock counter and the timing precision of the working clock counter, and the preset counting threshold value is the counting of the high-frequency clock counter when the counting of the working clock counter can be increased by 1. Illustratively, in the case where the timing accuracy of the operating clock counter is 312.5us and the timing accuracy of the high frequency clock counter is 0.5us, the preset count threshold is 624.
In this step, after obtaining a second sum of the current count of the high-frequency clock counter and the error duration, the preset count threshold may be obtained, the second sum is compared with the preset count threshold, when the second sum is greater than or equal to the preset count threshold, it indicates that the count of the working clock counter may be increased by 1, and the current count of the working clock counter is updated to the sum of the current count of the working clock counter and 1. And when the second sum is smaller than the preset counting threshold value, the counting of the working clock counter cannot be increased by 1, and the current counting of the working clock counter is not updated.
And S507, under the condition that the second sum is determined to be greater than or equal to the preset counting threshold, updating the current count of the high-frequency clock counter to be the difference value between the second sum and the preset counting threshold.
In this step, since 1 is added to the count of the operating clock counter when the second sum is greater than or equal to the preset count threshold, the current count of the high frequency clock counter needs to be updated to the difference between the second sum and the preset count threshold.
And S508, under the condition that the second sum is smaller than the preset counting threshold value, updating the current count of the high-frequency clock counter to the second sum.
In this step, when the second sum is smaller than the preset count threshold, it indicates that the count of the working clock counter is not increased by 1, and only the wakeup cumulative time difference needs to be compensated to the high frequency counter, that is, the current count of the high frequency clock counter is updated to the second sum.
It should be noted that, the steps S506 to S512 may be implemented by a compensation circuit, and the compensation circuit may be designed and implemented by a related art, which is not limited in the present disclosure.
By adopting the method, after the Bluetooth chip enters the sleep state, the preset low-frequency clock signal can be subjected to fractional frequency division to obtain a frequency division clock signal, and then the working clock counter of the Bluetooth chip is controlled to count through the frequency division clock signal.
Fig. 8 is a schematic structural diagram illustrating an apparatus for calibrating a bluetooth clock according to an exemplary embodiment, where the apparatus, as shown in fig. 8, includes:
the count control module 801 is configured to, when it is detected that the bluetooth chip enters the sleep state, acquire a clock cycle of a preset low-frequency clock signal, control a working clock counter of the bluetooth chip to count through a frequency division clock signal according to the clock cycle, and control a high-frequency clock counter of the bluetooth chip to stop counting, where the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit;
an error duration determining module 802, configured to, when it is detected that the bluetooth chip exits from the sleep state, obtain a current count of the working clock counter, and determine an error duration of the bluetooth chip in the sleep state according to a timing parameter of the frequency dividing circuit when the bluetooth chip exits from the sleep state; the current count is the count of the clock counter when the Bluetooth chip exits the sleep state;
an updating module 803, configured to update the current counts of the working clock counter and the high frequency clock counter according to the error duration, so as to calibrate the bluetooth clock.
Optionally, the count control module 801 is specifically configured to: and controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit the sleep state.
Optionally, the count control module 801 is further configured to: circularly executing a first counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal; if the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; and in the case that the sum value is smaller than the working clock period, taking the sum value as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the error duration determination module 802 is further configured to: and determining the error duration of the Bluetooth chip in the dormant state according to the awakening accumulated time difference and the preset timing precision corresponding to the high-frequency clock counter.
Optionally, the updating module 803 is specifically configured to: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the first sum is determined to be greater than or equal to a preset count threshold; updating the current count of the high frequency clock counter to a difference value of the first sum and the preset count threshold in a case where it is determined that the first sum is greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to the first sum in a case where it is determined that the first sum is less than the preset count threshold.
Optionally, the count control module 801 is further configured to: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; determining a first frequency division number corresponding to a first integer frequency division and a second frequency division number corresponding to a second integer frequency division which form the frequency division clock signal according to the frequency division coefficient; determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the count control module 801 is further configured to: circularly executing a second counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is determined to be increased by 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge; and in the case that the counting of the working clock counter is determined not to be increased by 1, increasing the counting of the frequency division coefficient counter by 1, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits from the sleep state, the current phase coefficient is a phase coefficient of the bluetooth chip when the bluetooth chip exits from the sleep state, and the error duration includes a first error duration and a second error duration; the error duration determination module 802 is further configured to: determining the first error duration according to the current frequency division count; and determining the second error time length according to the current phase coefficient.
Optionally, the updating module 803 is further configured to: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the second sum is determined to be greater than or equal to a preset count threshold; and updating the current count of the high-frequency clock counter to a difference value of the second sum and the preset count threshold in the case that the second sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high-frequency clock counter to the second sum in the case that the second sum is determined to be less than the preset count threshold.
Through the device, after the bluetooth chip gets into the sleep state, can maintain the bluetooth clock of bluetooth chip through predetermineeing low frequency clock signal, this frequency of predetermineeing low frequency clock signal can be the integral multiple of non-3.2 kHZ, to the error that the frequency division arouses, can revise the count of the work clock counter of this bluetooth chip and high frequency clock counter according to the timing parameter of frequency division circuit in bluetooth chip sleep state, calibrate bluetooth clock, like this, can be when guaranteeing bluetooth clock precision, maintain bluetooth clock's normal work.
With regard to the apparatus in the above-described embodiment, the specific manner in which each module performs the operation has been described in detail in the embodiment related to the method, and will not be elaborated here.
The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure. It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.
In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.

Claims (10)

1. A method of calibrating a bluetooth clock, the method comprising:
under the condition that a Bluetooth chip is detected to enter a sleep state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit;
under the condition that the Bluetooth chip is detected to exit from the sleep state, acquiring the current count of the working clock counter, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the sleep state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state;
and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
2. The method of claim 1, wherein in the case that it is detected that the bluetooth chip enters the sleep state, the controlling an operating clock counter of the bluetooth chip to count by dividing a clock signal according to the clock period comprises:
and controlling a working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit the sleep state.
3. The method of claim 2, wherein the controlling the operating clock counter of the bluetooth chip to count by the divided clock signal comprises:
circularly executing a first counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state;
the first count determining step includes:
acquiring the sum of the accumulated time difference of the frequency division circuit and the clock period of the preset low-frequency clock signal;
when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge;
and when the sum value is smaller than the working clock period, taking the sum value as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge.
4. The method of claim 2, wherein the timing parameter comprises a wake-up cumulative time difference, the wake-up cumulative time difference being a cumulative time difference of the frequency divider circuit when the bluetooth chip exits the sleep state; the determining, according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits the sleep state, the error duration of the bluetooth chip in the sleep state includes:
and determining the error duration of the Bluetooth chip in the dormant state according to the awakening accumulated time difference and the preset timing precision corresponding to the high-frequency clock counter.
5. The method of any of claims 2-4, wherein said updating the current counts of the operating clock counter and the high frequency clock counter based on the error duration comprises:
acquiring a first sum of the current count of the high-frequency clock counter and the error duration;
updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the first sum is determined to be greater than or equal to a preset count threshold;
updating the current count of the high frequency clock counter to a difference value of the first sum and the preset count threshold in a case where it is determined that the first sum is greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum in a case where it is determined that the first sum is less than the preset count threshold.
6. The method of claim 2, wherein the controlling the operating clock counter of the bluetooth chip to count by the divided clock signal comprises:
determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip;
determining a first frequency division number corresponding to a first integer frequency division and a second frequency division number corresponding to a second integer frequency division which form the frequency division clock signal according to the frequency division coefficient;
determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal;
and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
7. The method of claim 6, wherein determining the count of the operational clock counter based on the count of the divide coefficient counter, the phase coefficient, and the count threshold comprises:
circularly executing a second counting determination step aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit the sleep state;
the second count determining step includes:
determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold;
under the condition that the count of the working clock counter is determined to be increased by 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge;
and under the condition that the counting of the working clock counter is determined not to be added by 1, adding 1 to the counting of the frequency division coefficient counter, and taking the next rising edge of the current rising edge as a new current rising edge.
8. The method of claim 6, wherein the timing parameters comprise a current divide count and a current phase coefficient, wherein the current divide count is a count of the divide-by-coefficient counter when the Bluetooth chip exits the sleep state, wherein the current phase coefficient is a phase coefficient of the Bluetooth chip when the Bluetooth chip exits the sleep state, and wherein the error duration comprises a first error duration and a second error duration; the determining, according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits the sleep state, the error duration of the bluetooth chip in the sleep state includes:
determining the first error duration according to the current frequency division count;
and determining the second error time length according to the current phase coefficient.
9. The method of claim 8, wherein updating the current counts of the operational clock counter and the high frequency clock counter based on the error duration comprises:
acquiring an error sum value between the first error duration and the second error duration;
acquiring a second sum of the current count of the high-frequency clock counter and the error sum;
updating the current count of the working clock counter to a sum of the current count of the working clock counter and 1 if the second sum is determined to be greater than or equal to a preset count threshold;
and updating the current count of the high-frequency clock counter to a difference value between the second sum and the preset count threshold value when the second sum is determined to be greater than or equal to the preset count threshold value, and updating the current count of the high-frequency clock counter to the second sum when the second sum is determined to be less than the preset count threshold value.
10. An apparatus for calibrating a bluetooth clock, the apparatus comprising:
the counting control module is used for acquiring a clock cycle of a preset low-frequency clock signal under the condition that the Bluetooth chip is detected to enter a sleep state, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit;
the error duration determining module is used for acquiring the current count of the working clock counter under the condition that the Bluetooth chip is detected to exit the sleep state, and determining the error duration of the Bluetooth chip in the sleep state according to the timing parameters of the frequency dividing circuit when the Bluetooth chip exits the sleep state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state;
and the updating module is used for updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
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