CN112953514B - Method and device for calibrating Bluetooth clock - Google Patents

Method and device for calibrating Bluetooth clock Download PDF

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Publication number
CN112953514B
CN112953514B CN202110257281.9A CN202110257281A CN112953514B CN 112953514 B CN112953514 B CN 112953514B CN 202110257281 A CN202110257281 A CN 202110257281A CN 112953514 B CN112953514 B CN 112953514B
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count
frequency
clock
counter
current
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CN112953514A (en
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彭国杰
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Actions Technology Co Ltd
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Actions Technology Co Ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Abstract

The present disclosure relates to a method and apparatus for calibrating a bluetooth clock, the method comprising: under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting; under the condition that the Bluetooth chip exits from the dormant state, acquiring the current count of the working clock counter, and determining the error duration of the Bluetooth chip in the dormant state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the dormant state; the current count is the count of the clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock.

Description

Method and device for calibrating Bluetooth clock
Technical Field
The present disclosure relates to the field of bluetooth technology, and in particular, to a method and apparatus for calibrating a bluetooth clock.
Background
At present, more and more devices are added with Bluetooth functions to realize connection and interaction with mobile phone application programs, and among the devices, a great part of the devices are powered by batteries, so that high requirements on low power consumption are met. In the Bluetooth specification, the low-frequency clock is mainly used for timing of a low-power sleep mode, and the stability of Bluetooth connection can be ensured only by accurately waking up at a specific time, so that the high-precision Bluetooth clock has high requirements on precision and reaches 250ppm.
In the related art, the low-frequency crystal oscillator can be subjected to integer frequency division to obtain a clock meeting the precision (3.2 kHZ) of the bluetooth clock, and the clock is used as the working clock of the bluetooth chip, however, the frequency of the low-frequency crystal oscillator used in the mode needs to be an integer multiple of 3.2kHZ, and when the frequency of the low-frequency crystal oscillator is not an integer multiple of 3.2kHZ, the low-frequency crystal oscillator needs to be subjected to fractional frequency division to obtain the working clock of the bluetooth chip, but the fractional frequency division can introduce errors, so that the precision of the bluetooth clock is reduced.
Disclosure of Invention
In order to solve the above problems, the present disclosure provides a method and apparatus for calibrating a bluetooth clock.
In a first aspect, the present disclosure provides a method of calibrating a bluetooth clock, the method comprising: under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit; under the condition that the Bluetooth chip exits from the dormant state is detected, the current count of the working clock counter is obtained, and the error duration of the Bluetooth chip in the dormant state is determined according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the dormant state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
Optionally, in the case that the bluetooth chip is detected to enter the sleep state, the controlling the working clock counter of the bluetooth chip according to the clock period to count by dividing a clock signal includes: and controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit from the dormant state.
Optionally, the controlling the working clock counter of the bluetooth chip to count by the frequency-dividing clock signal includes: a first counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal; when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; and taking the sum value as a new accumulated time difference of the frequency dividing circuit and taking the next rising edge of the current rising edge as a new current rising edge when the sum value is smaller than the working clock period.
Optionally, the timing parameter includes a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the determining the error duration of the bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits from the sleep state comprises: and determining the error duration of the Bluetooth chip in the sleep state according to the wake-up accumulated time difference and the preset time precision corresponding to the high-frequency clock counter.
Optionally, updating the current counts of the working clock counter and the high frequency clock counter according to the error duration includes: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the first sum value is determined to be greater than or equal to a preset count threshold value; updating a current count of the high frequency clock counter to a difference between the first sum and the preset count threshold if the first sum is determined to be greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum if the first sum is determined to be less than the preset count threshold.
Optionally, the controlling the working clock counter of the bluetooth chip to count by the frequency-dividing clock signal includes: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; according to the frequency division coefficient, determining a first frequency division number corresponding to first integer frequency division and a second frequency division number corresponding to second integer frequency division which form the frequency division clock signal; determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold value includes: a second counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is increased by 1, the count of the frequency division coefficient counter and the phase coefficient are updated to obtain the count of a new frequency division counter and a new phase coefficient, and the next rising edge of the current rising edge is used as a new current rising edge; and in the case that the count of the working clock counter is not increased by 1, increasing the count of the frequency division coefficient counter by 1, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits the sleep state, the current phase coefficient is a phase coefficient when the bluetooth chip exits the sleep state, and the error duration includes a first error duration and a second error duration; the determining the error duration of the bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits from the sleep state comprises: determining the first error duration according to the current frequency division count; and determining the second error duration according to the current phase coefficient.
Optionally, updating the current counts of the working clock counter and the high frequency clock counter according to the error duration includes: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the second sum is determined to be greater than or equal to a preset count threshold value; updating the current count of the high frequency clock counter to be the difference between the second sum and the preset count threshold when the second sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to be the second sum when the second sum is determined to be less than the preset count threshold.
In a second aspect, the present disclosure provides an apparatus for calibrating a bluetooth clock, the apparatus comprising: the counting control module is used for acquiring a clock cycle of a preset low-frequency clock signal under the condition that the Bluetooth chip is detected to enter a dormant state, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit; the error duration determining module is used for acquiring the current count of the working clock counter under the condition that the Bluetooth chip is detected to exit the dormant state, and determining the error duration of the Bluetooth chip in the dormant state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits the dormant state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and the updating module is used for updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock.
Optionally, the counting control module is specifically configured to: and controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit from the dormant state.
Optionally, the counting control module is further configured to: a first counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal; when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; and taking the sum value as a new accumulated time difference of the frequency dividing circuit and taking the next rising edge of the current rising edge as a new current rising edge when the sum value is smaller than the working clock period.
Optionally, the timing parameter includes a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the error duration determining module is further configured to: and determining the error duration of the Bluetooth chip in the sleep state according to the wake-up accumulated time difference and the preset time precision corresponding to the high-frequency clock counter.
Optionally, the updating module is specifically configured to: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the first sum value is determined to be greater than or equal to a preset count threshold value; updating a current count of the high frequency clock counter to a difference between the first sum and the preset count threshold if the first sum is determined to be greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum if the first sum is determined to be less than the preset count threshold.
Optionally, the counting control module is further configured to: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; according to the frequency division coefficient, determining a first frequency division number corresponding to first integer frequency division and a second frequency division number corresponding to second integer frequency division which form the frequency division clock signal; determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the counting control module is further configured to: a second counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is increased by 1, the count of the frequency division coefficient counter and the phase coefficient are updated to obtain the count of a new frequency division counter and a new phase coefficient, and the next rising edge of the current rising edge is used as a new current rising edge; and in the case that the count of the working clock counter is not increased by 1, increasing the count of the frequency division coefficient counter by 1, and taking the next rising edge of the current rising edge as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits the sleep state, the current phase coefficient is a phase coefficient when the bluetooth chip exits the sleep state, and the error duration includes a first error duration and a second error duration; the error duration determining module is further configured to: determining the first error duration according to the current frequency division count; and determining the second error duration according to the current phase coefficient.
Optionally, the updating module is further configured to: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the second sum is determined to be greater than or equal to a preset count threshold value; updating the current count of the high frequency clock counter to be the difference between the second sum and the preset count threshold when the second sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to be the second sum when the second sum is determined to be less than the preset count threshold.
According to the technical scheme, under the condition that the Bluetooth chip is detected to enter the dormant state, the clock period of a preset low-frequency clock signal is acquired, the working clock counter of the Bluetooth chip is controlled to count through a frequency division clock signal according to the clock period, the high-frequency clock counter of the Bluetooth chip is controlled to stop counting, and the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit; under the condition that the Bluetooth chip exits from the dormant state is detected, the current count of the working clock counter is obtained, and the error duration of the Bluetooth chip in the dormant state is determined according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the dormant state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state; and updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock. That is, after the bluetooth chip enters the sleep state, the bluetooth clock of the bluetooth chip can be maintained by a preset low-frequency clock signal, the frequency of the preset low-frequency clock signal can be an integer multiple of 3.2kHZ, and aiming at errors caused by frequency division, the counts of a working clock counter and a high-frequency clock counter of the bluetooth chip can be corrected according to the timing parameters of the frequency division circuit in the sleep state of the bluetooth chip, so that the bluetooth clock can be calibrated, and the normal work of the bluetooth clock can be maintained while the accuracy of the bluetooth clock is ensured.
Additional features and advantages of the present disclosure will be set forth in the detailed description which follows.
Drawings
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification, illustrate the disclosure and together with the description serve to explain, but do not limit the disclosure. In the drawings:
FIG. 1 is a flowchart illustrating a method of calibrating a Bluetooth clock, according to an exemplary embodiment;
FIG. 2 is a flowchart illustrating a second method of calibrating a Bluetooth clock, in accordance with an exemplary embodiment;
FIG. 3 is a schematic diagram of a frequency divider circuit shown according to an exemplary embodiment;
FIG. 4 is a schematic circuit diagram of a Bluetooth clock, according to an exemplary embodiment;
FIG. 5 is a flowchart illustrating a third method of calibrating a Bluetooth clock, according to an exemplary embodiment;
FIG. 6 is a flowchart illustrating a method of obtaining a current count of an operating clock counter, according to an example embodiment;
FIG. 7 is a schematic diagram of another frequency divider circuit shown according to an exemplary embodiment;
fig. 8 is a schematic diagram showing a structure of an apparatus for calibrating a bluetooth clock according to an exemplary embodiment.
Detailed Description
Specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the disclosure, are not intended to limit the disclosure.
In the following description, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying a relative importance or order.
First, an application scenario of the present disclosure will be described. Since the bluetooth clock specified in the bluetooth protocol is a 28-bit counter and the timing precision is 312.5us, a 28-bit counter is usually included in the design, and 1 is added to each 312.5us, and further, since a smaller timing precision is required in the bluetooth transceiving process, a fine counter is usually added to each 1us or 0.5 us. The Bluetooth clock has a clock accuracy requirement of less than + -20 ppm in active mode and less than + -250 ppm in sleep mode. In the sleep mode, in order to save power consumption, the high-frequency high-precision clock of the system is turned off, and the low-frequency clock is used for maintaining the normal count of the Bluetooth clock. Since the timing accuracy of the bluetooth clock is 312.5us, a 3.2KHz clock is required to maintain the normal count of the bluetooth clock.
In the related art, the RC or the low-frequency crystal oscillator of 32kHZ can be subjected to integer frequency division to obtain a clock meeting the precision of a Bluetooth clock (3.2 kHZ) and used as the working clock of the Bluetooth chip, however, the frequency of the RC or the low-frequency crystal oscillator used in the mode needs to be an integer multiple of 3.2kHZ, and when the frequency of the RC or the low-frequency crystal oscillator is not an integer multiple of 3.2kHZ, the RC or the low-frequency crystal oscillator needs to be subjected to fractional frequency division to obtain the working clock of the Bluetooth chip, but the fractional frequency division can introduce errors, so that the precision of the Bluetooth clock is lower.
In order to solve the above-mentioned existing problems, the present disclosure provides a method and apparatus for calibrating a bluetooth clock, after a bluetooth chip enters a sleep state, the bluetooth clock of the bluetooth chip may be maintained by a preset low frequency clock signal, the frequency of the preset low frequency clock signal may be an integer multiple of 3.2kHZ, and for an error caused by frequency division, the count of a working clock counter and a high frequency clock counter of the bluetooth chip may be corrected according to a timing parameter of the frequency division circuit in the sleep state of the bluetooth chip, so that the bluetooth clock may be calibrated, and thus, the normal operation of the bluetooth clock may be maintained while the accuracy of the bluetooth clock may be ensured.
The present disclosure is described below in connection with specific embodiments.
Fig. 1 is a flowchart illustrating a method of calibrating a bluetooth clock, as shown in fig. 1, according to an exemplary embodiment, the method comprising:
s101, under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting.
The period of the preset low-frequency clock signal can be prestored or configurable, the frequency division clock signal is a clock signal output by the frequency division circuit of the preset low-frequency clock signal, the working clock counter can be a counter with the time precision of 312.5us in the Bluetooth chip, the working clock counter is added with 1 every 312.5us, the high-frequency clock counter can be a counter with the time precision of 1us or 0.5us in the Bluetooth chip, the high-frequency clock counter is added with 1 every 1us or 0.5us, and the count of the high-frequency clock counter is 0-624 when the time precision of the high-frequency clock counter is 0.5 us; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ.
In this step, after the bluetooth chip enters a sleep state, in order to reduce the power consumption of the bluetooth chip, the high-frequency clock counter of the bluetooth chip may be controlled to stop counting, and in order to maintain the bluetooth clock of the bluetooth chip, the working clock counter of the bluetooth chip may count by dividing a clock signal.
It should be noted that, considering that the frequencies of the preset low-frequency clock signal may include a plurality of types, if the frequency-divided clock signal cannot be obtained by integer frequency division for the preset low-frequency clock signal of a partial frequency, the frequency-divided clock signal can be obtained by fractional frequency division. For example, when the frequency of the preset low frequency clock signal is 32.768kHZ, the frequency of the preset low frequency clock signal is not an integer multiple of 3.2kHZ, and the preset low frequency clock signal may output the divided clock signal by fractional division.
S102, under the condition that the Bluetooth chip is detected to exit the dormant state, the current count of the working clock counter is obtained, and the error duration of the Bluetooth chip in the dormant state is determined according to the timing parameters of the frequency dividing circuit when the Bluetooth chip exits the dormant state.
The current count is a count of the clock counter when the Bluetooth chip exits the sleep state, the frequency dividing circuit can be determined according to the frequency of the preset low-frequency clock signal, and frequency dividing circuits corresponding to the preset low-frequency clock signals with different frequencies can be different.
In this step, when the frequency dividing circuit outputs the frequency dividing clock signal once, the count of the working clock counter of the bluetooth chip may be increased by 1, and since the count of the working clock counter is always accumulated when the bluetooth chip is in the sleep state, the current count of the working clock counter may be obtained when the bluetooth chip exits from the sleep state. Under the condition that the frequency division circuit is used for dividing frequency by decimal, an error exists in the Bluetooth clock of the Bluetooth chip, for example, if the accumulated time difference between the frequency division circuit and the accurate target clock reaches the working clock period of the working clock counter, the count of the working clock counter is increased by 1, and when the Bluetooth chip exits from the sleep state, if the accumulated time difference between the frequency division circuit and the accurate target clock does not reach the working clock period of the working clock counter, the count of the working clock counter is not increased by 1, and the accumulated time difference is the error of the Bluetooth clock.
In order to avoid the error of the Bluetooth clock of the Bluetooth chip, the error duration of the Bluetooth chip in the sleep state can be obtained according to the timing parameters of the frequency dividing circuit. For example, the accumulated time difference of the frequency dividing circuit may be taken as the error duration. Note that, the error durations corresponding to the different frequency dividing circuits are obtained in different manners, which is not limited in the present disclosure.
And S103, updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration.
Note that, since the high-frequency clock counter stops counting after the bluetooth chip enters the sleep state, the current count of the high-frequency clock counter may be the count of the high-frequency clock counter before the bluetooth chip enters the sleep state.
In this step, after the error time period is acquired, the current counts of the working clock counter and the high-frequency clock counter may be compensated according to the error time period. For example, the error duration may be superimposed on the current counts of the operating clock counter and the high frequency clock counter.
By adopting the method, after the Bluetooth chip enters the dormant state, the Bluetooth clock of the Bluetooth chip can be maintained through the preset low-frequency clock signal, the frequency of the preset low-frequency clock signal can be an integer multiple of 3.2kHZ, and the working clock counter and the high-frequency clock counter of the Bluetooth chip can be corrected according to the timing parameters of the frequency dividing circuit in the dormant state of the Bluetooth chip aiming at errors caused by frequency division, so that the Bluetooth clock can be calibrated, and the normal working of the Bluetooth clock can be maintained while the accuracy of the Bluetooth clock is ensured.
Fig. 2 is a flowchart illustrating a second method of calibrating a bluetooth clock, according to an exemplary embodiment, the method including:
s201, under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of the preset low-frequency clock signal, controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and controlling the high-frequency clock counter of the Bluetooth chip to stop counting.
The frequency division clock signal is a clock signal which is output by a frequency division circuit through a preset low-frequency clock signal, the working clock counter can be a counter with the timing precision of 312.5us in the Bluetooth chip, the working clock counter is added with 1 every 312.5us, the high-frequency clock counter can be a counter with the timing precision of 1us or 0.5us in the Bluetooth chip, the high-frequency clock counter is added with 1 every 1us or 0.5us, and under the condition that the timing precision of the high-frequency clock counter is 0.5us, the count of the high-frequency clock counter is 0-624; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ. The frequency dividing circuit may be determined according to the frequency of the preset low-frequency clock signal, and frequency dividing circuits corresponding to preset low-frequency clock signals with different frequencies may be different.
In this step, the first count determining step may be performed in a loop with respect to a current rising edge of the preset low frequency clock signal until the bluetooth chip is detected to exit the sleep state. The first count determining step may include:
s1, acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal;
the accumulated time difference may be accumulated from the time when the bluetooth chip enters the sleep state, and the accumulated time difference is 0, for example, at the time when the bluetooth chip enters the sleep state. The accumulated time difference may be stored by a time accumulation register during sleep of the bluetooth chip.
S2, under the condition that the sum is larger than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference value between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge;
after obtaining the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal, the sum and the working clock period can be compared, and when the sum is larger than or equal to the working clock period, the count of the working clock counter can be increased by 1, wherein the count of the working clock counter is indicated that the count of the frequency dividing circuit is larger than the working clock period.
After the count of the operation clock counter is increased by 1, a difference between the sum and the operation clock period may be obtained, and the difference may be used as a new accumulated time difference.
Further, at the next rising edge of the current rising edge of the preset low-frequency clock signal, a new sum of the new accumulated time difference and the clock period of the preset low-frequency clock signal is obtained, and the new sum and the working clock period are compared in the above manner. Similarly, the above operation is performed at each rising edge of the preset low frequency clock signal until the bluetooth chip exits from the sleep state.
And S3, taking the sum value as a new accumulated time difference of the frequency dividing circuit and taking the next rising edge of the current rising edge as a new current rising edge when the sum value is smaller than the working clock period.
When the sum is smaller than the working clock period, the timing of the frequency dividing circuit does not reach the working clock period, the count of the working clock counter is not increased, the sum is only used as the new accumulated time difference, and corresponding operation is executed according to the new sum at the next rising edge of the current rising edge of the preset low-frequency clock signal.
It should be noted that fig. 3 is a schematic diagram of a frequency dividing circuit according to an exemplary embodiment, as shown in fig. 3, in which T is losc For the clock period, T, of the preset low frequency clock signal 3p2k For the working clock period, t_acc is the accumulated time difference, clk_losc is the preset low frequency clock signal, f_3p2k is the count flag bit, and the frequency dividing circuit generates the count flag when the working clock counter can be increased by 1. The frequency dividing circuit is only an exemplary illustration, and the present disclosure is not limited to the structure of the frequency dividing circuit.
S202, under the condition that the Bluetooth chip is detected to exit from the dormant state, determining the current count.
The current count is a count of the clock counter when the Bluetooth chip exits the sleep state.
S203, determining the error duration of the Bluetooth chip in the sleep state according to the wake-up accumulated time difference and the preset time precision corresponding to the high-frequency clock counter.
The timing parameter may include a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference when the frequency dividing circuit exits the sleep state.
In this step, when the bluetooth chip exits from the sleep state, since the wake-up accumulated time difference is smaller than the working clock period, the part of the time length is not represented in the working clock counter of the bluetooth chip, and therefore, after the current count of the working clock counter is obtained, the wake-up accumulated time difference needs to be compensated to the counter.
Considering that the working clock counter counts through the high-frequency clock counter after the bluetooth chip exits from the sleep state, the wake-up accumulated time difference can be compensated to the high-frequency clock counter, and then the current count of the working clock counter is corrected according to the compensated current count of the high-frequency clock counter.
Since the timing precision corresponding to the high-frequency clock counter of the bluetooth chip may be various, for example, 0.5us or 1us, when the high-frequency clock counter is compensated according to the wake-up accumulated time difference, the wake-up accumulated time difference needs to be converted into a unit corresponding to the timing precision. For example, the accuracy of the accumulated time difference in this wake-up is 1e -15 s, in the case that the preset time precision is 0.5us, the wake-up accumulated time difference can be converted by the following formula:
delta＝t_acc/5e 8 (1)
wherein delta is the error duration and t_acc is the wake-up accumulated time difference.
It should be noted that, division is used in the above formula, which results in a complex operation process and affects the efficiency of obtaining the error duration, so the disclosure uses a binary shift manner instead of division to calculate the error duration, and in the case that the time accumulation register storing the accumulated time difference is 39 bits, for example, the error duration may be approximately expressed as:
Delta≈t_acc/2 29 +t_acc/2 33 +t_acc/2 37 (2)
S204, obtaining a first sum value of the current count of the high-frequency clock counter and the error duration.
And S205, under the condition that the first sum value is larger than or equal to a preset count threshold value, updating the current count of the working clock counter to be the sum value of the current count of the working clock counter and 1.
The preset counting threshold can be determined according to the timing precision of the high-frequency clock counter and the timing precision of the working clock counter, and the preset counting threshold is the counting of the high-frequency clock counter when the counting of the working clock counter can be increased by 1. For example, in the case where the timing accuracy of the operation clock counter is 312.5us and the timing accuracy of the high frequency clock counter is 0.5us, the preset count threshold is 624.
In this step, after obtaining the first sum of the current count of the high-frequency clock counter and the error duration, the preset count threshold may be obtained, and the first sum and the preset count threshold may be compared, where the first sum is greater than or equal to the preset count threshold, to indicate that the count of the working clock counter may be increased by 1, and the current count of the working clock counter may be updated to the sum of the current count of the working clock counter and 1. And under the condition that the first sum value is smaller than the preset counting threshold value, the counting of the working clock counter cannot be increased by 1, and the current counting of the working clock counter is not updated.
S206, under the condition that the first sum value is larger than or equal to the preset count threshold value, updating the current count of the high-frequency clock counter to be the difference value between the first sum value and the preset count threshold value.
In this step, since the count of the working clock counter is increased by 1 in the case where the first sum is greater than or equal to the preset count threshold, the current count of the high frequency clock counter needs to be updated to the difference between the first sum and the preset count threshold.
S207, updating the current count of the high-frequency clock counter to the first sum value under the condition that the first sum value is smaller than the preset count threshold.
In this step, when the first sum is smaller than the preset count threshold, it means that the count of the working clock counter is not increased by 1, and only the wake-up accumulated time difference is compensated to the high-frequency counter, i.e. the current count of the high-frequency clock counter is updated to the first sum.
It should be noted that, the steps S204 to S207 may be implemented by a compensation circuit, which may be implemented by a design of a related art, and the disclosure is not limited thereto. Fig. 4 is a schematic circuit diagram of a bluetooth clock according to an exemplary embodiment, where the circuit includes a frequency dividing circuit and a compensating circuit, and after the bluetooth chip enters a sleep state, all circuit operation clocks are preset low frequency clocks clk_losc, the frequency dividing circuit generates a frequency dividing clock signal f_3p2k, the operation clock counter (bt_clk counter) counts when f_3p2k is valid, and the high frequency clock counter (bit_cnt counter) stops counting, and after the bluetooth chip exits the sleep state, the bt_clk counter and the bit_cnt counter are corrected by the compensating circuit.
By adopting the method, after the Bluetooth chip enters the sleep state, the Bluetooth clock of the Bluetooth chip can be maintained through the preset low-frequency clock signal, the current count of the Bluetooth chip when the Bluetooth chip exits the sleep state can be obtained according to the clock period of the preset low-frequency clock signal and the working clock period of the working clock counter of the Bluetooth chip, the wake-up accumulated time difference when the Bluetooth chip exits the sleep state is obtained, and the counts of the working clock counter and the high-frequency clock counter of the Bluetooth chip are corrected according to the wake-up accumulated time difference, so that the Bluetooth clock is calibrated, and the normal work of the Bluetooth clock can be maintained while the accuracy of the Bluetooth clock is ensured.
Fig. 5 is a flowchart illustrating a third method of calibrating a bluetooth clock, according to an exemplary embodiment, as shown in fig. 5, the method comprising:
s501, under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of the preset low-frequency clock signal, controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and controlling the high-frequency clock counter of the Bluetooth chip to stop counting.
The frequency division clock signal is a clock signal output by the frequency division circuit through the preset low-frequency clock signal, the working clock counter can be a counter with the timing precision of 312.5us in the Bluetooth chip, the working clock counter is added with 1 every 312.5us, the high-frequency clock counter can be a counter with the timing precision of 1us or 0.5us in the Bluetooth chip, the high-frequency clock counter is added with 1 every 1us or 0.5us, and under the condition that the timing precision of the high-frequency clock counter is 0.5us, the count of the high-frequency clock counter is 0-624; the divided clock signal may be a clock signal having a frequency of 3.2 kHZ. The frequency dividing circuit may be determined according to the frequency of the preset low-frequency clock signal, and frequency dividing circuits corresponding to preset low-frequency clock signals with different frequencies may be different.
It should be noted that, the method for acquiring the clock period of the preset low-frequency clock signal may refer to the method for acquiring the clock period of the preset low-frequency clock signal in step S201, which is not described herein.
In this step, controlling the working clock counter of the bluetooth chip to count by dividing the clock signal according to the clock period may include the steps of:
s1, determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip.
In this step, when the frequency of the preset low-frequency clock signal is not an integer multiple of the bluetooth clock accuracy (3.2 kHZ) of the bluetooth chip, the preset low-frequency clock signal may be divided by a fractional frequency to obtain the divided clock signal. In the fractional frequency division, the frequency division coefficient may be determined according to a clock period of the preset low-frequency clock signal and a working clock period corresponding to a working clock counter of the bluetooth chip, for example, in the case that the clock period of the preset low-frequency clock signal is 1/32768s and the working clock period is 1/3200s, the frequency of the preset low-frequency clock signal is 32.768kHZ, the frequency of the working clock counter is 3.2kHZ, and the frequency division coefficient may be calculated by the following formula:
wherein div is the frequency division coefficient, f losc For the frequency of the preset low-frequency clock signal, f 3p2k For the frequency of the operating clock counter.
S2, according to the frequency division coefficient, determining a first frequency division number corresponding to the first integer frequency division and a second frequency division number corresponding to the second integer frequency division which form the frequency division clock signal.
In this step, after the frequency division coefficient is obtained, the frequency division numbers of the two integer frequency divisions that compose the frequency division clock signal may be obtained, and taking the frequency division coefficient of step S502 as an example, in the case where the frequency division coefficient is 10265, the first frequency division number corresponding to the first integer frequency division is 10, the second frequency division number corresponding to the second integer frequency division is 11, and the ratio of the first integer frequency division to the second integer frequency division is 19:6.
S3, determining a counting threshold corresponding to the frequency division coefficient counter according to the first frequency division number, the second frequency division number and the phase coefficient corresponding to the frequency division clock signal.
The phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal.
In this step, after the first frequency division number and the second frequency division number are determined, a count threshold corresponding to the frequency division coefficient counter may be determined according to the first frequency division number, the second frequency division number, and a phase coefficient corresponding to the frequency division clock signal, for example, in a case where the first frequency division number is 10 and the second frequency division number is 11, if the phase coefficient is greater than or equal to 6, the count threshold is 9, and if the phase coefficient is less than 6, the count threshold is 10.
S4, determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
The second count determining step may be performed in a loop for a current rising edge of the preset low frequency clock signal until the bluetooth chip is detected to exit the sleep state, where the second count determining step includes:
S41, determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold;
in the case where the phase coefficient is greater than or equal to 6, it may be determined whether the count of the operation clock counter is incremented by 1 based on the count of the frequency division coefficient counter and the count threshold. For example, if the count of the frequency division coefficient counter is equal to the count threshold, the count of the working clock counter is increased by 1, and if the count of the frequency division coefficient counter is smaller than the count threshold, the count of the working clock counter is not increased by 1.
S42, under the condition that the count of the working clock counter is increased by 1, updating the count of the frequency division coefficient counter and the phase coefficient to obtain the count of a new frequency division counter and a new phase coefficient, and taking the next rising edge of the current rising edge as a new current rising edge;
after the count of the working clock counter is increased by 1, the count of the frequency division coefficient counter may be set to 0, and the count of the frequency division coefficient counter and the phase coefficient may be updated according to the frequency division ratio of the frequency division coefficient and the phase coefficient. Illustratively, where the division factor is In case the phase coefficient is greater than or equal to 6, the phase coefficient may be subtracted by 6, where the frequency division coefficient is +.>In case the phase coefficient is smaller than 6, the phase coefficient may be added to 19.
And S43, when the fact that the count of the working clock counter is not increased by 1 is determined, the count of the frequency division coefficient counter is increased by 1, and the next rising edge of the current rising edge is taken as a new current rising edge.
FIG. 6 is a flowchart of a method of obtaining a current count of an operating clock counter, according to an exemplary embodiment, as shown in FIG. 6, with a division factorFor example, p_acc is the phase coefficient, div_cnt is the count of the divide coefficient counter, and bt_clk is the count of the working clock counter.
The frequency division coefficient is used asFor example, fig. 7 is a schematic diagram of another frequency-dividing circuit according to an exemplary embodiment, as shown in fig. 7, div_cnt in the frequency-dividing circuit is the count of the frequency-dividing coefficient counter, p_acc is the phase coefficient, clk_losc is the preset low-frequency clock signal, f_3p2k is the count flag bit, and the frequency-dividing circuit generates the count flag when the working clock counter can be incremented by 1. The frequency dividing circuit is only an exemplary illustration, and the present disclosure is not limited to the structure of the frequency dividing circuit.
S502, determining the first error duration according to the current frequency division count.
In this step, the first error duration may be the number of clock cycles of the preset low-frequency clock signal included between the time when the bluetooth chip exits from the sleep mode and the time when the working clock counter counts up by 1 last time. The first error duration delta_1 can be calculated by the following formula:
delta_1＝div_cnt*T losc ＝div_cnt*61.03515625 (4)
illustratively, where the division factor isIn order to simplify the operation complexity, the first error duration delta_1=div_cnt 61.03515625, the unit is 0.5us, the approximation delta_1 is about div_cnt 61 is taken, and the first error duration can be calculated by the following formula:
delta_1＝{div_cnt，6'b0}-{div_cnt，1'b0}-div_cnt (5)
where { div_cnt,6'b0} means that div_cnt is shifted left by 6 bits, and { div_cnt,1' b0} means that div_cnt is shifted left by 1 bit.
S503, determining the second error duration according to the current phase coefficient.
In this step, the second error duration may be an accumulated error of the frequency of the divided clock characterized by a phase coefficient and the operating clock counter, for example, where the divided coefficient isThe second error duration may be calculated by the following formula:
delta_2＝p_acc*T losc /25 (6)
taking an approximation of the above result, delta_2≡p_acc is 2.5, in order to simplify the complexity of the operation, in the case that the phase accumulator corresponding to the phase coefficient is 5 bits, the second error duration may be calculated by the following formula:
delta_2＝{p_acc，1'b0}+p_acc[4:1] (7)
Where { p_acc,1' b0} represents shifting p_acc left by 1 bit, p_acc [4:1] is the data of bits 4 to 1 of the phase accumulator.
S504, obtaining an error sum value between the first error duration and the second error duration.
Wherein the error sum may be positive, i.e. less clocked, or negative, i.e. more clocked.
S505, obtaining a second sum of the current count of the high-frequency clock counter and the error sum.
In this step, the second sum value may be greater than the current count of the high frequency clock counter in the case that the error sum value is a positive value, and may be less than the current count of the high frequency clock counter in the case that the error sum value is a negative value.
S506, under the condition that the second sum value is larger than or equal to a preset count threshold value, updating the current count of the working clock counter to be the sum value of the current count of the working clock counter and 1.
The preset counting threshold can be determined according to the timing precision of the high-frequency clock counter and the timing precision of the working clock counter, and the preset counting threshold is the counting of the high-frequency clock counter when the counting of the working clock counter can be increased by 1. For example, in the case where the timing accuracy of the operation clock counter is 312.5us and the timing accuracy of the high frequency clock counter is 0.5us, the preset count threshold is 624.
In this step, after obtaining the second sum of the current count of the high-frequency clock counter and the error duration, the preset count threshold may be obtained, and the second sum and the preset count threshold may be compared, where the second sum is greater than or equal to the preset count threshold, and if the second sum is greater than or equal to the preset count threshold, it indicates that the count of the working clock counter may be increased by 1, and the current count of the working clock counter is updated to be the sum of the current count of the working clock counter and 1. And under the condition that the second sum value is smaller than the preset counting threshold value, the counting of the working clock counter cannot be increased by 1, and the current counting of the working clock counter is not updated.
S507, under the condition that the second sum value is larger than or equal to the preset count threshold value, updating the current count of the high-frequency clock counter to be the difference value between the second sum value and the preset count threshold value.
In this step, since the count of the working clock counter is increased by 1 when the second sum is greater than or equal to the preset count threshold, the current count of the high frequency clock counter needs to be updated to be the difference between the second sum and the preset count threshold.
And S508, updating the current count of the high-frequency clock counter to the second sum value under the condition that the second sum value is smaller than the preset count threshold value.
In this step, when the second sum is smaller than the preset count threshold, it means that the count of the working clock counter is not increased by 1, and only the wake-up accumulated time difference is compensated to the high frequency counter, i.e. the current count of the high frequency clock counter is updated to the second sum.
It should be noted that, the above steps S506 to S512 may be implemented by a compensation circuit, which may be implemented by a design of a related art, and the disclosure is not limited thereto.
By adopting the method, after the Bluetooth chip enters the sleep state, the preset low-frequency clock signal can be subjected to fractional frequency division, the working clock counter of the Bluetooth chip is controlled to count through the frequency division clock signal after the frequency division clock signal is obtained, in addition, the error duration of the Bluetooth chip in the sleep state can be calculated according to the current frequency division coefficient and the current phase coefficient of the frequency division circuit when the Bluetooth chip exits the sleep state, and the counting of the working clock counter and the high-frequency clock counter of the Bluetooth chip is corrected according to the error duration, so that the Bluetooth clock is calibrated, and the normal working of the Bluetooth clock can be maintained while the accuracy of the Bluetooth clock is ensured.
Fig. 8 is a schematic structural view of an apparatus for calibrating a bluetooth clock according to an exemplary embodiment, and as shown in fig. 8, the apparatus includes:
the counting control module 801 is configured to obtain a clock cycle of a preset low-frequency clock signal when the bluetooth chip is detected to enter a sleep state, control a working clock counter of the bluetooth chip to count through a frequency division clock signal according to the clock cycle, and control a high-frequency clock counter of the bluetooth chip to stop counting, where the frequency division clock signal is a clock signal output by the frequency division circuit of the preset low-frequency clock signal;
the error duration determining module 802 is configured to obtain a current count of the working clock counter when the bluetooth chip is detected to exit the sleep state, and determine an error duration of the bluetooth chip in the sleep state according to a timing parameter of the frequency dividing circuit when the bluetooth chip exits the sleep state; the current count is the count of the clock counter when the Bluetooth chip exits the sleep state;
an updating module 803 is configured to update the current counts of the working clock counter and the high frequency clock counter according to the error duration to calibrate the bluetooth clock.
Optionally, the counting control module 801 is specifically configured to: and controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit from the sleep state.
Optionally, the count control module 801 is further configured to: a first counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the first count determining step includes: acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal; when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge; in the case that the sum is smaller than the duty clock period, the sum is taken as a new accumulated time difference of the frequency dividing circuit, and a next rising edge of the current rising edge is taken as a new current rising edge.
Optionally, the timing parameter includes a wake-up accumulated time difference, where the wake-up accumulated time difference is an accumulated time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the error duration determining module 802 is further configured to: and determining the error duration of the Bluetooth chip in the sleep state according to the wake-up accumulated time difference and the preset time precision corresponding to the high-frequency clock counter.
Optionally, the updating module 803 is specifically configured to: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; under the condition that the first sum value is larger than or equal to a preset count threshold value, updating the current count of the working clock counter to be the sum value of the current count of the working clock counter and 1; updating the current count of the high frequency clock counter to a difference between the first sum and the preset count threshold if the first sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to the first sum if the first sum is determined to be less than the preset count threshold.
Optionally, the count control module 801 is further configured to: determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip; determining a first frequency division number corresponding to the first integer frequency division and a second frequency division number corresponding to the second integer frequency division which form the frequency division clock signal according to the frequency division coefficient; determining a count threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing an alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating a clock period of the frequency division clock signal; and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
Optionally, the count control module 801 is further configured to: a second counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state; the second count determining step includes: determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold; under the condition that the count of the working clock counter is increased by 1, the count and the phase coefficient of the frequency division coefficient counter are updated to obtain the count of a new frequency division counter and a new phase coefficient, and the next rising edge of the current rising edge is used as a new current rising edge; in the case that it is determined that the count of the operation clock counter is not increased by 1, the count of the division coefficient counter is increased by 1, and the next rising edge of the current rising edge is taken as a new current rising edge.
Optionally, the timing parameter includes a current frequency division count and a current phase coefficient, the current frequency division count is a count of the frequency division coefficient counter when the bluetooth chip exits the sleep state, the current phase coefficient is a phase coefficient when the bluetooth chip exits the sleep state, and the error duration includes a first error duration and a second error duration; the error duration determining module 802 is further configured to: determining the first error duration according to the current frequency division count; and determining the second error duration according to the current phase coefficient.
Optionally, the updating module 803 is further configured to: acquiring an error sum value between the first error duration and the second error duration; obtaining a second sum of the current count of the high frequency clock counter and the error sum; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the second sum is determined to be greater than or equal to a preset count threshold value; and updating the current count of the high-frequency clock counter to be the difference value between the second sum value and the preset count threshold value under the condition that the second sum value is determined to be greater than or equal to the preset count threshold value, and updating the current count of the high-frequency clock counter to be the second sum value under the condition that the second sum value is determined to be less than the preset count threshold value.
Through the device, after the Bluetooth chip enters the dormant state, the Bluetooth clock of the Bluetooth chip can be maintained through the preset low-frequency clock signal, the frequency of the preset low-frequency clock signal can be an integer multiple of 3.2kHZ, and the working clock counter and the high-frequency clock counter of the Bluetooth chip can be corrected according to the timing parameters of the frequency dividing circuit in the dormant state of the Bluetooth chip to calibrate the Bluetooth clock according to the error caused by frequency division, so that the normal working of the Bluetooth clock can be maintained while the accuracy of the Bluetooth clock is ensured.
The specific manner in which the various modules perform the operations in the apparatus of the above embodiments have been described in detail in connection with the embodiments of the method, and will not be described in detail herein.
The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings, but the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solutions of the present disclosure within the scope of the technical concept of the present disclosure, and all the simple modifications belong to the protection scope of the present disclosure. In addition, the specific features described in the foregoing embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, the present disclosure does not further describe various possible combinations.
Moreover, any combination between the various embodiments of the present disclosure is possible as long as it does not depart from the spirit of the present disclosure, which should also be construed as the disclosure of the present disclosure.

Claims (8)

1. A method of calibrating a bluetooth clock, the method comprising:
under the condition that the Bluetooth chip is detected to enter a dormant state, acquiring a clock period of a preset low-frequency clock signal, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock period, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit;
Under the condition that the Bluetooth chip exits from the dormant state is detected, the current count of the working clock counter is obtained, and the error duration of the Bluetooth chip in the dormant state is determined according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits from the dormant state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state;
updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock;
the updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock comprises:
acquiring a first sum of the current count of the high-frequency clock counter and the error duration;
updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the first sum value is determined to be greater than or equal to a preset count threshold value;
updating a current count of the high frequency clock counter to a difference between the first sum and the preset count threshold if the first sum is determined to be greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum if the first sum is determined to be less than the preset count threshold;
Or the error duration includes a first error duration and a second error duration; the updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock comprises:
acquiring an error sum value between the first error duration and the second error duration;
acquiring a second sum of the current count of the high-frequency clock counter and the error sum;
updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the second sum is determined to be greater than or equal to a preset count threshold value;
updating the current count of the high frequency clock counter to be the difference between the second sum and the preset count threshold when the second sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to be the second sum when the second sum is determined to be less than the preset count threshold.
2. The method of claim 1, wherein said controlling the operating clock counter of the bluetooth chip to count by dividing the clock signal in accordance with the clock period upon detecting that the bluetooth chip enters the sleep state comprises:
And controlling the working clock counter of the Bluetooth chip to count through the frequency division clock signal according to the clock period and the working clock period corresponding to the working clock counter, and determining the current count under the condition that the Bluetooth chip is detected to exit from the dormant state.
3. The method of claim 2, wherein the controlling the operating clock counter of the bluetooth chip to count by the divided clock signal comprises:
a first counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state;
the first count determining step includes:
acquiring the sum of the accumulated time difference of the frequency dividing circuit and the clock period of the preset low-frequency clock signal;
when the sum is greater than or equal to the working clock period, adding 1 to the count of the working clock counter, taking the difference between the sum and the working clock period as a new accumulated time difference of the frequency dividing circuit, and taking the next rising edge of the current rising edge as a new current rising edge;
And taking the sum value as a new accumulated time difference of the frequency dividing circuit and taking the next rising edge of the current rising edge as a new current rising edge when the sum value is smaller than the working clock period.
4. The method of claim 2, wherein the timing parameter comprises a wake-up cumulative time difference, the wake-up cumulative time difference being a cumulative time difference of the frequency dividing circuit when the bluetooth chip exits the sleep state; the determining the error duration of the bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits from the sleep state comprises:
and determining the error duration of the Bluetooth chip in the sleep state according to the wake-up accumulated time difference and the preset time precision corresponding to the high-frequency clock counter.
5. The method of claim 2, wherein the controlling the operating clock counter of the bluetooth chip to count by the divided clock signal comprises:
determining a frequency division coefficient according to the clock period of the preset low-frequency clock signal and the working clock period corresponding to the working clock counter of the Bluetooth chip;
According to the frequency division coefficient, determining a first frequency division number corresponding to first integer frequency division and a second frequency division number corresponding to second integer frequency division which form the frequency division clock signal;
determining a counting threshold corresponding to a frequency division coefficient counter according to the first frequency division number, the second frequency division number and a phase coefficient corresponding to the frequency division clock signal, wherein the phase coefficient is used for representing the alternating state of the first integer frequency division and the second integer frequency division, and the frequency division coefficient counter is used for calculating the clock period of the frequency division clock signal;
and determining the count of the working clock counter according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold.
6. The method of claim 5, wherein determining the count of the operating clock counter based on the count of the divide by factor counter, the phase factor, and the count threshold comprises:
a second counting and determining step is circularly executed aiming at the current rising edge of the preset low-frequency clock signal until the Bluetooth chip is detected to exit from the dormant state;
the second count determining step includes:
Determining whether the count of the working clock counter is increased by 1 according to the count of the frequency division coefficient counter, the phase coefficient and the count threshold;
under the condition that the count of the working clock counter is increased by 1, the count of the frequency division coefficient counter and the phase coefficient are updated to obtain the count of a new frequency division counter and a new phase coefficient, and the next rising edge of the current rising edge is used as a new current rising edge;
and in the case that the count of the working clock counter is not increased by 1, increasing the count of the frequency division coefficient counter by 1, and taking the next rising edge of the current rising edge as a new current rising edge.
7. The method of claim 5, wherein the timing parameters include a current frequency division count and a current phase coefficient, the current frequency division count being a count of the frequency division coefficient counter when the bluetooth chip exits the sleep state, the current phase coefficient being a phase coefficient of the bluetooth chip when the bluetooth chip exits the sleep state, the error duration including a first error duration and a second error duration; the determining the error duration of the bluetooth chip in the sleep state according to the timing parameter of the frequency dividing circuit when the bluetooth chip exits from the sleep state comprises:
Determining the first error duration according to the current frequency division count;
and determining the second error duration according to the current phase coefficient.
8. An apparatus for calibrating a bluetooth clock, the apparatus comprising:
the counting control module is used for acquiring a clock cycle of a preset low-frequency clock signal under the condition that the Bluetooth chip is detected to enter a dormant state, controlling a working clock counter of the Bluetooth chip to count through a frequency division clock signal according to the clock cycle, and controlling a high-frequency clock counter of the Bluetooth chip to stop counting, wherein the frequency division clock signal is a clock signal output by the preset low-frequency clock signal through a frequency division circuit;
the error duration determining module is used for acquiring the current count of the working clock counter under the condition that the Bluetooth chip is detected to exit the dormant state, and determining the error duration of the Bluetooth chip in the dormant state according to the timing parameter of the frequency dividing circuit when the Bluetooth chip exits the dormant state; the current count is the count of a clock counter when the Bluetooth chip exits the sleep state;
The updating module is used for updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration so as to calibrate the Bluetooth clock; the updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock comprises: acquiring a first sum of the current count of the high-frequency clock counter and the error duration; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the first sum value is determined to be greater than or equal to a preset count threshold value; updating a current count of the high frequency clock counter to a difference between the first sum and the preset count threshold if the first sum is determined to be greater than or equal to the preset count threshold, or updating the current count of the high frequency clock counter to the first sum if the first sum is determined to be less than the preset count threshold;
or the error duration includes a first error duration and a second error duration; the updating the current counts of the working clock counter and the high-frequency clock counter according to the error duration to calibrate the Bluetooth clock comprises: acquiring an error sum value between the first error duration and the second error duration; acquiring a second sum of the current count of the high-frequency clock counter and the error sum; updating the current count of the working clock counter to be the sum of the current count of the working clock counter and 1 under the condition that the second sum is determined to be greater than or equal to a preset count threshold value; updating the current count of the high frequency clock counter to be the difference between the second sum and the preset count threshold when the second sum is determined to be greater than or equal to the preset count threshold, and updating the current count of the high frequency clock counter to be the second sum when the second sum is determined to be less than the preset count threshold.
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