JPH09191086A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the level of integration of a semiconductor integrated circuit device wherein a memory cell transistor is constituted of an N channel MOS. SOLUTION: A sense amplifier SA1 which amplifies an electric potential difference between terminals N, #N in a memory core region is constituted of resistors 3, 4 and N channel MOS transistors wherein gate-drains are cross- connected. A sense amplifier SA2 which contains P channel MOS's and amplifies an electric potential difference between data lines D, #D, and latch transistors 11, 12 are formed in the peripheral region of the memory core.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a DRAM having a sense amplifier provided in a memory core area.

[0002]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional DRAM. In FIG. 5, W1 to W3 are word lines, B and #B,
BL and #BL are bit line pairs, M1 to M3 are memory cells, 51 and 52 are N-channel MOS transistors that function as sense amplifiers, and 53 and 54 are P-channel MOS transistors that function as restore amplifiers. Is an N-channel MOS transistor, and each bit line B, #B, BL, #BL has, for example, 12
An 8-bit memory cell is allocated, and amplifier transistors 51 to 54 are arranged in the center of the bit line pairs B and #B, and BL and #BL so that they can be shared by the upper and lower bit line pairs B and #B, and these are arranged in the memory core area. Is repeatedly arranged vertically and horizontally to form, for example, a 128 × 1024-bit memory block, and amplifier latch transistors 61 and 62 and a power supply voltage V are formed in the memory core peripheral region.
In this configuration, a power supply circuit for dd is arranged.

[0003]

However, in such a circuit device, since the amplifier is composed of the P-channel MOS transistor and the N-channel MOS transistor, the P-channel MOS and the N-channel MOS are processed. An element isolation region is required, and P
The channel MOS usually requires a larger area than the N-channel MOS, which is disadvantageous in high integration.

[0004]

According to the present invention, as in the prior art, a memory cell, a word line, a bit line pair, a sense amplifier, an input / output gate transistor pair, a data line pair, And a column selection line are formed, and the transistor of the memory cell and the input / output gate transistor pair are composed of N-channel MOS transistors. The column selection line is driven to connect the input / output terminal pair of the sense amplifier to the input / output gate transistor pair and the data. The present invention relates to a semiconductor integrated circuit configured to be taken out to a peripheral region of a memory core via a line pair.

According to the present invention, a sense amplifier in a memory core region is composed of a pair of N-channel MOS transistors and a pair of resistors, the gates and drains of these transistors are cross-connected to each other, and the gates and drains are connected to each other. And a first sense amplifier in which one end of each resistor is connected to each connection point of.

Further, the sources of a pair of N-channel MOS transistors are both connected to the sense activation line and taken out to the peripheral region of the memory core, and the other ends of the pair of resistors are both connected to the sense drive line to form a memory core. A second sense amplifier including a P-channel MOS transistor for amplifying the potential difference of the data line pair is provided in the peripheral region of the memory core, and a latch transistor or the like is provided in the peripheral region of the memory core. Precharging is performed via a sense drive line and a resistor.

In this way, the amplifier in the memory core area is
By configuring with channel MOS transistor,
All transistors in the memory core area are N-channel MO
It can be composed of S transistors, and the degree of integration can be increased.

[0008]

1 is a circuit diagram showing a main part of an embodiment of a DRAM as a semiconductor integrated circuit device according to the present invention. The DRAM shown in FIG. 1 has a positive-phase bit line B and a negative-phase bit line #B arranged in pairs in the vertical direction.
At the intersections with the word lines W1 to W3 arranged in the horizontal direction,
The memory cells M1 to M3 are arranged, and similarly, the memory cells are arranged at the intersections of the positive-phase bit lines BL and the negative-phase bit lines #BL arranged in pairs in the vertical direction and the word lines arranged in the horizontal direction. And the bit line pair B, #B and B at the top and bottom of the figure.
A sense amplifier SA1 and the like are arranged in the center of the L and #BL so that they can be shared.

Each memory cell M1 to M3 has an N channel M
It is composed of a series circuit of an OS transistor MT and a capacitor MC, and its source / drain path is each bit line B,
It is connected between #B (BL, #BL) and the cell plate, the gate is connected to the word lines W1, W2, W3, and such memory cells M1 to M3 are connected to the bit lines B, #.
For example, 128 bits are arranged for each of B, BL, and #BL. In the memory core region, an array of such two bit line pairs B, #B and BL, #BL is arranged vertically and horizontally, for example, 128 × 1024. A memory block is formed.

The sense amplifier SA1 is an N channel MO.
It is composed of S transistors 1 and 2 and resistors 3 and 4, and their input and output terminals (terminals) N and #N have their gates and drains cross-connected to each other, and one ends of the respective resistors 3 and 4 are connected. The other ends of the resistors 3 and 4 are both connected to the sense drive line ARL.

FIG. 2 shows the sense amplifier SA1 in the case where the resistance values of the resistors 3 and 4 are 100 K ohms, the driving voltage applied from one end thereof is 5 V, and the connection between the terminal N and the gate terminal of the transistor 2 is removed. The static characteristic is shown, in which the horizontal axis represents the input voltage VIN to the gate terminal and the vertical axis represents the output voltage VOUT of the terminals N and #N.

The voltage V # N at the terminal #N exhibits a voltage drop characteristic due to resistance, and the voltage VN at the terminal N exhibits an on / off characteristic with the threshold value of the transistor as a boundary. As is apparent from FIG. 2, almost full levels can be obtained in terms of DC "H" level and "L" level, and the sense amplifier SA1 having the gate and the drain cross-connected has a flip-flop with resistors 3 and 4 as loads. Function as a group.

In FIG. 1, the sources of the transistors 1 and 2 of the sense amplifier SA1 are both connected to the sense activation line AL, and one ends of the resistors 3 and 4 are connected to the peripheral region of the memory core via the sense drive line ARL. It has been taken out.

The terminals N and #N of the sense amplifier SA1 are
Separation N-channel MOS transistors 5, 6, 7, 8
Connected to the bit lines B, #B, BL, #BL via
Further, it is connected to the sources of the input / output gate N-channel MOS transistors 9 and 10.

The drains of the input / output gate transistors 9 and 10 are connected to the data lines D and #D, and the gates of the transistors are connected to the column line CL and are taken out to the peripheral region of the memory core. BI and BIL
Is a bit line separation line. In the memory core peripheral region, the sense drive line ARL is connected to the power supply potential voltage Vdd via the latch transistor 11, the sense activation line AL is connected to the ground potential via the latch transistor 12, and the data line D, #D is the sense amplifier SA
2 are connected.

The sense amplifier SA2 is a P channel MO.
The S transistors 13 and 14 have their gates grounded, their drains connected to the respective data lines D and #D, and their sources connected to the power supply potential Vdd.

Next, the operation of the DRAM thus constructed will be described. In the standby state for reading, the separation transistors 5, 6, 7, and 8 are in a conductive state, and the bit lines B, #B, BL, and #BL are precharged to the power supply potential Vdd.

When reading data from the memory cell M1, the isolation transistors 7 and 8 are made non-conductive to disconnect the bit lines BL and #BL to which the memory cell M1 does not belong, and the potential of the word line W1 is set to "1". Start up to H ”level (high level). As a result, the charges stored in the capacitor MC in the memory cell M1 are transferred to the bit line B.
Appear on top.

"H" is applied to the capacitor MC of the memory cell M1.
When the level data is written, the potential of the positive phase bit line B slightly rises above Vdd, and the change is given to the terminal N of the sense amplifier SA1. On the other hand, negative phase bit line #
The potential of B maintains the precharge voltage Vdd because the memory cell data is not read, and therefore a potential difference is generated between the bit line B and the anti-phase bit line #BT.

After the word line W1 is raised, the sense activation signal AS is raised, the sources of the transistors 1 and 2 of the sense amplifier SA1 are grounded via the sense activation line AL and the latch transistor 12, and then the sense drive is performed. The signal ARS is lowered, and the resistors 3 and 4 of the sense amplifier SA1 are
A power supply potential Vdd is applied to one end of the sense drive line ARL and the latch transistor 11, and the sense amplifier S
Drive A1.

The terminals N and #N of the sense amplifier SA1 are
Since the terminal N is slightly supplied with a higher potential than the terminal #N, the transistor 2 is turned on more than the transistor 1, and the negative-phase bit line #B is lowered to the “L” level (low level). And As a result, "H" level appears on the positive phase bit line and "L" level appears on the negative phase bit line #B.

After a lapse of a predetermined time required for the potentials of the terminals N and #N to reach a sufficient "H" level or "L" level,
Then, when the potential of the column line CL is raised to "H" level, both the input / output gate N-channel MOS transistors 9 and 10 are turned on, and the potential of the positive phase bit line B is changed to the data line D and the negative phase bit line #. The potential of B is applied to the data line #D, and the data of the memory cell M1 is read to the data lines D and #D.

At this time, the terminal N of the sense amplifier SA1
The H ″ level drops to [H−Vt] due to the threshold potential Vt of the transistor 9, but is restored to the power supply voltage Vdd by the sense amplifier SA2 including the P channel MOS transistors 13 and 14.

After reading to the data lines D and #D, the potential of the column line CL is lowered to "L" level, and the restore operation to the memory cell M1 by the sense amplifier SA1 is performed, thereby ending the read operation. To do.

After the reading is completed, the potential of the word line W1 is lowered, the sense activation signal AS is lowered, and then the isolation transistors 7 and 8 are turned on, and the bit lines B and # are connected through the resistors 3 and 4. After the lapse of the time required to precharge B, the sense drive signal ARS is raised,
Prepare to read the next data.

As described above, in this embodiment, the sense amplifier SA1 is composed of a pair of N-channel MOS transistors that are cross-connected with the resistor, so that the memory core can be composed of all N-channel MOS transistors, and the integrated circuit is integrated. You can increase the degree.

FIG. 3 shows another configuration example that can be used as the sense amplifier SA2 of FIG.
As shown in FIG. 3A, the sense amplifier SA2 is composed of a pair of P-channel MOS transistors 31 and 32, and the gate and drain thereof are cross-connected to each other, whereby high-speed operation is performed. be able to. That is, the "H" level on the data line D changes to the data line #D.
When a "L" level appears at, the transistor 32 tries to turn off in response to the "H" level of the data line D,
When the transistor 1 receives the "L" level of the data line #D and tries to turn on more, as a result, the "H" level of the data line D is actively raised, and the operation of the data line after the column line can be realized at high speed.

Further, as shown in FIG. 3B, the sense amplifier SA2 has a structure in which a latch transistor 34 is provided on the source side of the transistors 31 and 32, and the column line is "
After setting to "H" level, the latch signal RS is continuously set to "
By setting the L ″ level to start the sense operation of the sense amplifier SA2, the operation of the data line after the column line can be realized at high speed while suppressing the current consumption.

Further, as shown in FIG. 3 (C), a sense amplifier SA2 is added to the configuration of FIG. 3 (A), and a pair of N-channel MOS transistors 34 and 35 are provided. By adopting a cross connection configuration in which the two are connected to each other, a high speed operation can be performed with respect to the “L” level of the data line D or #D. Furthermore, in addition to the configuration of FIG. By providing a P-channel MOS latch transistor different from the circuit having the same configuration as 34 and 35, the data line D or #D
With respect to the "L" level of, the operation of the data line after the column line can be realized at high speed while suppressing the current consumption.

FIG. 4 shows the sense amplifier SA1 in FIG.
3 is a layout diagram showing an embodiment of the pattern structure of FIG. FIG. 4A is a pattern structure shown by removing the gate oxide film and the interlayer insulating film, and shows the sources S1 and S2 of the transistors.
And the n + region serving as the drains D1 and D2, the gate line G
1, G2, sense activation line AL, sense drive line AR
Resistors R1 and R2 formed integrally with L, bit lines B and #
It is made of B, and H1 to H8 are connection holes.

As shown in FIG. 4B, the n + region S of the transistor is formed on the substrate surface in the n region which is the active region.
1, D1, S2, D2 are formed, a gate oxide film is formed, and then gate lines G1, G2 are formed so as to cover the gap between the source regions S1, S2 and the drain regions D1, D2. Transistors 1 and 2 are formed, in which case the gate line G of the transistor 1 is formed in the connection hole H5.
1 and the drain region D2 of the transistor 2 are connected.

After forming an insulating layer thereon, FIG.
The sense activation line AL is formed as shown in (4), and at this time, the sources of the transistors 1 and 2 are connected to the sense activation line AL in the connection holes H4 and H8.

Further, after forming an insulating layer thereon, bit lines B and #B are formed. At this time, the gate lines G1 and G2 of the transistors 1 and 2 and the bit lines B and # are formed in the connection holes H2 and H7. Connection with B respectively, and also with connection hole H6
At, the drain D1 of the transistor 1 and the bit line B are connected.

In the regions of the cross-connected transistors 1 and 2 thus constructed, the resistance R of polysilicon is used.
1 and R2 are formed so as to cover them along the bit lines #B and B, respectively, to lower the resistance of the portion serving as the sense drive line ARL. At that time, the resistance R in the connection holes H1 and H5 is reduced.
The sense amplifier SA1 is configured by connecting the bit lines # 1 and R2 to the bit lines #B and B, respectively.

Thus, the cross-connected transistors 1,
By forming a resistor along the bit lines #B and B so as to cover it in the region where 2 is formed, the sense amplifier SA1 can be configured substantially within the width of the bit line, and a highly integrated circuit device can be obtained. Can be adapted.

[0036]

As described above, according to the present invention, the sense amplifier in the memory core region is composed of the pair of N-channel MOS transistors connected in parallel with the resistor.
The memory core can be composed entirely of N-channel MOS transistors, and the degree of integration can be increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of an embodiment of a DRAM according to the present invention.

FIG. 2 is a diagram showing static characteristics of a sense amplifier SA1 in FIG.

FIG. 3 is a circuit diagram showing another configuration example of a sense amplifier SA2 in FIG.

FIG. 4 is a layout diagram showing a pattern structure of a sense amplifier SA1 in FIG.

FIG. 5 is an explanatory view of a conventional technique.

[Explanation of symbols]

1, 2 N channel MOS transistors 3, 4 Resistors 5, 6, 7, 8 Separation N channel MOS transistors 9, 10 Input / output gate N channel MOS
Transistor 11, 12 Latch transistor 13, 14 P-channel MOS transistor AS Sense activation line ASR Sense drive line B, BL Positive phase bit line #B, #BL Reverse phase bit line BI, BIL Bit line separation line CL Column selection line D , #D Data line M1, M2 Memory cell MC Memory cell capacitor MT Memory cell N-channel MOS transistor SA1, SA2 Sense amplifier W1, W2, W3 Word line

Claims (2)

[Claims] 1. A memory cell, a word line, a bit line pair, a sense amplifier, an input / output gate transistor pair, a data line pair, and a column selection line are formed in a memory core region on a semiconductor substrate, and the memory cell transistor is formed. And the input / output gate transistor pair is formed of an N-channel MOS transistor, and drives the column select line to connect the input / output terminal pair of the sense amplifier to the input / output gate transistor pair and the data line pair to the memory core. In a semiconductor integrated circuit configured to be taken out to a peripheral region of a region, the sense amplifier includes a pair of N-channel MOS transistors and a pair of resistors, and a gate and a drain of the transistor are cross-connected to each other, Also, one end of each of the resistors is provided at each connection point between the gate and the drain. A pair of first sense amplifiers connected to each other, the sources of the pair of N-channel MOS transistors are both connected to the sense activation line and taken out to the memory core peripheral region, and the other ends of the pair of resistors are connected together. A second sense amplifier which is connected to a sense drive line and is taken out to the memory core peripheral region and which includes a P-channel MOS transistor and amplifies the potential difference of the data line pair is provided in the memory core peripheral region, and the bit line pair is precharged. Integrated circuit device is configured to be performed via the sense drive line and the resistor. 2. The semiconductor integrated circuit according to claim 1, wherein the sense amplifier in the memory core region is a pair of Ns.
A pattern structure in which a gate and a drain of a channel MOS transistor are cross-connected to each other, and a pair of bit lines formed in an upper layer of the pattern structure and connected to respective corresponding connection points of the gate and the drain. And a resistor formed along the respective bit line in the upper layer of the bit line so as to cover the bit line, one end of which is connected to the corresponding bit line, and the other end of which is also connected to the sense drive line. And a semiconductor integrated circuit device.