JPH09191056A - Semiconductor integrated circuit device and fabrication thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit device which is high in performance and reliability and which has a fine CMOS and complete CMOS fine memory cells formed on a silicon substrate. SOLUTION: A nitride film 14 (of 50-100nm thick) is formed on a lower side of an interlayer insulating oxide film 15 (of 1000-500nm thick), and only the interlayer insulating oxide film 15 is subjected to such a dry etching process that the nitride film firstly becomes much smaller in processing rate than the oxide film. Secondly, the nitride film 14 is subjected to an existing dry etching process to thereby suppress sum-faces of MOS sources/drains 8, 9, 11, and 12, a surface of a gate electrode 7, and missing of a side space 10 and field oxide film 2.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and more particularly to an SRAM (Static Ra
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an ndom access memory) cell and a manufacturing method thereof.

2. Description of the Related Art In recent years, various studies have been conducted on semiconductor integrated circuit devices in order to realize high speed, high integration, low power consumption and the like. SR, which is a semiconductor memory device
In the field of AM, flip-flop inverters are CMO
Research into miniaturizing a complete CMOS type memory cell composed of S is under way. As a known example of the prior art, for example, 19
1994 IEEE JOURNAL OF SOLID-STATE CIRCUIS VOL.29, N
O.11, pp1344 to 1354), an ultra-high speed SRAM using a complete CMOS type memory cell has been realized. Below
The outline of the conventional complete CMOS type memory cell will be described with reference to FIGS. FIG. 18 is a sectional configuration diagram of a complete CMOS type memory cell when manufactured by the existing CMOS technology. An N-type well region 3 is formed in the PMOS region,
On the surface of the well 3, a P-type source / drain 9, 12, a PMOS threshold voltage control layer 4, a polycide layer 20, and a gate electrode 17 composed of an oxide insulating film 21 are formed. In the NMOS area, P
A type well region 4 is formed, and on the surface of the P type well 4, an N type source / drain 8, 11, an NMOS threshold voltage control layer 6, a polycide layer 20 and a gate electrode 17 composed of an oxide insulating film 21 are formed. There is. The source / drain regions 8, 9, 11, 12 of the MOS are
The metal electrode 16 is connected to the opening of the interlayer insulating oxide film 15. Further, in the memory cell, in the portion A shown in the figure, the surface of the polycide layer 20 of the gate electrode 17 and the NMOS source / drains 8 and 11 are connected by the metal electrode 16 in the opening of the interlayer insulating oxide film 15. . FIG. 19 is a plan configuration diagram of a complete CMOS type memory cell. The memory cells consist of two transfer MOSs Qt1 and Qt2, two drive MOSs Qd1 and Qd2 that form a flip-flop circuit, and two load MOSs Qp1 and Qt.
It consists of p2 and is arranged as shown. The portions indicated by A and A'are the connecting portions between the surface of the polycide layer 20 of the gate electrode and the source / drain of the MOS described above. In the process of manufacturing the above-mentioned complete CMOS memory cell, since the connection hole is provided in the interlayer insulating film deposited on the substrate, when the film is etched, over-etching is required in consideration of variations in the film thickness and the like. . At this time, in particular, since the interlayer insulating film is thick, the sidewall having an etching selection ratio substantially equal to that of the interlayer insulating film is also removed at the time of etching for forming the connection hole. As an improved technique for forming a connection hole in an interlayer insulating film near the sidewall, Japanese Patent Laid-Open No. 6-
There is a means disclosed in Japanese Patent Publication No. 196498. That is, according to this publication, the problem is that a part of the sidewall is scraped off during etching of the interlayer film and leaks between the gate electrode and the metal film embedded in the connection hole. It is formed under the film, and after the interlayer insulating film is etched, the insulator is etched to prevent sidewall abrasion.

However, according to the technique disclosed in Japanese Patent Laid-Open No. 6-196498, the sidewall is etched to the portion in contact with the substrate during the etching of the interlayer film, and the substrate under the sidewall is also scraped. The problem is not recognized. The inventors of the present application have found that the structure of the complete CMOS type memory cell described in the above-mentioned prior art has the following problems. Conventionally, when the layer-related insulating oxide film 15 is opened by the existing dry etching technique, the surface portion of the source / drain of the MOS is scraped by about several hundred Å because the layer-related insulating film 15 is very thick. In particular, the above A,
Since the sidewall 10 is also processed in the A'portion, the N-layer 8, P-layer 9 and the metal electrode 16 are connected. Therefore, if the surfaces of the N-layer 8 and the P-layer 9 are excessively shaved, the metal wiring and the well are short-circuited. Furthermore,
When attempting to realize a fine CMOS that constitutes the above-mentioned complete CMOS type memory cell and peripheral circuits, in the fine CMOS, the N− layer 8,
Since it is necessary to make the junction depth of the P− layer 9 shallow, there arises a problem that the metal wiring and the well are short-circuited similarly to the above. (1) An object of the present invention is to provide a semiconductor integrated circuit device having a highly reliable SRAM with a reduced memory cell area. (2) Another object of the present invention is to provide a method for manufacturing a semiconductor device having a highly reliable SRAM with a reduced memory cell area.

Outlines of typical ones of the inventions disclosed by the present application will be described below. The present invention provides a memory cell including a flip-flop circuit having a pair of input / output terminals composed of at least two MISFETs, and a switch MISFET connected to each input / output terminal of the flip-flop circuit. A semiconductor integrated circuit device having the one semiconductor region of the first MISFET and the second MI formed on the memory cell and constituting the flip-flop circuit.
It is characterized by having an interlayer insulating film provided with a connection hole for connecting to the gate electrode of the SFET and a nitride film provided under the interlayer insulating film. That is, in order to achieve the above-mentioned object, the present invention provides a dry etching technique in which a nitride film 14 is provided under the interlayer insulating oxide film 15 and the processing speed of the nitride film is very small with respect to the processing speed of the oxide film. Is used to process only the interlayer insulating oxide film 15. Next, the nitride film 14 is processed by the existing dry etching technique.

Embodiments of the present invention will be described with reference to the drawings. (Embodiment 1) FIG. 1 shows a schematic configuration of a semiconductor integrated circuit device which is a typical embodiment of the present invention. As shown in FIG. 1, the complete CMOS type memory cell of the semiconductor integrated circuit device of the present embodiment has an N channel type insulated gate field effect transistor (hereinafter referred to as N-type) on the main surface of the P type semiconductor substrate 1. MISFET
Also called NMOS. ) And a P channel type insulated gate transistor (hereinafter referred to as P-MISFET or PMOS). The PMOS region is the N-type well region 3
Is formed, and P-type source / drain is formed on the surface of the N-type well 3.
9, 12, a PMOS threshold voltage control layer 4, a gate insulating film 19 and an N-type gate electrode 7 made of a polycrystalline silicon film are formed. In the NMOS region, a P-type well region 5 is formed, and an N-type source / drain 8, 11, an NMOS threshold voltage control layer 6, a gate insulating film 19 and a polycrystalline silicon film are formed on the surface of the P-type well 5. The mold gate electrode 7 is formed. A side wall 10 is provided on the side wall of the gate electrode 7.
Source / drain regions 8, 9, 11, 12 of each MOS,
The surface of the gate electrode 7 is salicided, and the metal electrode 16 is connected to the surface of the silicide 13 at the openings of the nitride film 14 and the interlayer insulating oxide film 15. Furthermore, in the memory cell, in the area A shown in FIG. 1, the surface of the silicide 13 of the gate electrode 7 and the surface of the silicide of the NMOS source / drain 8, 11 are connected by the metal electrode 16 in the opening of the interlayer insulating oxide film 15. Has been done. 2 and 3 are a plan configuration diagram and a circuit configuration diagram of a complete CMOS type memory cell. The memory cell consists of two transfer MOS Qt1 and Qt2 and two drive MOS Qd1 and Qd2 that form a flip-flop circuit and two loads.
It consists of MOS Qp1 and Qp2 and is arranged as shown in FIG. The portions indicated by A and A ′ are the connecting portions between the salicide surface of the gate electrode 7 and the salicide surface of the source / drain of the MOS described above. Note that, in FIG. 2, a portion indicated by a thick solid line frame indicates an active region, that is, a portion where a MOS device without a field insulating film is formed. In the present invention, the interlayer insulating oxide film 15 (1000 ~ 500n
m) is provided with a nitride film 14 (50 to 100 nm) underneath, and first, the interlayer insulating oxide film 15 is formed by using a dry etching technique in which the processing speed of the nitride film is extremely small compared to the processing speed of the oxide film.
Since only the nitride film 14 is processed by the existing dry etching technique, the surface of the source / drain 8, 9, 11, 12 of the MOS under the nitride film 14, the surface of the gate electrode 7,
Scraping of the sidewall 10 and the field insulating film 2 can be suppressed. The dry etching in which the processing speed of the nitride film is extremely smaller than the processing speed of the oxide film is performed, for example, using a mixed gas of CF4, CO, and Ar at a wafer temperature of about 40 [° C]. At this time, the etching selection ratio is about 10. As a result, (1) In the A and A'parts of the complete CMOS memory cell, the N-layer
8, the side wall 10 on the surface of the P-layer 9 is left, the surface of the N-layer 8 and the P-layer 9 can be prevented from being scraped, and the problem that the metal wiring and the well are short-circuited is eliminated. be able to. (2) Since the problem of short circuit between the metal wiring and the well is eliminated in the above-mentioned A and A'sections, the N-layer 8 and P
-The junction depth of the layer 9 can be formed shallow, and a fine CMOS and a complete CMOS type memory cell forming a peripheral circuit can be realized at the same time. (3) In the openings of the interlayer insulating oxide film 15 other than A and A ′ described above, it is possible to reduce the margins between the sidewalls 10 and the openings and between the field insulating film 2 and the openings, and to reduce the size of the microstructure that constitutes the peripheral circuit. Since CMOS and a complete CMOS type fine memory cell can be realized at the same time, high integration of a semiconductor integrated circuit device becomes possible. Next, a method of manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention will be briefly described with reference to FIGS. Figure 4
As shown in, a P-type silicon substrate 1 having a specific resistance of about 10 Ωcm is used. Although a P-type silicon substrate is used for description in the embodiments, an N-type silicon substrate may be used. As shown in FIG. 5, in order to electrically isolate the individual MOSs, the field insulating film 2 is formed with a film thickness of 300 to 500 nm by a known selective oxidation method. As shown in FIG. 6, a threshold voltage control layer 4 for controlling the threshold voltage (Vth) of the N-type well 3 and the PMOS is formed in the PMOS region by using the photolithography technique and the ion implantation technique. Ion implantation of N-type well 3
A type impurity such as phosphorus (P) is implanted at about 10 ¹² to 10 ¹³ / cm ² . The threshold voltage control layer 4 is ion-implanted by implanting a P-type impurity such as boron (B) at a concentration of about 10 ¹³ / cm ² . Further, the threshold voltage control layer 6 for controlling the threshold voltage of the P-type well 5 and the NMOS is formed in the NMOS region by using the photolithography technique and the ion implantation technique. The P-type well 5 is ion-implanted with P-type impurities such as boron (B) 10 ¹² to 10 ¹³ / cm.
Type in about ² . Ion implantation of the threshold voltage control layer 6 is performed by implanting a P-type impurity such as boron (B) at a concentration of about 10 ¹³ / cm ² . Here, the heat treatment may be performed at about 950 ° C. in order to activate the impurities in the wells 3 and 5 and the threshold voltage control layers 4 and 6. As shown in FIG. 7, after forming a gate insulating film 19 and depositing polycrystalline silicon to which phosphorus is added to a film thickness of about 300 nm, using a photolithography technique and a dry etching technique, polycrystalline silicon is formed to a desired dimension. The film is processed to obtain the gate electrode 7 made of the gate insulating film 19 and the N-type polycrystalline silicon film. As shown in FIG. 8, a photolithography technique and an ion implantation technique are used to form an N − layer 8 for LDD formation in the NMOS region and a P − layer 9 for LDD formation in the PMOS region. The ion implantation of the N- layer 8 is performed by implanting an N-type impurity such as phosphorus (P) at a concentration of 10 ¹⁴ / cm ² . Ion implantation of the P- layer 9 is performed by implanting a P-type impurity such as boron (B) at a concentration of 10 ¹⁴ / cm ² . At this time, although not shown in the figure, in order to shorten the channel of the MOS transistor, a known pocket region having a conductivity type opposite to that of the LDD may be formed so as to surround the LDD. here,
A heat treatment is performed to activate the impurities in the N- layer 8 and the P- layer 9.
It may be carried out at about 900 ° C. Since the N-layer 8 and the P-layer 9 are formed at the same time as the fine CMOS forming the peripheral circuit as described above, the junction depth is made shallower than before. Figure
As shown in FIG. 9, an oxide film is deposited to a thickness of about 200 nm, and a sidewall 10 is formed on the sidewall of the MOS gate electrode 7 by the existing anisotropic dry etching technique. Next, using photolithography technology and ion implantation technology,
N + source / drain region 11 in the PMOS region P + source /
The drain region 12 is formed. The ion implantation of the N + layer 11 is N
Type impurities such as arsenic (As) are implanted at 10 ¹⁵ / cm ² or more. P
The ion implantation of the + layer 12 is performed by using P-type impurities such as boron (B).
Drive 10 ¹⁵ / cm ² or more. Where N + layer 11 and P + layer 12
The heat treatment is performed at about 900 ° C. to activate the impurities. As shown in FIG. 10, a silicide layer 13 is formed on the surface of the MOS gate electrode 7 and the source / drain regions 11 and 12 by using a known salicide technique. As shown in Figure 11,
After depositing the nitride film 14 having a thickness of 50 to 100 nm, the interlayer insulating oxide film 15 which is planarized by the existing technique is provided. The role of the nitride film 14 is to play a role of the interlayer insulating film 15 in the connection hole forming process of the next step.
This is for processing only. As shown in FIG. 12, only the interlayer insulating oxide film 15 is processed by using the dry etching technique in which the processing speed of the nitride film is very small with respect to the processing speed of the oxide film. The etching conditions are, for example, CF4 and CO.
Using a mixed gas of Ar and Ar, the wafer temperature is about 40 [° C.]. As shown in FIG. 13, the nitride film 14 is processed by the existing dry etching technique. As a result, the MO under the nitride film 14
Surface of S source / drain 8, 9, 11, 12 and gate electrode 7
It is possible to suppress abrasion of the surface, the side wall 10 and the field insulating film 2. Then, using a photolithography technique and a dry etching technique, after opening the portion to be contacted with the metal wiring by the above-described manufacturing method, the metal wiring film is formed.
A metal electrode 16 is obtained as shown in FIG. 1 by vapor deposition of about 500 to 1000 nm and processing by photolithography technology and dry etching technology. (Embodiment 2) FIG. 14 shows a schematic sectional structure of a semiconductor integrated circuit device according to another embodiment of the present invention. As shown in the figure,
In the complete CMOS type memory cell of the semiconductor integrated circuit device of this embodiment, the gate electrode 17 is composed of the polycide layer 20 and the oxide insulating film 21. In this embodiment, after etching the nitride film,
Although it is necessary to remove the oxide film above the gate electrode, which will be referred to as a cap layer hereinafter, the cap layer is thinner than the interlayer insulating film, and therefore the substrate and the sidewalls are scarcely etched even when overetched. Therefore, also in this structure, the same effect as that of the above embodiment can be obtained, and the fine CMOS and the complete CMOS type memory cell forming the peripheral circuit can be realized. (Embodiment 3) FIG. 15 is a plan configuration diagram of a semiconductor integrated circuit device according to another embodiment of the present invention. As shown in the figure,
To reduce the distance between the drive MOS Qd and the load MOS Qp, place only one of the gate electrodes 7 between the drive MOS Qd and the load MOS Qp, and place the other gate electrode 7'on the load MOS Qp side. It was placed asymmetrically. That is, the patterns of the integrated gate electrodes 7 and 7'of the pair of driving MOSs are asymmetrically arranged. Therefore, as compared with the memory cell having the symmetrical gate pattern configuration as in the first embodiment, the driving MOS Qd and the load MOS Qp are
Since it is not necessary to provide a space between the gate electrodes arranged between the two, a finer complete CMOS type memory cell can be realized. FIG. 16 is a diagram showing the configuration of a microprocessor to which the present invention is applied. As is well known, the microprocessor includes a C cache memory 501 for receiving instructions and a decoder unit 50.
4, data structure macrocell (DS macrocell) 505 that executes and outputs arithmetic processing based on the output signal of the decoder, D cache memory that stores the arithmetic result
502, a code translation look aside buffer (C-TLB) 503b that specifies an address for reading the next instruction after the operation from the C cache memory 501,
It is configured by a D-TLB 503a that converts a logical address of a calculation result into a physical address of the D cache and designates a data storage address. By applying the complete CMOS type memory cell of the present invention to the memory portion, a microprocessor having high performance and high reliability can be realized. Figure
17 is a plan view showing the configuration of an SRAM-IC (one chip) to which the present invention is applied. SRAM is an input pad 601 for inputting an address signal and an input buffer 60 for receiving an address signal.
2, a decoder unit 603 that selects an address based on a signal from an input buffer, a memory cell mat 604 that holds information with a unique address, a sense amplifier 605 that amplifies information in the memory cell, and a sense amplifier 605 The output buffer 606 outputs the output signal to the circuit in the subsequent stage, and the signal output pad 607. By applying the complete CMOS type memory cell of the present invention to the memory portion, an SRAM having high performance and high reliability can be realized.

The effects obtained by this embodiment will be briefly described as follows. (1) Since the problem of short circuit between the metal wiring and the well is eliminated, a semiconductor integrated circuit device having a highly reliable complete CMOS type memory cell can be provided. (2) Since the margins between the side wall 10 and the connection hole opening provided in the interlayer insulating film and the field insulating film 2 and the opening can be reduced, a fine CMOS forming a peripheral circuit can be formed.
It is possible to provide a semiconductor integrated circuit device which simultaneously realizes a complete CMOS type fine memory cell and achieve high integration.

[Brief description of the drawings]

FIG. 1 is a sectional configuration diagram of a complete CMOS type memory cell of a semiconductor integrated circuit device which is a first embodiment of the present invention.

FIG. 2 is a plan configuration diagram of a complete CMOS type memory cell.

FIG. 3 is a circuit configuration diagram of a complete CMOS type memory cell.

FIG. 4 is a cross-sectional view showing the manufacturing method of FIG.

5 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

6 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

7 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

8 is a cross-sectional view showing the manufacturing method of FIG. 1 following FIG.

9 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

10 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

11 is a cross-sectional view showing the manufacturing method of FIG. 1 following FIG.

12 is a cross-sectional view showing the manufacturing method of FIG. 1 subsequent to FIG.

13 is a cross-sectional view showing the manufacturing method of FIG. 1 following FIG.

FIG. 14 is a sectional configuration diagram of a complete CMOS type memory cell of a semiconductor integrated circuit device which is a second embodiment of the present invention.

FIG. 15 is a plan configuration diagram of a complete CMOS type memory cell of a semiconductor integrated circuit device which is a third embodiment of the present invention.

FIG. 16 is a schematic configuration diagram of a microprocessor.

FIG. 17 is a schematic plan view of the configuration of SRAM.

FIG. 18 is a sectional configuration diagram of a complete CMOS type memory cell of a conventional semiconductor integrated circuit device.

FIG. 19 is a plan configuration diagram of a conventional complete CMOS memory cell.

[Explanation of symbols]

1; P type silicon substrate, 2; field insulating film, 3; N type well, 4; PMOS threshold voltage control layer, 5; P type well, 6; NM
OS threshold voltage control layer, 7; gate electrode, 8; N- layer, 9; P
-Layer, 10; sidewall, 11; N + layer, 12; P + layer, 1
3; silicide layer, 14; nitride film, 15; interlayer insulating oxide film, 1
6; metal electrode, 17; gate electrode, 19; gate insulating film, 2
0: polycide layer, 21; oxide insulating film, 501; C cache memory, 502; D cache memory, 503a; D-TL
B, 503b; C-TLB, 504; decoder section, 505; DS macrocell, 601, input pad, 602; input buffer, 60
3; decoder section 604; memory cell 605; sense amplifier 606; output buffer 607; output pad

Claims (12)

[Claims] 1. A memory cell comprising a flip-flop circuit having a pair of input / output terminals composed of at least two MISFETs, and a switch MISFET connected to each input / output terminal of the flip-flop circuit. A semiconductor integrated circuit device having: a connection hole formed on the memory cell, the connection hole connecting one semiconductor region of the first MISFET forming the flip-flop circuit and a gate electrode of the second MISFET. And a nitride film provided below the interlayer insulating film. 2. The semiconductor integrated circuit device according to claim 1, wherein a silicide layer is provided on the gate electrode and the semiconductor region of the MISFET forming the memory cell. 3. The semiconductor integrated circuit device according to claim 1, wherein the gate electrode of the MISFET forming the memory cell is made of polycide. 4. The semiconductor integrated circuit device according to claim 3, further comprising a silicide layer above a semiconductor region of the MISFET forming the memory cell. 5. The semiconductor integrated circuit according to claim 1, wherein the memory cell is a complete CM.
A semiconductor integrated circuit device comprising an OS type memory cell. 6. A semiconductor integrated circuit device according to any one of claims 1 to 4, wherein the semiconductor integrated circuit is a microprocessor. 7. A memory cell comprising a flip-flop circuit having a pair of input / output terminals composed of at least two MISFETs, and a switch MISFET connected to each input / output terminal of the flip-flop circuit. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a first insulating film on a semiconductor substrate;
Forming a second insulating film on the first insulating film;
A first MISFE forming the flip-flop circuit
A connection hole for connecting one semiconductor region of T and the gate electrode of the second MISFET is formed with the second insulating film and the first insulating film.
The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the etching selectivity between the first insulating film and the second insulating film is not less than a predetermined value. 8. A memory cell comprising a flip-flop circuit having a pair of input / output terminals composed of at least two MISFETs, and a switch MISFET connected to each input / output terminal of the flip-flop circuit. A method of manufacturing a semiconductor integrated circuit device, comprising: a step of forming a nitride film on a semiconductor substrate; a step of forming an interlayer insulating film on the nitride film; and a step of forming a first MISFET forming the flip-flop circuit. And a step of forming a connection hole for connecting one semiconductor region and a gate electrode of the second MISFET in the interlayer insulating film and the nitride film, the method for manufacturing a semiconductor integrated circuit device. 9. A memory cell comprising a flip-flop circuit having a pair of input / output terminals composed of at least two MISFETs, and a switch MISFET connected to each input / output terminal of the flip-flop circuit. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a silicide layer on a gate electrode of the MISFET and a semiconductor region; forming a nitride film on a semiconductor substrate; and performing interlayer insulation on the nitride film. Film forming step, one semiconductor region of the first MISFET forming the flip-flop circuit, and the second MIS
And a step of forming a connection hole connecting to a gate electrode of the FET in the interlayer insulating film and the nitride film. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein the gate electrode of the MISFET forming the memory cell is made of polycide. Device manufacturing method. 11. The method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein the MIS forming the memory cell is formed.
A method of manufacturing a semiconductor integrated circuit device, comprising a silicide layer on a semiconductor region of an FET. 12. A semiconductor substrate main surface having at least two Ms.
Flip-flop circuit having a pair of input / output terminals composed of ISFETs, and switch MIS connected to each input / output terminal of the flip-flop circuit
A semiconductor integrated circuit device having a memory cell composed of an FET, wherein a pattern of integrated gate electrodes of a pair of drive MOS and load MOS is asymmetrically arranged on the main surface of the semiconductor substrate. Semiconductor integrated circuit device.