JPH09185491A - Comulative adder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate an entire cumulative adder by operating adding processing at high speed by executing adding processing for each output of multiplier divided into plural parts. SOLUTION: Cumulative adding processing is performed by inputting the low-order side output of multiplier 13 to a 1st adding processing part 115 and inputting the high-order side output of multiplier 13 to a 2nd adding processing part 116. Then, one most significant bit generated by adding processing at the 1st adding processing part 115 is stored into a carry register 108 as a carry bit and added to the 2nd adding processing part 116 after one cycle. Thus, 64-bit adding processing can be provided at high speed and an entire cumulative adder 100 can be accelerated. Namely, since adding processing is simultaneously executed in one cycle while being divided into high-order side and low-order side, this is 64-bit adding processing but can be provided in the same cycle as 32-bit adding processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cumulative adder for inputting data for each unit time and executing a cumulative addition process, and more particularly to a digital signal processor (DSP: Digi).
Ital signal processor) and the like for a cumulative adder that executes a cumulative addition process in a pipeline.

[0002]

2. Description of the Related Art An arithmetic operation circuit constituting a DSP or the like is basically based on an adder, and increasing the speed of the adder is extremely important from the viewpoint of improving the speed of the entire arithmetic operation circuit.

FIG. 5 is a block diagram of a conventional cumulative adder of this type, which is an example of a cumulative adder that executes a cumulative addition process in a pipeline manner to realize a high speed operation.

In FIG. 5, a cumulative adder 10 includes a first input terminal 11, a second input terminal 12, a multiplier 13 having a pipeline register 14, a multiplication register 15, an adder 16, and a cumulative addition register 17. , And an output terminal 18. The calculation accuracy of the data is 32 for the input data.
The output data after calculation is 64 bits.

32-bit input data is input to the first input terminal 11 and the second input terminal 12 of the cumulative adder 10 and supplied to the multiplier 13. Multiplier 13
Outputs a 64-bit precision multiplication data by performing a multiplication process on two input data.

Here, since the processing speed of the multiplier 13 is slower than that of the other arithmetic units of the cumulative adder 10, it is usual that one set of multiplication processing requires a plurality of cycles. For this reason, the pipeline register 14 is provided inside the multiplier 13 to enable input of data every cycle and output of multiplication data.

The multiplication result output from the multiplier 13 is temporarily stored in the multiplication register 15. The multiplication result output from the multiplication register 15 is input to the adder 16 as first input data. In the adder 16, the multiplication register 1
An addition process of the multiplication result from 5 and cumulative addition data from a cumulative addition register 17, which will be described later, is performed. At this time, it is assumed that the input data to the adder 16 has a data length of 64 bits and the output data from the adder 16 has a data length of 65 bits.

The output data from the adder 16 is stored in the cumulative addition register 17. The cumulative addition register 17 is
It is assumed that the input data length is 65 bits and the output data length is 64 bits. As a method of reducing the data length by 1 bit, there is a method of simply reducing the most significant 1 bit or performing a saturation operation process.

The output data from the cumulative addition register 17 becomes the second input data of the adder 16 and is output from the output terminal 18 to the outside as the output data of the cumulative adder 10.

Next, the operation of the cumulative adder 10 will be described with reference to FIG. FIG. 6 is a timing chart showing the operation of the cumulative adder 10. In FIG. 6, X is the first input data, Y is the second input data, pipe-M is the internal data of the pipeline register 14, M is the data stored in the multiplication register 15, and A is the data stored in the cumulative addition register 17. , Z are output data, and t indicates the time for each processing cycle.

Here, the manner in which the cumulative addition process of the four terms is realized as shown in the equation 1 is shown.

[0012]

[Equation 1]

In FIG. 6, mk and sk represent equation (1) and equation 2, respectively. Further, [mk] indicates the value in the pipeline register 14 during the calculation of mk.

Mk = xk × yk (1)

[Equation 2]

The operation of the cumulative adder 10 will be described below for each unit time.

First, the data x1 and y1 are input at time 0 (t = 0), and the cumulative addition process is started.

At time 0, the first half of the multiplication process is performed, and the result is stored in the pipeline register 14 (pipe-M).

At time 1, the latter half of the multiplication process of the first set of input data is performed, and the result is stored in the multiplication register 15 (M) (m1). At the same time, the second set of input data (x2, y2) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 14 (pipe-M).

At time 2, the multiplication result (m1) stored in the multiplication register 15 (M) and the cumulative addition register 17 (A).
Is added to the initial value (0) stored in the adder 16 and the addition result (s1) is added to the cumulative addition register 17 (A).
Write back to At the same time, the latter half of the multiplication process of the second set of input data is performed, and the result is used as the multiplication register 15 (M).
(M2). Also, the third set of input data (x3,
y3) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 14 (pipe-M).

At time 3, the multiplication result (m 2) stored in the multiplication register 15 (M) and the cumulative addition register 17 (A)
The value (s1) stored in (1) is added by the adder 16, and the addition result (s2) is written back to the cumulative addition register 17 (A). At the same time, the latter half of the multiplication process of the third set of input data is performed, and the result is stored in the multiplication register 15 (M) (m3). Also, the fourth set of input data (x4, y
4) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 14 (pipe-M).

At time 4, the multiplication result (m3) stored in the multiplication register 15 (M) and the cumulative addition register 17 (A)
The value (s2) stored in (1) is added by the adder 16, and the addition result (s3) is written back to the cumulative addition register 17 (A). At the same time, the latter half of the multiplication process of the fourth set of input data is performed, and the result is stored in the multiplication register 15 (M) (m4).

At time 5, the multiplication result (m4) stored in the multiplication register 15 (M) and the cumulative addition register 17 (A)
The addition result (s4) is added back to the cumulative addition register 17 (A) with the value (s3) stored in (1).

At time 6, the calculation result (s4) stored in the cumulative addition register 17 (A) is output from the output terminal 18 to the outside of the cumulative adder 10 and the processing is terminated.

[0024]

However, in the conventional cumulative adder 10 as described above, since it is premised that the addition processing is performed every unit time (here, one cycle), the operating frequency is changed. There was a problem that it could not be raised.

That is, the processing speed of the 64-bit adder 16 determines the operating frequency of the entire cumulative adder 10.
For example, as shown in FIG. 5, the multiplication result obtained by multiplying 32-bit input data is 64-bit data, and 64 cycles are required to perform cumulative addition processing using the adder 16 and the cumulative addition register 17. Becomes Therefore, even if the 32-bit multiplication process is performed at high speed by the multiplier 13 including the pipeline register 14, the 64-bit adder 16 currently limits the speed of the cumulative adder 10 as a whole.

In order to avoid this problem, there is an example in which the cumulative addition processing is limited to the upper or lower 32 bits of the multiplication result. However, since the 64-bit data is reduced to 32-bit data, the calculation accuracy is reduced. There is an upper problem.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a cumulative adder capable of operating the addition processing at a high speed to increase the speed of the entire cumulative adder. To aim.

[0028]

SUMMARY OF THE INVENTION A cumulative adder according to the present invention is a cumulative adder that inputs data at each unit time and executes a cumulative addition process. Then, a plurality of addition processing units that perform addition processing for each output of the divided multipliers and an output unit that connects the outputs of the plurality of addition processing units and outputs the result as a cumulative addition result are provided.

Further, the addition processing section includes a first addition processing section for executing addition processing on the lower side of the multiplier output and a second addition processing section for executing addition processing on the higher side of the multiplier output. And a means for adding the carry bit generated in the addition processing of the first addition processing unit to the second addition processing unit after a predetermined time, and the second addition processing unit executes the addition processing based on the carry bit. It may be configured.

Further, the output means includes a third adder for adding the carry bit and the output of the second addition processing section,
A configuration may be provided in which the data output from the third adder is provided on the upper side and the data output from the first addition processing unit is connected to the lower side and held.

Further, the first addition processing section holds the lower side of the output of the multiplier, the first adder, and the first accumulator holding the output of the first adder. An addition register, the first adder adds the output of the first register and the output of the first accumulation register, and the second addition processing unit holds the upper side of the output of the multiplier. A second register, a second adder, and a second accumulation register that holds the output of the second adder, the second adder including the output of the second register and the second register. Add the output of the accumulation register of
Further, a carry register for holding the most significant 1 bit of the addition result of the first adder as a carry bit may be provided, and the carry bit stored in the carry register may be added to the second adder after a unit time.

The cumulative adder according to the present invention is a cumulative adder that inputs data at each unit time and executes a cumulative addition process. The first and second multipliers hold the lower side of the output of the multiplier. , A second register for holding the upper side, a first adder, and a first accumulation register for holding the output of the first adder, and the first adder is 1
Of the output of the first accumulation register and the output of the first accumulation register, and further includes a second adder and a second accumulation register that holds the output of the second adder. The adder is
A third addition that adds the output of the second register and the output of the second accumulation register, and adds the output of the second accumulation register and the most significant bit of the output of the first adder A vessel,
An output register for connecting and holding the output of the third adder on the upper side and the output of the first cumulative addition register on the lower side, and setting the most significant bit of the output of the first adder to the second Of the first adder except the most significant bit, and the second adder outputs the output of the second register. The most significant bit of the output of the second accumulation register and the output of the first adder may be added.

The cumulative adder may be provided with a selection means for selecting the addition result.

Further, the cumulative adder may be an adder which prevents the cumulative addition processing on the output of the multiplier and executes only the addition processing.

Further, the cumulative adder may execute subtraction processing for adding negative data to the output of the multiplier.

Furthermore, the multiplier may be composed of a pipeline multiplier capable of inputting data and outputting multiplication data for each cycle.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION The cumulative adder according to the present invention can be applied to all those that input data for each unit time and execute addition processing. In particular, cumulative addition processing such as DSP is pipelined. The present invention can be applied to a cumulative adder that executes in a similar manner.

First Embodiment FIG. 1 is a block diagram of a cumulative adder according to a first embodiment of the present invention. The cumulative adder shown in FIG. 1 is the same as the cumulative adder shown in FIG. 5, and is an example applied to a cumulative adder that executes a cumulative addition process in a pipeline to realize a high speed operation.

In FIG. 1, the cumulative adder 100 has a first
Input terminal 101, second input terminal 102, multiplier 103 including pipeline register 104, first multiplication register 105, first adder 106, first cumulative addition register 107, carry register 108, Second multiplication register 109, second adder 110, second cumulative addition register 111, third adder 112, output register 11
3 and an output terminal 114. The data calculation accuracy is 32 bits for input data and 64 bits for output data after calculation.

The first multiplication register 105, the first adder 106, and the first cumulative addition register 107 constitute a first addition processing section 115 as a whole, and the second multiplication register 109 and the second adder are included. 110 and the second cumulative addition register 111 collectively constitute the second addition processing unit 116.

That is, the cumulative adder 100 is arranged in parallel with the addition processing section (corresponding to the first addition processing section 115) of the conventional cumulative adder 10 shown in FIG. Unit 116 and carry register 108 for storing the most significant 1 bit of the addition result of first addition processing unit 115.
And a third adder 112 for adding the addition result of the second addition processing unit 116 and the output of the carry register 108, and the output of the third addition unit 112 to the upper side, and the output of the first addition processing unit 115 An output register 113 for additionally storing the data with the addition result set to the lower side is stored, and the lower side of the output of the multiplier 13 is input to the first addition processing unit 115,
The higher-order side of the output of the multiplier 13 is input to the addition processing unit 116 to perform cumulative addition processing, and the first addition processing unit 1
The most significant 1 bit generated in the addition process in 15 is stored in the carry register 108 as a carry bit, and is added to the second addition processing unit 116 after one cycle.

First input terminal 101 of cumulative adder 100
Input data of 32 bits is input to each of the input terminals 102 and 102 and supplied to the multiplier 103. The multiplier 103 multiplies the two input data by 64.
Outputs bit-precision multiplication data.

Here, since the processing speed of the multiplier 103 is slower than that of the other arithmetic units of the cumulative adder 100, a plurality of cycles are usually required for one set of multiplication processing. For this reason,
A pipeline register 104 is provided inside the multiplier 103 to enable input of data every cycle and output of multiplication data.

The multiplication result output from the multiplier 103 is
It is temporarily stored in the first multiplication register 105 and the second multiplication register 105. The multiplication register is the lower 3 of the multiplication result
The first multiplication register 105 that stores 2 bits and the upper 3
It is composed of a second multiplication register 105 which stores 2 bits.

The lower 32-bit data of the multiplication result output from the first multiplication register 105 is input to the first adder 106 as the first input data. In the first adder 106, the lower 32 bits from the first multiplication register 105 are
Bit multiplication result and first cumulative addition register 10 described later
The addition processing with the cumulative addition data of 32 bit length output from 7 is performed.

Here, the addition result output from the first adder 106 has a data length of 33 bits, the most significant 1 bit is stored in the carry register 108, and the lower 32 bits are stored in the first cumulative addition register 107. Store.

On the other hand, the upper 32 bits of the multiplication result stored in the second multiplication register 109 is input to the second adder 110 and the 32-bit length data output from the second cumulative addition register 111 described later. , And 1-bit data output from carry register 108. The addition result output from the second adder 110 has a data length of 33 bits and is stored in the second cumulative addition register 111. In the second cumulative addition register 111, the input data length is 33 bits and the output data length is 32 bits. As a method of reducing the data length by 1 bit, there is a method of simply reducing the most significant 1 bit or performing a saturation operation process. When performing saturation calculation processing,
When the overflow occurs in the second cumulative addition register 111, the value of the first cumulative addition register 107 is also corrected.

In the third adder 112, the 32-bit data output from the second cumulative addition register 111 and the 1-bit data output from the carry register 108 are added to each other to obtain 32-bit length data. Is output. Here again, the most significant 1 bit is reduced as in the case of the output from the second cumulative addition register 111.

The output register 113 is the third adder 112.
The 32-bit data output from the first cumulative addition register 107 is concatenated with the 32-bit data output from the first cumulative addition register 107 to the lower side, and a total of 64-bit data is stored.

The output of the output register 113 is output to the outside from the output terminal 114 as the calculation result of the cumulative adder 100.

Next, the operation of the cumulative adder 100 configured as described above will be described.

The cumulative adder 100 divides the output from the multiplier 103 into an upper side and a lower side, and the first addition processing section 1
The lower side of the output of the multiplier 13 is input to 15 and the upper side of the output of the multiplier 13 is input to the second addition processing unit 116 to perform cumulative addition processing, and at the same time, the first addition processing unit of the lower side is input. The carry bit generated in the addition processing in 115 is added in the second addition processing unit 116 on the upper side after one cycle, thereby eliminating the 64-bit addition processing in one cycle.

The operation and overall operation of each part will be described below with reference to the timing chart of FIG.

FIG. 2 is a timing chart showing the operation of the cumulative adder 100. In FIG. 2, X is the first input data, Y is the second input data, pipe-M is the internal data of the pipeline register 104, ML is the lower 32-bit storage data of the first multiplication register 105, and C is the carry. Carry data in register 108, AL is data stored in first cumulative addition register 107, MH is data stored in upper 32 bits of second multiplication register 109, AH is data stored in second cumulative addition register 111, and Z is output. This is data, and t indicates the time of each processing cycle.

Here, the operation will be described by taking as an example the case where the cumulative addition processing of the fourth term is realized as shown in Expression 3.

[0056]

(Equation 3)

In FIG. 2, the multiplication data mhk and mlk are represented by equations (2) and (3), respectively.

Mhk = (xk × yk) 63 ... 32 Equation (2) mlk = (xk × yk) 31 ... 0 Equation (3) Here, in the equation (2), (N) 63. ..32 represents continuous 32-bit data of bit positions 63 to 32 of data N.

The cumulative addition data shk and slk are
These are represented by equations (4) and (5), respectively.

(Ck, slk) = slk-1 + mlk (4) shk = shk-1 + mhk + ck-1 (5) Here, the cumulative addition data sh0 and sl0 when the initial value c0 of the carry register 108 is: It is shown by the equation (6).

C0 = sl0 = sh0 = 0 Equation (6) Further, in (ck, slk) shown in Equation (4), the most significant 1 bit of the operation result on the right side of Equation (4) is stored in carry register 1
08, and the lower 32 bits are input to the first multiplication register 105.

[Mk] indicates the value in the pipeline register 104 during the calculation of mk.

The operation of the cumulative adder 100 will be described below for each unit time.

First, at time 0 (t = 0), the data x1 and y1 are input to the first input terminal 101 and the second input terminal 102, and the cumulative addition process is started.

At time 0, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe-M). Here, the pipeline register 104 provided inside the multiplier 103 enables input of data every cycle and output of multiplication data.

At time 1, the first set of input data (x1, y
The latter half of the multiplication process of 1) is performed, and the lower 32 bits of this result are stored in the first multiplication register 105 (ML) (m
11), the upper 32 bits are used as the second multiplication register 109
It is stored in (MH) (mh1). At the same time, the second set of input data (x2, y2) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe).
-Store the result in M).

As described above, of the multiplication output from the multiplier 103, the lower 32 bits of data are the first multiplication register 1
Stored in 05 (ML) and the upper 32 bits of data are the second
Stored in the multiplication register 109 (MH).

At time 2, the first adder 106 makes the first
The multiplication result (ml1) stored in the multiplication register 105 (ML) and the initial value (0) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are 1 cumulative addition register 107 (AL)
(Sl1) and stores the most significant 1 bit of the addition result in carry register 108 (C) (c).
1).

In addition, the multiplication result (sh) stored in the second multiplication register 109 (MH) by the second adder 110.
1) and the initial value (0) stored in the second cumulative addition register 111 (AH) and the initial value (0) stored in the carry register 108 (C) are added, and the addition result is the second cumulative value. Write back to the addition register 111 (AH) (sh
1). At the same time, the second set of input data (x2, y2)
The second half of the multiplication process is performed, and the result is the second multiplication register 109 (MH) and the first multiplication register 105 (M).
L) (mh2 and ml2). Furthermore, the third set of input data (x3, y3) is input, the first half of the multiplication process is performed, and the result is pipeline register 104 (pipe-
Store the result in M).

As described above, in the stage of time 2, the multiplication result (ml) stored in the first multiplication register 105 (ML) is stored.
1) and the initial value (0) stored in the first cumulative addition register 107 (AL) are cumulatively added by the first adder 106, and again the first cumulative addition register 107 (A
It is written back to L) (sl1), and the most significant 1 bit of the addition result is stored in carry register 108 (C) (c1). Also, the second set of input data (x2, y2)
2nd half of the multiplication process of and the third set of input data (x3,
The first half of the multiplication process of y3) is similarly executed.

At time 3, the first adder 106 makes the first
The multiplication result (ml2) stored in the multiplication register 105 (ML) and the value (sl1) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are Cumulative addition register 107 (AL)
Is written back to (sl2) and the most significant 1 bit of the addition result is stored in the carry register 108 (C) (c2).

The multiplication result (mh stored in the second multiplication register 109 (MH) by the second adder 110
2) and the value (mh1) stored in the second cumulative addition register 111 (AH) and the value (c1) stored in the carry register 108 (C) are added, and the addition result is stored in the second cumulative addition register. Write back to 111 (AH) (sh2).

The third adder 112 obtains the addition result of the value (sh1) output by the second cumulative addition register 111 (AH) and the value (c1) output by the carry register 108 (C), and outputs the output register 113. In (S), the value (s1) obtained by concatenating the value output from the third adder 112 into the upper 32 bits and the value (sl1) output from the first cumulative addition register 107 (AL) into the lower 32 bits is added. Output. At the same time, the latter half of the multiplication process of the third set of input data is performed.
The result is stored in the second multiplication register 109 (MH) and the first multiplication register 105 (ML) (mh3 and ml).
3). Further, the fourth set of input data (x4, y4) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe-M).

As described above, at the stage of time 3, the same process as that described at time 2 for the third set of input data (x3, y3), that is, the cumulative addition process is divided into the upper side and the lower side. In addition to the operation (c1) of storing the most significant 1 bit of the addition result in the carry register 108 (C), the output value of the second cumulative addition register 111 (AH) is further output by the third adder 112. (Sh1) is added to the output value (c1) of the carry register 108 (C), the addition result is the upper 32 bits, and the output value (sl1) of the first cumulative addition register 107 (AL) is the lower 32 bits. Is stored in the output register 113 (S). As a result, the output register 113 (S)
The cumulative addition result that is concatenated into 64-bit data is stored. Further, the processing of the first half of the multiplication processing of the fourth set of input data (x4, y4) is similarly executed.

At time 4, the first adder 106 makes the first
The multiplication result (ml3) stored in the multiplication register 105 (ML) and the value (s12) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are set to the first Cumulative addition register 107 (AL)
(Sl3) and stores the most significant 1 bit of the addition result in carry register 108 (C) (c)
3).

Further, the second adder 110 causes (MH)
Is added to the multiplication result (mh3) stored in the second cumulative addition register 111 (AH) and the value (c2) stored in the carry register 108 (C). To the second cumulative addition register 111 (A
Write back to H) (sh3).

The third adder 112 obtains the addition result of the value (sh2) output by the second cumulative addition register 111 (AH) and the value (c2) output by the carry register 108 (C), and the output terminal 114 In (Z), the third adder 11
The value output by 2 is in the upper 32 bits, and the value output by the first cumulative addition register 107 (AL) (s12) is in the lower 3
A value (s2) concatenated into 2 bits is output. As a result, the output data (s) stored in the output register 113 at the previous time is output to the output terminal 114 (Z) of the cumulative adder 100.
1) is output. At the same time, the latter half of the multiplication process of the fourth set of input data is performed, and the result is the second multiplication register 109 (MH) and the first multiplication register 105 (ML).
Store in (mh4 and ml4). Although not shown in FIG. 2, similarly, the fifth set of input data (x5, y5) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe-M). It

As described above, in the stage of time 4, the same processing as that described in time 3 is executed, and the cumulative adder 100
From the output terminal 114 (Z) of the output register 1 at the previous time.
The output data (s1) stored in 13 is output. Further, the processing of the latter half of the multiplication processing of the fourth set of input data is executed.

At time 5, the first adder 106 makes the first
The multiplication result (ml4) stored in the multiplication register 105 (ML) and the value (sl3) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are Cumulative addition register 107 (AL)
And the most significant 1 bit of the addition result is stored in the carry register 108 (C) (c).
Four).

Further, the second adder 110 causes (MH)
The multiplication result (mh4) stored in the second cumulative addition register 111 (AH) and the value (sh3) stored in the carry register 108 (C) are added, and the addition result is added. To the second cumulative addition register 111 (A
Write back to H) (sh4).

The third adder 112 obtains the addition result of the value (sh3) output from the second cumulative addition register 111 (AH) and the value (c3) output from the carry register 108 (C), and the output terminal 114 Output to (Z). here,
The output terminal 114 (Z) outputs the value output from the third adder 112 to the upper 32 bits, and outputs the value to the first cumulative addition register 1
The value (s3) obtained by concatenating the value (sl3) output by 07 (AL) with the lower 32 bits is output. Cumulative adder 100
To the output terminal 114 (Z) of the output register 11 at the previous time.
The output data (s2) stored in 3 is output.

At time 6, the first adder 106 makes the first
The multiplication result (ml4) stored in the multiplication register 105 (ML) and the value (sl3) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are Cumulative addition register 107 (AL)
And the most significant 1 bit of the addition result is stored in the carry register 108 (C) (c).
Four).

Further, the second adder 110 causes (MH)
The multiplication result (mh4) stored in the second cumulative addition register 111 (AH) and the value (sh3) stored in the carry register 108 (C) are added, and the addition result is added. To the second cumulative addition register 111 (A
Write back to H) (sh4).

The third adder 112 obtains the addition result of the value (sh4) output from the second cumulative addition register 111 (AH) and the value (c4) output from the carry register 108 (C), and the output terminal 114 In (Z), the third adder 11
The value output by 2 is in the upper 32 bits, and the value output by the first cumulative addition register 107 (AL) (sl4) is in the lower 3
A value (s4) concatenated into 2 bits is output. The output data (s3) stored in the output register 113 at the previous time is output to the output terminal 114 (Z) of the cumulative adder 100.

At time 7, the output data (s4) stored in the output register 113 at time 6 is output from the output terminal 108 to the outside of the cumulative adder 100, and the process ends.

In this way, the cumulative addition process of the input data up to the fourth set is completed after the time 0 to the time 7. Here, an example is shown in which the cumulative addition processing is executed for up to the fourth set of input data, but in reality, data is sequentially input to the first input terminal 101 (X) and the second input terminal 102 (Y). It is input and the cumulative addition process is executed.

In this case, as shown in FIG. 2, the addition is performed by dividing into the upper side and the lower side in one cycle (every time t), and the carry bit generated in the addition processing on the lower side is transferred to the upper side one cycle later. In addition, since the output register 113 is connected to 64 bits, the 64-bit addition processing can be realized in the same number of cycles as the 32-bit addition processing.

As described above, the cumulative adder 100 according to the first embodiment to which the present invention is applied includes the multiplier 103 having the pipeline register 104, the first multiplication register 105, and the first addition. Adder 106 including first multiplier 106 and first cumulative addition register 107, second multiplication register 109, second adder 110, and second adder 110
Second addition processing unit 1 including the cumulative addition register 111 of
16, a carry register 108 that stores the most significant 1 bit of the addition result of the first addition processing unit 115, an addition result of the second addition processing unit 116, and a carry register 108.
A third adder 112 that adds the output and an output register that stores the data by concatenating the data with the output of the third adder 112 on the upper side and the addition result of the first addition processing unit 115 on the lower side. 113 and a new addition processing unit 115.
Is input to the lower side of the multiplier 13 output, and the upper side of the output of the multiplier 13 is input to the second addition processing unit 116 to perform cumulative addition processing, and addition processing in the first addition processing unit 115 is performed. Since the most significant 1 bit generated in 1 is stored in the carry register 108 as a carry bit and added to the second addition processing unit 116 after one cycle, the 64-bit addition processing is realized at high speed. Therefore, the speed of the cumulative adder 100 as a whole can be increased.

That is, the addition process as shown in FIG.
Since the upper side and the lower side are divided and executed at the same time in one cycle, the 64-bit addition processing can be realized in the same cycle as the 32-bit addition processing. 3
Since the 2-bit addition process is fast, the drawbacks that are rate-controlled by the adder in the conventional example can be solved, and the speed of the entire cumulative adder 100 can be increased. Further, unlike the conventional example, since the cumulative addition is not reduced to 32 bits on the upper or lower side of the multiplication result, the calculation accuracy is not deteriorated at all.

Second Embodiment FIG. 3 is a block diagram of a cumulative adder according to a second embodiment of the present invention. The cumulative adder shown in FIG. 3 is the same as the cumulative adder according to the first embodiment shown in FIG. 1, and is an example applied to a cumulative adder that executes a cumulative addition process in a pipeline to realize a high speed. Is. In the description of the cumulative adder according to the second embodiment, elements that are the same as or correspond to those in FIG. 1 are denoted by the same symbols.

In FIG. 1, the cumulative adder 200 has a first
Input terminal 101, second input terminal 102, multiplier 103 including pipeline register 104, first multiplication register 105, first adder 106, first cumulative addition register 107, carry register 108, Second multiplication register 109, second adder 110, second cumulative addition register 111, first selector 211, third adder 1
12, a second selector 212, an output register 113, and an output terminal 114. The data calculation accuracy is 32 bits for input data and 6 for output data after calculation.
4 bits.

The first multiplication register 105, the first adder 106, and the first cumulative addition register 107 together constitute a first addition processing unit 115, and the second multiplication register 109 and the second adder 110 and the second cumulative addition register 111 collectively constitute the second addition processing unit 116.

That is, the cumulative adder 200 includes the first selector 211 for newly selecting the outputs of the first cumulative addition register 107 and the carry register 108, and the first cumulative addition in addition to the cumulative adder 100 shown in FIG. Addition register 10
7, second cumulative addition register 111 and third adder 1
A second selector 212 for selecting the output of 12 is added, and the input to the third adder 112 is added to the carry register 1
08 and the first cumulative addition register 107, and the output value from the cumulative adder 200 is output to the first cumulative addition register 107, the second cumulative addition register 111, and the third adder 112. From the selectors, a 32-bit multiplication mode in which data with a data length of 32 bits is multiplied and a 16-bit multiplication mode in which data with a data length of 16 bits are multiplied can be selected.

The input data to the cumulative adder 200 is the first data
Are supplied to the multiplier 103 from the input terminal 101 and the second input terminal 102. The multiplier 103 can select a multiplication process of 32 bits or a multiplication process of 16 bits on the upper side and 16 bits on the lower side by designation from the outside.

That is, the upper 16 bits of the 32-bit input data x, y are xh, yh, the lower 16 bits are xl,
If each is represented by yl, the output m by the 32-bit multiplication processing is expressed by Expression (7), and the output by the 16-bit multiplication processing is expressed by Expressions (8) to (10).

M = x × y = (xh, xl) × (yh, yl) Equation (7) mh = xh × yh Equation (8) ml = xl × yl Equation (9) m = (mh, ml) Equation (10) Here, even in the 16-bit multiplication process, the multiplication result mh,
Since ml has a data length of 32 bits, the output data from the multiplier 103 is 64 bits in any case.

Since the processing speed of the multiplier 103 is slower than that of the other arithmetic units of the cumulative adder 200, a plurality of cycles is usually required for one set of multiplication processing. Therefore, as in the case of the cumulative adder according to the first embodiment, the pipeline register 104 is provided inside the multiplier 103,
It is possible to input data every cycle and output multiplication data.

The multiplication result output from the multiplier 103 is
It is temporarily stored in the first multiplication register 105 and the second multiplication register 105. The multiplication register is the lower 3 of the multiplication result
The first multiplication register 105 that stores 2 bits and the upper 3
It is composed of a second multiplication register 105 which stores 2 bits.

That is, in the 16-bit multiplication mode, the multiplication result (ml) between the lower sides is set to the first multiplication register 105.
Then, the multiplication result (mh) of the upper side is stored in the second multiplication register 109.

The lower 32-bit data of the multiplication result output from the first multiplication register 105 is input to the first adder 106 as the first input data. In the first adder 106, the lower 32 bits from the first multiplication register 105 are
The addition processing of the bit multiplication result and the 32-bit-long cumulative addition data output from the first cumulative addition register 107 is performed.

Here, the addition result output from the first adder 106 has a data length of 33 bits, the most significant 1 bit is stored in the carry register 108, and the lower 32 bits are stored in the first cumulative addition register 107. Store. further,
In the cumulative adder 200 according to this embodiment, the output of the carry register 108 is input to the second adder 110 and the first selector 211.

On the other hand, the upper 32 bits of the multiplication result stored in the second multiplication register 109 are input to the second adder 110 and the 32-bit length data output from the second cumulative addition register 111, and Carry register 108
The addition processing with the 1-bit data output from is performed.
The addition result output from the second adder 110 has a data length of 33 bits and is stored in the second cumulative addition register 111. In the second cumulative addition register 111, the input data length is 33 bits and the output data length is 32 bits.
As a method of reducing the data length by 1 bit, there is a method of simply reducing the most significant 1 bit or performing a saturation operation process. The output of the second cumulative addition register 111 is the second adder 110, the third adder 112, and the second adder 110.
Input to the selector 212.

The first selector 211 selects either the output from the carry register 108 or the output from the cumulative addition register 107 and outputs it to the third adder 112.

In the third adder 112, the 32-bit data output from the second cumulative addition register 111 and the output selected by the first selector 211 (1-bit output from the carry register 108 or the cumulative addition register (32-bit output from 107)
The 32-bit data is output to the second selector 212. Here again, the most significant 1 bit is reduced as in the case of the output from the second cumulative addition register 111.

The second selector 212 outputs the output of the first cumulative addition register 107 and the second cumulative addition register 111.
And the output of the third adder 112, and outputs the selected output to the output register 113.

The output register 113 is the third adder 112.
The 32-bit data output from the first cumulative addition register 107 is concatenated with the 32-bit data output from the first cumulative addition register 107 to the lower side, and a total of 64-bit data is stored.

The output of the output register 113 is output to the outside from the output terminal 114 as the calculation result of the cumulative adder 200.

Next, the operation of the cumulative adder 200 configured as described above will be described.

The cumulative adder 200 according to the present embodiment can switch the operation mode between the cumulative addition mode of 32 bits and the cumulative addition mode of 16 bits by the first selector 211 and the second selector 212. It is characterized by having done.

To set the operation mode of the cumulative adder 200 to the 32-bit multiplication mode similar to the operation of the cumulative adder 100 according to the first embodiment, the following is done.
That is, the first selector 211 always selects the output from the carry register 108, and the second selector 212
Set to always select the output from the third adder 112. With this setting, the same operation as the operation timing shown in FIG. 2 can be realized.

Therefore, the operation in the case of performing the cumulative addition process of 16 bits will be described here.

The operation of each part and the overall operation will be described below with reference to the timing chart of FIG.

FIG. 4 is a timing chart showing the operation in the cumulative addition process of 16 bits. X in FIG.
Is the first input data, Y is the second input data, pipe-M
Is internal data of the pipeline register 104, ML is lower 32-bit storage data of the first multiplication register 105,
AL is data stored in the first cumulative addition register 107, M
H is data stored in the upper 32 bits of the second multiplication register 109, AH is data stored in the second cumulative addition register 111, Z is output data, and t represents time for each processing cycle.

Here, the operation will be described by taking as an example the case where the cumulative addition processing of the four terms is realized as shown in Expression 4.

[0115]

(Equation 4)

In FIG. 4, the multiplication data mhk and mlk are represented by equations (11) and (12), respectively.

Mhk = xhk × yhk (Equation (11)) mlk = xlk × ylk (Equation (12)) Further, the cumulative addition data shk and slk are represented by Equation (13) and Equation (14), respectively.

Slk = slk-1 + mlk (Equation (13)) shk = shk-1 + mhk (Equation (14)) Here, the cumulative addition data sh0 and sl0 are expressed by Equation (15).
Indicated by

Sl0 = sh0 = 0 Expression (15) Further, [mk] represents the value in the pipeline register 104 during the calculation of mk.

The operation of the cumulative adder 200 will be described below for each unit time.

First, at time 0 (t = 0), the data x1 and y1 are input to the first input terminal 101 and the second input terminal 102, and the cumulative addition process is started.

At time 0, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe-M). Here, the pipeline register 104 provided inside the multiplier 103 enables input of data every cycle and output of multiplication data.

At time 1, the first set of input data (x1, y
The latter half of the multiplication process of 1) is performed, and the lower 32 bits of this result are stored in the first multiplication register 105 (ML) (m
11), the upper 32 bits are used as the second multiplication register 109
It is stored in (MH) (mh1). At the same time, the second set of input data (x2, y2) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe).
-Store the result in M).

As described above, in the multiplication output from the multiplier 103, the lower 32-bit data is the first multiplication register 1
Stored in 05 (ML) and the upper 32 bits of data are the second
Stored in the multiplication register 109 (MH).

At time 2, the first adder 106 makes the first
The multiplication result (ml1) stored in the multiplication register 105 (ML) and the initial value (0) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are 1 cumulative addition register 107 (AL)
Write back to (sl1).

Further, the multiplication result (mh stored in the second multiplication register 109 (MH) by the second adder 110
1) and the initial value (0) stored in the second cumulative addition register 111 (AH) are added, and the addition result is written back to the second cumulative addition register 111 (AH) (sh1).
At the same time, the latter half of the multiplication process of the second set of input data (x2, y2) is performed, and the result is stored in the second multiplication register 1
09 (MH) and the first multiplication register 105 (ML) (mh2 and ml2). Furthermore, the third set of input data (x3, y3) is input and the first half of the multiplication process is performed.
The result is stored in the pipeline register 104 (pipe-M).

As described above, in the stage of time 2, the multiplication result (ml) stored in the first multiplication register 105 (ML) is stored.
1) and the initial value (0) stored in the first cumulative addition register 107 (AL) are cumulatively added by the first adder 106, and again the first cumulative addition register 107 (A
It is written back to L) (sl1). The second half of the multiplication process of the second set of input data (x2, y2) and the first half of the multiplication process of the third set of input data (x3, y3) are similarly executed.

At time 3, the first adder 106 makes the first
The multiplication result (ml2) stored in the multiplication register 105 (ML) and the value (sl1) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are Cumulative addition register 107 (AL)
The data is written back to (sl2) and the same data is output to the first selector 211. The first selector 211 selects the input from the first cumulative addition register 107 (AL) and outputs it to the third adder 112.

The multiplication result (mh) stored in the second multiplication register 109 (MH) by the second adder 110
2) and the value (sh1) stored in the second cumulative addition register 111 (AH) are added, and the addition result is written back to the second cumulative addition register 111 (AH) (sh2).

In the third adder 112, the first selector 2
The addition result (s1) of the value (sl1) output by 11 and the value (sh1) output by the second cumulative addition register 111 (AH) is obtained and output to the second selector 212. The second selector 212 selects the input from the third adder 112 and outputs it to the output register 113 (S). At the same time, the latter half of the multiplication process of the third set of input data is performed, and the result is stored in the second multiplication register 109 (MH) and the first multiplication register 105 (ML) (mh3 and ml3). Further, the fourth set of input data (x4, y4) is input, the first half of the multiplication process is performed, and the result is stored in the pipeline register 104 (pipe-M).

As described above, at the stage of time 3, the same processing as that described at time 2 for the third set of input data (x3, y3), that is, the cumulative addition process is divided into the upper side and the lower side. In addition to the processing performed by the first selector 211, the operation of selecting the input from the first cumulative addition register 107 (AH) by the first selector 211 and outputting it to the third adder 112, and the third selector 212 by the third The operation of selecting the addition result (s1) by the adder 112 and outputting it to the output register 113 (S) is performed. As a result, 16-bit cumulative addition processing is executed.

At time 4, the first adder 106 makes the first
The multiplication result (ml3) stored in the multiplication register 105 (ML) and the value (s12) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are set to the first Cumulative addition register 107 (AL)
Write back to (sl3) and the first selector 211
Output the same data to. The first selector 211 is the first
The input from the cumulative addition register 107 (AL) is selected and output to the third adder 112.

Further, the second adder 110 causes (MH)
The multiplication result (mh3) stored in the second cumulative addition register 111 (AH) is added to the value (sh2) stored in the second cumulative addition register 111 (AH).
Write back to H) (sh3).

In the third adder 112, the first selector 2
The addition result of the value (sl2) output from 11 and the value (sh2) output from the second cumulative addition register 111 (AH) is obtained and output to the second selector 212. The output data (s1) stored in the output register 113 (S) at the previous time (time 3) is output to the output terminal 114 (Z) of the cumulative adder 200. At the same time, the latter half of the multiplication processing of the fourth set of input data is performed, and the result is the second multiplication register 109 (MH) and the first multiplication register 105.
Store in (ML) (mh4 and ml4).

As described above, in the stage of time 4, the same processing as that described in time 3 is executed, and the cumulative adder 200
From the output terminal 114 (Z) of the output register 1 at the previous time.
The output data (s1) stored in 13 is output. Further, the processing of the latter half of the multiplication processing of the fourth set of input data is executed.

At time 5, the first adder 106 makes the first
The multiplication result (ml4) stored in the multiplication register 105 (ML) and the value (sl3) stored in the first cumulative addition register 107 (AL) are added, and the lower 32 bits of the addition result are Cumulative addition register 107 (AL)
Write back to (sl4) and the first selector 211
Output the same data to. The first selector 211 is the first
The input from the cumulative addition register 107 (AL) is selected and output to the third adder 112.

Further, the second adder 110 causes (MH)
The multiplication result (mh4) stored in the second cumulative addition register 111 (AH) is added to the value (sh3) stored in the second cumulative addition register 111 (AH).
Write back to H) (sh4).

In the third adder 112, the first selector 2
The addition result of the value output by 11 (s13) and the value output by the second cumulative addition register 111 (AH) (sh3) is calculated and output to the second selector 212. The second selector 212 selects the input from the third adder 112 and outputs it to the output register 113 (S). Output terminal 114
The output data (s2) stored in the output register 113 (S) at the previous time is output to (Z).

At time 6, the third adder 112 makes the first
The value (sl4) output by the selector 211 and the addition result (s4) are obtained and output to the second selector 212. The second selector 212 selects the input from the third adder 112 and outputs it to the output register 113 (S). The output terminal 114 (Z) of the accumulator 200 outputs the output data (s) stored in the output register 113 (S) at the previous time.
3) is output.

At time 7, the output data (s4) stored in the output register 113 at time 6 is output from the output terminal 108 to the outside of the cumulative adder 200, and the process ends.

In this way, the cumulative addition process of the input data up to the fourth set is completed from time 0 to time 7. Here, an example is shown in which the cumulative addition processing is executed for up to the fourth set of input data, but in reality, data is sequentially input to the first input terminal 101 (X) and the second input terminal 102 (Y). It is input and the cumulative addition process is executed.

In particular, the cumulative adder 2 according to the second embodiment
00, the first selector 211 and the second selector 2
By selecting 12, it is possible to perform multiplication and cumulative addition processing on the upper side and the lower side in one cycle (every time t) as shown in FIG.
The sets can be cumulatively added at the same time. Here, if either one of the data is exchanged, it is possible to perform multiplication and cumulative addition on the upper side and the lower side.

As described above, the cumulative adder 200 according to the second embodiment to which the present invention is applied includes the first selector 211 for selecting the outputs of the first cumulative addition register 107 and the carry register 108, The first cumulative addition register 107, the second cumulative addition register 111, and the second selector 212 that selects the output of the third adder 112 are added, and the input to the third adder 112 is carried by the carry register 108. And the output value from the cumulative adder 200 is selected from the outputs of the first cumulative addition register 107, the second cumulative addition register 111, and the third adder 112. Since the configuration is selectable, not only data having a data length of 32 bits but also two sets of 16-bit data can be cumulatively added at the same time. It becomes possible to output a sum of the cumulative addition value of the cumulative addition value and the lower side of the upper side during the force.

If the first selector 211 is set to always select the output from the carry register 108 and the second selector 212 is always to select the output from the third adder 112, the first selector 211 is set. Cumulative adder 1 according to the embodiment
Similar to 00, a 32-bit cumulative addition mode can be realized, and 64-bit addition processing can be performed at high speed to speed up the cumulative adder 200 as a whole.

In the second embodiment, the multiplication process is performed on the upper side and the lower side, but either one of the data may be exchanged to perform multiplication and cumulative addition on the upper side and the lower side. Needless to say.

Further, in each of the above-mentioned embodiments, the cumulative adder in which the data having the data length of 32 bits is input has been described, but it can be applied to the data of any bit length such as 16 bits or 8 bits. Needless to say.

Further, in each of the above-mentioned embodiments, the output data from the cumulative adders 100 and 200 is 64-bit data, but it is also possible to output data of an arbitrary bit length, for example 32 bits. For example, data having a shorter data length than each of the above-described embodiments may be selected and output.

Also, in each of the above-mentioned embodiments, the division of the multiplier output is divided into upper and lower divisions, but it is not limited to this, and it is also possible to divide into three or more divisions. . For example, a third addition processing unit is further provided in parallel with the second addition processing unit 116, and a carry register that holds a carry bit of the third addition processing unit is provided, and the same operation as that in each of the above-described embodiments is performed. You may allow it. By doing so, the effects of the above-described embodiments can be further enhanced.

Further, in each of the above-described embodiments, the pipeline multiplier 103 having the pipeline register 104 therein is used as the multiplier to enable the input of each cycle data and the output of the multiplication data. It goes without saying that any multiplier may be used as long as it can divide the output of the multiplier.

Further, it is needless to say that the number of registers, arithmetic circuits, selectors, type connection states, etc. constituting the above-mentioned cumulative adder are not limited to those in the above-mentioned respective embodiments, and it is needless to say that the arithmetic circuits constituting DSP etc. It may be a part.

Furthermore, in each of the above-mentioned embodiments, although it is applied to the cumulative adder, the accumulation by the selection means is prohibited,
Alternatively, it is possible to execute only the addition process by changing the data input. Further, although the adder of each of the above-described embodiments performs only the addition process, it is also possible to execute a subtraction process (for example, complement addition) that adds negative data to the output of the multiplier. Therefore, the name is not limited to the cumulative adder, and may be appropriately changed to an adder, a subtracter, or the like within the scope of the technical idea of the present invention.

[0152]

In the cumulative adder according to the present invention, the output of the multiplier is divided into a plurality of parts, and a plurality of addition processing parts for executing addition processing for each output of the divided multipliers, and a plurality of addition processing parts. Since the output means is configured to be connected and output as a cumulative addition result, the addition processing can be realized at high speed by a plurality of addition processing units, and the speed of the entire cumulative adder can be increased. You can

Further, in the cumulative adder according to the present invention, the addition processing is performed by the first addition processing for the addition processing on the lower side of the multiplier output.
And the second addition processing unit that executes the higher-order addition processing of the multiplier output, and the carry bit generated in the addition processing of the first addition processing unit is added to the second addition processing unit after a predetermined time. Since it is configured to be added to the addition processing unit, the addition processing can be divided into the upper side and the lower side and executed simultaneously in one cycle, and the addition processing time can be halved. Therefore, it is possible to eliminate the drawback that the rate is limited by the adder, and it is possible to increase the speed of the cumulative adder as a whole.

Further, by adopting a structure provided with a selecting means for selecting the addition result, it is possible to interchange the data and perform multiplication and cumulative addition on the upper side and the lower side, and to simultaneously generate two sets of data having a plurality of bit lengths. Can be cumulatively added. Therefore, at the time of output, it is possible to output the sum of the cumulative addition value on the upper side and the cumulative addition value on the lower side.

Since it is possible to realize a high-speed cumulative adder having high calculation accuracy as described above, it is suitable for application to a DSP or the like.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a cumulative adder according to a first embodiment to which the present invention is applied.

FIG. 2 is a timing chart for explaining the operation of the cumulative adder.

FIG. 3 is a configuration diagram of a cumulative adder according to a second embodiment to which the present invention is applied.

FIG. 4 is a timing chart for explaining the operation of the cumulative adder.

FIG. 5 is a configuration diagram of a conventional cumulative adder.

FIG. 6 is a timing chart for explaining the operation of a conventional cumulative adder.

[Explanation of symbols]

100,200 Cumulative adder, 103 Multiplier, 104
Pipeline register, 105 first multiplication register, 106 first adder, 107 first cumulative addition register, 108 carry register, 109 second multiplication register, 110 second adder, 111 second cumulative addition Register, 112 third adder, 113 output register, 115 first addition processing unit, 116 second addition processing unit, 211 first selector, 212 second selector

Claims (9)

[Claims] 1. A cumulative adder that inputs data for each unit time and executes cumulative addition processing, wherein: a multiplier and an output of the multiplier are divided into a plurality of pieces, and the output is added for each divided output of the multiplier. A cumulative adder comprising: a plurality of addition processing units for executing processing; and an output unit for connecting outputs of the plurality of addition processing units and outputting as a cumulative addition result. 2. The addition processing unit includes a first addition processing unit that executes addition processing on a lower side of the multiplier output, and a second addition processing unit that executes addition processing on an upper side of the multiplier output. And a means for adding a carry bit generated in the addition processing of the first addition processing unit to the second addition processing unit after a predetermined time, the second addition processing unit based on the carry bit. The cumulative adder according to claim 1, wherein the cumulative adder is configured to perform addition processing. 3. The output means includes a third adder for adding the output of the second addition processing unit and the carry bit, and the data output from the third adder to the upper side. 3. The cumulative adder according to claim 2, further comprising: an output register for connecting and holding the data output from the first addition processing unit to a lower side. 4. The first addition processing unit, a first register holding a lower side of an output of the multiplier, a first adder, and holding an output of the first adder. A first accumulation register, the first adder adds an output of the first register and an output of the first accumulation register, and the second addition processing unit includes: A second register for holding the upper side of the output of the multiplier; a second adder; and a second accumulation register for holding the output of the second adder, the second adder Is a carry register for adding the output of the second register and the output of the second accumulation register, and further holding a most significant 1 bit of the addition result of the first adder as a carry bit. The carry bit stored in the carry register is stored in the second register after a unit time. Cumulative adder according to claim 2 or 3, characterized by being configured to add to the adder. 5. A cumulative adder that inputs data for each unit time and executes a cumulative addition process, comprising: a multiplier, a first register that holds the lower side of the output of the multiplier, and a higher side. A second register, a first adder, and the first accumulation register that holds the output of the first adder, wherein the first adder is the first register of the first register. An output and an output of the first accumulation register are added, and further, a second adder, and a second accumulation register that holds an output of the second adder, Adder adds the output of the second register and the output of the second accumulation register, and outputs the highest of the output of the second accumulation register and the output of the first adder. A third adder for adding the bit and an output of the third adder to the upper side, And an output register for holding an output of the adding register coupled to the lower side, the first of said most significant bit of the output of the adder second
To the third adder and the output of the first adder excluding the most significant bit to the first accumulation register, and the second adder is the second adder. A cumulative adder configured to perform addition processing on the most significant bit of the output of the second register, the output of the second accumulation register, and the output of the first adder. 6. A cumulative adder characterized by further comprising selection means for selecting an addition result by the cumulative adder according to any one of claims 1 to 5. 7. The cumulative addition according to claim 1, wherein the cumulative adder is an adder that prevents cumulative addition processing and executes only addition processing on a multiplier output. vessel. 8. The cumulative adder according to claim 1, wherein the cumulative adder executes subtraction processing for adding negative data to a multiplier output. 9. The cumulative adder according to claim 1, wherein the multiplier is a pipeline multiplier capable of inputting data and outputting multiplication data for each cycle.