JPH0918465A - Radio communication equipment - Google Patents

Abstract

PURPOSE: To establish the word synchronization with high probability by outputting a word synchronizing detection signal when the number of error is within the allowable number of error determined by an error setting device and outputting a pseudo word synchronizing detection signal based on the number of reception bit when the number is except the allowable number of error. CONSTITUTION: A control circuit 15 sets an allowable number of error to '0' when measured reception electric field intensity is a reference value A or more and decides whether the value is the one that 2dB is subtracted from A or more or not if the intensity is less than A If the intensity is (A-2) or more, the allowable number of error is set to '1', and if the intensity is less than (A-2), whether the value is the one that 4dB is subtracted from A or more or not is decided. If the intensity is (A-4) or more, the allowable number of error is set to '2', and if the intensity is less than (A-4), whether the value is the one that 6dB is subtracted from A or more or not is decided. After this allowable value of error setting processing is performed, the circuit 15 compares the data of word synchronizing phase memory 16 and the fewest number of error information. When the number of error is within the allowable number of error, a word synchronizing signal is outputted and when the number is except the allowable number of error, a pseudo word synchronizing detection signal is outputted based on the number of reception bit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a predetermined word rate,
The present invention relates to a wireless communication device such as a cordless phone, a cellular car phone and a mobile phone, which is capable of receiving a data signal transmitted at a bit rate and containing a predetermined synchronization character.

[0002]

2. Description of the Related Art Conventionally, in a cellular communication system, a baseband data signal (forward control channel message) for performing control such as channel change is transmitted from a wireless base station and received by a wireless communication device. Then, each process is performed.
By the way, this baseband data signal has a word synchronization character and is transmitted at a predetermined word rate and bit rate. The wireless communication device first detects the word synchronization character and restores the word synchronization. There is a need. Therefore, as disclosed in, for example, Japanese Unexamined Patent Publication No. 52-115609, a data signal recovery circuit is provided, and a word synchronization signal is given to a control circuit for data processing upon detection of this word synchronization character. .

[0003]

By the way, since an error correction code is not normally included in the word synchronization character, burst error due to fading or the like or loss of word synchronization due to random error in a weak electric field region is likely to occur. Here, a random error in a weak electric field region is a problem in practical use.

Since the sync signal recovery circuit compares a predetermined word sync pattern with the word sync character received by the wireless communication device and attempts to match them, when random error occurs, the word sync cannot be established. In such a case, even if the error of the data is within the correctable range, the word synchronization cannot be determined, so that the analysis processing of the data is not performed, and if the data is voice data, it becomes a silent state.

[0005]

A wireless communication apparatus of the present invention compares error setting means for setting an allowable error number of a word synchronization character with input data and a word synchronization pattern, and the error number is determined by the error setting means. The synchronization recovery means outputs the word synchronization detection signal when the number of allowable errors is determined by the above, and outputs the pseudo word synchronization detection signal based on the number of received bits when the number of errors is outside the allowable number of errors.

[0006]

Since the present invention is configured as described above, word synchronization can be established with high probability even if there is an error in the word synchronization character.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. The embodiment described here shows the case where the forward control channel (FOCC) is applied to the present invention. In this forward control channel, a forward control channel message (baseband data signal) is transmitted from the wireless base station, and the mobile station (wireless communication device) receiving this message performs various processes such as registration and channel change according to the message. To do.

FIG. 1 is a diagram showing a typical format of such a forward control channel message. This message consists of a bit sync field, a word sync field, and a data message. More specifically, the bit synchronization field is a 10-bit field and 1s and 0s are alternately arranged (so-called dotting), as shown in FIG. Next, as shown in FIG. 3, the word synchronization field is an 11-bit field and has a bit arrangement that is unlikely to occur in a voice message. For example, in the United States, as shown in FIG.
The word synchronization character "1100010010" is set. Next, the data message includes 40-bit data messages A and B each including an error correction code, and the data messages are alternately repeated 5 times (A1 to A1 respectively). Repeating the data message 5 times each in this way means that when there is a difference between the received data, the validity of the data is determined by a match of 3/5 or more, that is, by a majority vote. This is for judging.

Although not shown in FIGS. 1 to 3, in the bit synchronization field, the word synchronization field and each data message, 1 is set for every 10 bits.
Bit Busy-Idle bit has been added. The busy-idle bit is for notifying the mobile station of the acceptance state of the radio base station which is the transmission source of the message, that is, the idle state of the reverse control channel (RECC). Thus, the bit sync field, word sync field and data message will actually consist of 11 bits, 12 bits and 44 bits, respectively. Then, the message shown in FIG. 1 is subjected to the well-known Manchester code in the United States, for example, and is transferred at a rate of 10 kilobits / second. However, in order to simplify the description, the busy-idle bit will be omitted in the following description.

Next, FIG. 4 shows a radio communication device as a mobile station in a cellular system, wherein (1) and (2) are a transmission unit and a reception unit, a transmission / reception duplexer (3), a control signal, and voice coding. TDMA for time division demultiplexing of signals and synchronization signals
It is connected to the circuit (4) and realizes basic wireless communication between the subscriber and a wireless base station (not shown). A radio link connection for communicating with a mobile telephone switching center (not shown) is formed through a radio base station, and an interface with a public telephone communication network is established through the radio link connection. Transmitter (1) is π /
It consists of a 4-shift QPSK modulator (5) and a highly efficient linear power amplifier (6). The receiving section (2) includes a first receiving circuit (7) connected to the transmission / reception duplexer (3), a second receiving circuit (9) connected to the antenna (8), and a demodulator (1).
0), the demodulator (10) has a circuit for detecting the received electric field strength based on the received signals of the first receiving circuit (7) and the second receiving circuit (9), and the first receiving circuit It also has a diversity circuit that switches the outputs of (1) and the second receiving circuit (9) at a predetermined timing to select the one with the better reception state. (11) is a synthesizer circuit,
A channel is changed by applying a carrier wave to the transmitting unit (1) and a local oscillation signal to the first receiving circuit (7) and the second receiving circuit (9) of the receiving unit (2), and changing these frequencies. It will be. (12) is a voice coder / decoder circuit, which not only decodes a voice signal but also has an error correction function for reducing the influence of fading or the like. (1
3) (14) are a microphone and a speaker, which are connected to the voice codec (12). (15) is a control circuit composed of a 16-bit microprocessor and an ASIC, and includes a TDMA circuit (4) and a word synchronous phase memory (1
6), it is connected to a display device (17) for displaying a telephone number, a buzzer (18) for making a ring tone when an incoming call arrives, and a key circuit (19). This control circuit (15)
Data from the TDMA circuit (4) is input to perform word synchronization recovery processing. In this processing, error information corresponding to the delay or advance time of the received word synchronization with respect to the word synchronization predicted position is word synchronization. Phase memory (1
Store in 6). Also, it analyzes a message from the wireless base station and controls various functions as a telephone device such as a wireless line control and a transmission output control.

Next, FIGS. 5 to 8 show control circuits (1) for receiving the forward control channel message.
5) is a flow chart of the program written in FIG. 5, FIG. 5 shows an outline of the whole operation, FIG. 6 shows an allowable error number setting process by the received electric field strength of FIG. 5, and FIG. 7 shows an error information memory of FIG. It is a flow chart which showed processing in detail.

In FIG. 5, a control circuit (15) for the mobile station.
First sets the receiving channel (S1), and TDM
Reception of data from the A circuit (4) is started (S2).
The received serial data is sequentially transferred to the 16-bit shift register, and the input data is shifted bit by bit (S3). The shift register is used for synchronization confirmation, and the input data is sequentially stored in separate memories for data processing. At the initial stage of reception, since the synchronization is not fixed, the data in the shift register is compared with the word synchronization pattern (at this time, the 0th to 9th bits of the shift register are always compared with the word synchronization pattern. The data is received until the word synchronization character is detected without error (S4, S5). If the word sync character is detected without error, the reference value A of the received field strength (RSSI) for determining the allowable number of errors in the word sync detection is set to -115 dB (S
6). This is -113 in the US cellular system.
Since it is determined that the word sync character must be detected without error with the electric field strength of dB, the reference value is set to -115 dB, which is lower by 2 dB.
After that, the control circuit (15) sets the synchronization confirmation flag, records the position of the synchronization confirmation bit for the data in the data processing memory in the internal register (S7), and presets the built-in synchronization wait counter ( S8),
The counting of the synchronization waiting counter is started (S9). This synchronization wait counter counts the number of bits of input data after the synchronization position. The forward control channel message is 42 in total as described above.
Since it is 1 bit (excluding the busy-idle bit), the next time, logically, the synchronization position will be reached after counting 421, but 423 is preset in the synchronization waiting counter in consideration of jitter and the like.

Next, the processing of steps 2 and 3 is performed until the synchronization waiting counter counts over, and the data processing of the data message is performed (S4, 10, 11).
In the data processing of the data message, the data after the synchronization confirmation bit is read from the memory for data processing and the data processing is sequentially performed. When the synchronization waiting counter is counting over (Y in S10), the control circuit (15) measures the reception electric field strength of the reception channel,
The allowable value of the error information of the word synchronization character is set based on the received electric field strength (S12, 13).

This error allowable value setting process will be described with reference to FIG. First, the control circuit (15) determines whether or not the measured received electric field strength is equal to or higher than the reference value A (S24). If it is the reference value A or more, the allowable error count is set to "0" (S2
5) If it is less than the reference value A, it is determined whether the value is equal to or more than the value obtained by subtracting 2 dB from the reference value A (S26). If (A-
If 2 or more, the allowable error number is set to "1" (S2
7), if less than (A-2), it is determined whether the value is equal to or more than the value obtained by subtracting 4 dB from the reference value A (S28). If (A-4) or more, the allowable number of errors is set to "2" (S29),
If it is less than (A-4), it is determined whether the value is equal to or more than the value obtained by subtracting 6 dB from the reference value A (S30). If (A-6) or more, the allowable error count is set to "3" (S31), and (A-
If less than 6), the allowable number of errors is set to "4" (S
32).

After this error tolerance setting process, the control circuit (1
In 5), the detection processing of the number of error information corresponding to the phase difference of the received data is performed (S14).

This detection process will be described with reference to FIG. First, the control circuit (15) sets the number of shift stages of the word synchronization pattern for the data set in the shift register in order to detect the coincidence of the synchronization pattern from the data set in the shift register. (Set) (S33), the data of the shift register and the word synchronization pattern are EORed (S34). The error (EOR result error is "1") obtained as a result of this is counted (S35), and the synchronization word prediction position (42 after the synchronization is determined).
The number of error information is stored in the area of the word synchronization phase memory (16) corresponding to the difference (phase difference) from the first bit (S3).
6). After that, the word synchronization pattern is shifted one step (S3
7) S34 to S37 until the set number of shift steps is reached
Is repeated (S38). The phase difference is "-3", "-"
There are five types, "2", "-1", "0", "1", and "2" (see FIG. 8).

After this detection processing, the control circuit (15) sorts the data of the word synchronous phase memory (16) in ascending order of error information (S15), the smallest number of error information and the allowable error value. A comparison is made with the error tolerance determined by the setting process (S13) (S1).
6). The word-synchronous phase memory (16) is sorted by the well-known technique without changing the memory area in general and by controlling the pointer corresponding to the area to perform the apparent sorting. Further, according to such a method, the sorting is performed in the order of the smallest amount of error information, and when the number of error information is the same as a result of the execution, the sorting is performed in the order of being closer to the synchronization prediction position (smaller phase difference). There is.

If the result of the comparison is within the error tolerance, the bit position of the shift register corresponding to the phase difference of the pointer 0 of the word synchronization phase memory (16) is set as the synchronization confirmation bit position, and the error tolerance is exceeded. If so, the synchronization predicted position (phase difference 0) is set as the synchronization fixed bit position (S17,
21). When the sync bit position is fixed, for example, when b2 is set as the sync bit position in the state of FIG. 8, since the 2-bit data message has already been received after the sync is fixed, in step S8, A value obtained by subtracting 2 from 423 is preset in the waiting counter. In this way, the subtraction process calculates the number of bits of the data message already received in the shift register according to the sync bit position, and presets a value obtained by subtracting the value from 423. . After this, the process proceeds to step S9 to start counting.

By the way, if it is judged within the error allowable value by the judgment processing of step S16 as to whether it is within the error allowable value or not, the value obtained by subtracting 2 from A at that time is taken as A, and the error allowable value is exceeded. If it is determined that the value is A, the value obtained by adding 2 to A at that time is set as A (S19, 2).
2). This is for setting the optimum allowable number of errors in the receiving environment by this addition and subtraction. That is, for example, A
Is -113 dB and the RSSI is -117 dB, the error allowable number is set to 2 in FIG. 6, and when the error of the word synchronization character is 2, it is within the error allowable number, but the actual error is It is preferable that the number is 1 and the allowable number of errors is also 1. Next time, A is set to −115 dB, and when the RSSI is also −117 dB, the allowable number of errors is set to 1. Further, in the above example, when the error of the word synchronization character is 3, next time, A is set to −111 dB,
Similarly, when RSSI is -117 dB, the allowable error number is 3
And so on. In this embodiment, -115 dB
In this case, the allowable number of errors is set to 0 in the optimum reception environment, and the allowable number of errors of each RSSI is set on the basis of this, and A is not set to a value smaller than -115 dB (S18). When A is set to −109 dB, the allowable error number is 3 if the RSSI is −115 dB.
Even in such a case, if the error number of the word synchronization character exceeds 3, it is determined that it is a special reception environment, for example, an environment where strong interference is intermittently generated from the outside, The synchronization confirmation flag is released (S20, 23).

That is, in the present invention, since the error correction code is added to the data message, even if the number of errors of the word synchronization character is outside the allowable number of errors, the synchronization prediction position is simulated. Although the data message is processed as the synchronization confirmation bit position, it is determined that the error correction is impossible in the special reception environment described above, and the synchronization confirmation flag is cleared.

When the synchronization confirmation flag is released, the received data after the last data message after the synchronization is confirmed is cleared from the data memory in step S2, and the data is received until the synchronization confirmation flag is set next. The data is not stored in the data memory.

[0022]

Since the present invention is configured as described above, word synchronization can be established with a high probability even if there is an error in the word synchronization character, and the data message can be rescued.

[Brief description of the drawings]

FIG. 1 is a diagram showing a typical format of a forward control channel message.

FIG. 2 is a diagram showing a specific example of a bit synchronization field.

FIG. 3 is a diagram showing a specific example of a word synchronization field.

FIG. 4 is a block diagram of a wireless communication device of the present invention.

FIG. 5 is a flowchart of a program relating to reception of a forward control channel message written in the control circuit of the wireless communication layer of the present invention.

6 is a flowchart showing a process of setting an allowable error number based on a received electric field strength in the flowchart of FIG.

FIG. 7 is a flowchart showing error information memory processing in the flowchart of FIG.

FIG. 8 is an explanatory diagram related to a method for detecting a word synchronization character.

[Explanation of symbols]

 1 Transmitter 2 Receiver 4 TDMA Circuit 12 Voice Codec 15 Control Circuit 16 Word Synchronous Phase Memory

Claims (1)

[Claims] 1. In an apparatus for recovering word synchronization of serial data including a predetermined word synchronization character to receive a data message, error setting means for setting an allowable error number of the word synchronization character, input data and word synchronization. When the number of errors is within the allowable number of errors determined by the error setting means, a word synchronization detection signal is output, and when the number of errors is outside the allowable number of errors, a pseudo word synchronization detection signal is generated based on the number of received bits. A wireless communication device comprising: a synchronization recovery means for outputting.