JPH0918337A - Frequency synthesizer - Google Patents

Abstract

PURPOSE: To reduce the number of times of setting a frequency division ratio and to reduce the processing loads of an external control circuit such as a microcomputer or the like by providing a data transfer means for repeatedly transferring frequency division ratio data from a frequency division ratio data holding means to a programmable divider. CONSTITUTION: The three sets of the frequency division ratio data DNA DNC are set to the respective registers 31-33 of a frequency division ratio data holding mechanism 3A by data write. A transfer pulse generator 41 for constituting a data transfer mechanism 4 generates a reception frame pulse FR, a transmission frame pulse FT and a monitor frame pulse FM respectively corresponding to reception, transmission and monitor reception at the slot time within one TDMA frame specified beforehand by a slot number specifying signal SS. Then, the stored data DNA DNC of the registers 31-33 are transferred through a multiplexer 42 to the programmable divider 1 in synchronism with the respective pulses FR-FM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency synthesizer, and more particularly to a frequency synthesizer used in a cell type TDMA (time division multiple access) radio telephone (hereinafter, digital cellular telephone).

[0002]

2. Description of the Related Art Conventionally, a frequency synthesizer of this type for generating a transmission / reception frequency of a general digital cellular telephone has a register for storing frequency division ratio data of a programmable divider, and the frequency division data is externally supplied every time the frequency is changed. Was reset and switched to a predetermined frequency.

Referring to FIG. 3, which shows a block diagram of a conventional frequency synthesizer, in this conventional frequency synthesizer, a frequency-divided signal fd obtained by dividing a frequency fx of an oscillation signal VO by a set frequency division ratio and a reference frequency fr are phased. A synthesizer unit 100 for comparing and outputting a phase difference signal PC, a loop filter 200 for smoothing the phase difference signal PC and outputting a control signal DC, and a frequency fx in response to control of the control signal DC.
Voltage controlled oscillator 3 that outputs an oscillation signal VO
00.

The synthesizer section 100 divides the frequency fx of the oscillation signal VO by a set frequency division ratio N to obtain a frequency fd (= f
(x / N) frequency-divided signal Fd (= fx / N) and a programmable divider 1 with a variable frequency division ratio, and a reference frequency fr.
And the frequency division frequency fd are compared with each other to output a phase difference signal PC, and a frequency divider including a register 31 in which a frequency division ratio N corresponding to designation of the frequency division ratio data DN from the outside is set. The ratio data holding mechanism 3 is provided.

Next, referring to FIG. 3, the operation of the conventional frequency synthesizer will be described. First, in response to the supply of the write pulse W, the division ratio data DN is stored in the register 31.
When set to, the register 31 supplies the frequency division ratio setting data DN to the programmable divider 1. The programmable divider 1 is set to the division ratio N corresponding to the data DN, divides the frequency fx of the input oscillation signal VO by N, and supplies the divided signal Fd of the frequency fx / N to the phase comparator 2.
The phase comparator 2 compares the phases of the divided signal Fd and the reference frequency fr and outputs a phase difference signal PC, and the loop filter 2
Supply to 00. The loop filter 200 has a phase difference signal P
The high frequency component of C is removed and smoothed, and the control signal DC is supplied to the voltage controlled oscillator 300. The voltage controlled oscillator 300 outputs an oscillation signal VO whose frequency fx is controlled in response to the voltage of the control signal DC.

In a digital cellular telephone, each frequency of transmission and reception of a communication channel (hereinafter referred to as transmission / reception frequency)
However, the difference between the transmission and reception frequencies assigned to a specific call link is set to a constant value. Further, because of the TDMA system, a frame is used as a transmission / reception frequency, and the time is divided into a plurality of time slots so that the same frequency can be used by a plurality of users.

Further, the digital cellular telephone has a monitor function for receiving the specific frequency of the adjacent cell for each call frame and measuring the electric field strength thereof during the call so that the call link is maintained even when the caller moves. When the electric field strength (reception strength) of the reception signal of the communication channel in use decreases and the reception strength of the frequency of the adjacent cell to be monitored increases, the transmission / reception frequency during communication is switched to the adjacent cell side.

Referring to FIG. 4 showing a time chart for explaining the monitor function and the switching operation, the horizontal axis represents time, the transmission frequency corresponding to the reception frequency fR0 is fX0, the transmission frequency corresponding to the reception frequency fR1 is fX1, and the reception frequency is fX1. Frequency f
The transmission frequency corresponding to R2 is fX2 ... And the frequency difference between them is a constant frequency. In this figure fR
0, fR1, fX0, fX1, and fM0 are specific service cells, and other fR2, fR3, fX2, fX3, and fM1 are frequencies belonging to other cells.

Also, the initial reception frequency is fR0, the transmission frequency is fX0, and the transmission / reception time slot 3 is used. The frequency information fR2, fR3, fX3, fM1 etc. of the adjacent cells are designated in advance via the communication link, and as a result of the monitoring process of the frequency fM1, the intensity thereof increases and if it is judged that the adjacent cells have reached the transmission / reception frequency. Is switched to the frequency on the adjacent cell side, reception at fR2, transmission at fX2, and monitoring at fM0 are started.

That is, in a digital cellular telephone,
As described above, during one frame period during a call, first, the "reception" operation at the reception frequency of the communication channel, the second, the "transmission" operation at the transmission frequency of the communication channel, and the third, the monitoring of the specific frequency of the adjacent cell. Is repeated, and the "monitor reception" operation is repeated, and the frequency division ratio setting for the programmable divider 1 of the frequency synthesizer for transmission / reception frequency setting is set to 3 in order to set 3 kinds of frequencies corresponding to these 3 kinds of operations. I have to do it once.

For example, in a system having a channel structure in which a 1 TDMA transmission / reception frame time interval is 5 ms and transmission / reception time slots are 8 each, if the communication time is 2 minutes, even if there is no switching of transmission / reception frequency due to cell movement, one frame period Since the transmission / reception frequency is switched three times during this period, it is necessary to switch the frequency division ratio of the programmable divider 1 72000 times during the call period.

[0012]

The above-mentioned conventional frequency synthesizer, when applied to a digital cellular telephone, repeats reception, transmission, and monitor reception for each frame, so three types of operations corresponding to these three types of operations are performed. It is necessary to repeatedly set the frequency division ratio data of the frequency synthesizer to the frequency synthesizer, and the processing load of the external control circuit such as a microcomputer for setting the frequency division ratio data for the frequency synthesizer becomes extremely heavy. .

[0013]

SUMMARY OF THE INVENTION A frequency synthesizer of the present invention comprises a programmable divider that divides an input oscillation signal at a set frequency division ratio to generate a frequency division signal and a phase comparison between the frequency division signal and a reference signal. Synthesizer circuit including a phase comparison circuit for outputting a phase difference signal, a loop filter for smoothing the phase difference signal and outputting a control signal, and a frequency controlled in response to control of the control signal In a frequency synthesizer including a voltage controlled oscillator that outputs an oscillation signal, the synthesizer circuit includes first, second, and third frequency division ratio data corresponding to predetermined first, second, and third frequency division ratios. And frequency division ratio data holding means for respectively storing the frequency division ratio data, and the frequency division ratio data for the first to third frequency division ratio data at the slot time designated by the slot number designation signal in response to the clock supply. And a lifting means and a data transfer means for repeating transferred to the programmable divider.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Next, referring to FIG. 1, which is a block diagram in which components common to those of FIG. 3 are designated by common reference characters / numerals, the embodiment of this invention shown in FIG. The frequency synthesizer of the present invention is similar to the conventional loop filter 200.
In addition to the voltage-controlled oscillator 300, instead of the synthesizer section 100, a frequency division ratio data holding mechanism 3A including a plurality of registers corresponding to three frequency division ratios corresponding to reception, transmission, and monitor reception, and a clock CK. A synthesizer unit including a data transfer mechanism 4 that repeatedly transfers the three sets of frequency division ratio data from the frequency division ratio data holding mechanism 3A to the programmable divider 1 at the slot time corresponding to the designation of the slot number designation signal SS in response to the supply. With 100A.

In addition to the programmable divider 1 and the phase comparator 2 which are common to the conventional ones, the synthesizer section 100A includes frequency division ratio data DNA, DNB, corresponding to each of reception, transmission and monitor reception set from the outside. Frequency division ratio data holding mechanism 3A having registers 31 to 33 for respectively storing the DNC, and reception, transmission, and monitor reception at the slot time within the 1TDMA frame designated by the transmission / reception slot number designation signal in response to the supply of the clock CK. Of the transfer pulse generator 41 for generating the frame pulses FR, FT, FM corresponding to each of the frame pulses FR, FT, FM, and the division ratio data DNA, D in response to the supply of each of the frame pulses FR, FT, FM.
And a data transfer mechanism 4 including a multiplexer 42 that selectively outputs one of NB and DNC.

Next, the operation of the present embodiment will be described with reference to FIG. 1. First, three sets of frequency division ratio data D for each of the registers 31 to 33 of the frequency division ratio data holding mechanism 3A.
It is set by writing data to NA, DNB, and DNC. In this writing, an external control circuit such as a microcomputer determines the validity of the write enable signal EW generated by the transfer pulse generator 41, and when it is valid, the registers 31, 3 are set.
The write pulses WA, WB, and WC are performed in synchronization with each of Nos. 2 and 33. Setting data DNA, DN
B and DNC are retained unless overwritten. The transfer pulse generator 41, at the slot time in the 1TDMA frame previously designated by the slot number designation signal SS,
The reception frame pulse FR, the transmission frame pulse FT, and the monitor frame pulse FM are generated, and the data 42, DNB, and DNC stored in the registers 31 to 33 are synchronized with the respective pulses FR, FT, and FM by the multiplexer 42.
To the programmable divider 1 via.

In the same manner as in the conventional case, the 1TDMA frame is divided into the 0th
In the system configured by the seventh 8 time slots, the transmission / reception frame interval is 3, and the monitor frame position is the intermediate position of the transmission / reception slot, the above data transfer when the reception slot position is set to 0 by the transmission / reception slot number designation signal SS. Referring also to FIG. 2 showing the operation in a time chart, the transfer pulse generator 41 first receives the reception frame pulse F in the 0th slot indicated by the system clock CK.
R is generated, and the division ratio data DNA corresponding to the reception that has been set up to that point at the trailing edge of the pulse FR is transmitted to the data D corresponding to the transmission.
Switch to NB. Next, the transmission frame pulse FT is generated in the third slot, and the frequency division ratio data DNB corresponding to the transmission, which has been set until then, is switched to the data DNC corresponding to the monitor reception at the trailing edge of the pulse FT. Next, the monitor frame pulse FM is generated in the fifth slot, and the frequency division ratio data DN corresponding to the monitor reception that has been set up to then is set at the trailing edge of the pulse FM.
The C is switched to the data DNA corresponding to the reception.

As a result, the external control circuit sets three frequency division ratio data DNA, DNB, DNC corresponding to respective frequencies of reception, transmission and monitor reception for the registers 31 to 33 of the frequency division ratio holding mechanism 3A. And these data DN
A, DNB, and DNC are sequentially and repeatedly transferred to the programmable divider 1 in synchronization with the system clock CK, and use the original stored data unless these data DNA, DNB, and DNC are updated.

[0019]

As described above, in the frequency synthesizer of the present invention, the frequency division ratio data holding means for storing the three sets of frequency division ratio data respectively, and the frequency division ratio data at the designated slot time are divided. Since the data transfer means for repeatedly transferring from the ratio data holding means to the programmable divider is provided, while the same transmission / reception frequency and the same monitor frequency are being used, a portion corresponding to each frequency of reception, transmission, and monitor reception in one TDMA frame is provided. If it is not necessary to newly set the frequency ratio data, and if it is not necessary to switch the transmission / reception frequency such as staying in the same cell during the call time, the setting of the frequency division ratio data becomes unnecessary regardless of the call time. This has the effect of significantly reducing the processing load of the external control circuit that performs the setting processing of the division ratio data.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a frequency synthesizer of the present invention.

FIG. 2 is a time chart showing an example of the operation of the frequency synthesizer of this embodiment.

FIG. 3 is a block diagram showing an example of a conventional frequency synthesizer.

FIG. 4 is a time chart showing frequencies and operations of transmission / reception and monitor reception of the digital cellular telephone.

[Explanation of symbols]

 1 Programmable Divider 2 Phase Comparator 3, 3A Dividing Ratio Data Holding Mechanism 4 Data Transfer Mechanism 31-33 Register 41 Transfer Pulse Generator 42 Multiplexer

Claims (4)

[Claims] 1. A programmable divider that divides an input oscillation signal by a set division ratio to generate a divided signal, and a phase comparison circuit that compares the phase of the divided signal with a reference signal and outputs a phase difference signal. A loop filter that smoothes the phase difference signal and outputs a control signal, and a voltage controlled oscillator that outputs the oscillation signal whose frequency is controlled in response to control of the control signal. In the frequency synthesizer, the synthesizer circuit includes predetermined first, second, and third
Frequency division ratio data holding means for respectively storing the first, second, and third frequency division ratio data corresponding to the frequency division ratio, and at the slot time designated by the slot number designation signal in response to the clock supply, A frequency synthesizer, comprising: data transfer means for repeatedly transferring first to third frequency division ratio data from the frequency division ratio data holding means to the programmable divider. 2. The frequency division ratio data holding means comprises:
The frequency synthesizer according to claim 1, further comprising: first to third registers for respectively storing third frequency division ratio data. 3. A transfer pulse generation circuit, wherein said data transfer means generates first to third frame pulses corresponding to each of reception, transmission and monitor reception at said slot time in response to supply of said clock. And a multiplexer that selectively outputs one of the first to third frequency division ratio data in response to the supply of the first to third frame pulses, respectively. Frequency synthesizer. 4. The first to third frame pulses are generated by the transfer pulse generation circuit during the periods in which the first to third frame pulses are not generated.
4. The frequency synthesizer according to claim 3, wherein a write permission signal is generated to permit writing of the third frequency division ratio data.