JPH09181644A - Synchronizing signal generator for spread spectrum signal and spread spectrum communication equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve communication efficiency by generating quickly a signal corresponding to a period of a correlation peak signal outputted from a correlation detector. SOLUTION: A chip length counter 13 provides an output of a bit pattern signal of a pseudo random noise (PN) code synchronously with an oscillated frequency of a chip rate oscillator 12 and provides newly an output of a bit pattern signal of the PN code from the head bit when a correlation peak signal is received from a correlation detector 19. A decode circuit 25 provides an output of the signal converted into a prescribed square wave corresponding to the period of the PN code based on the bit pattern signal of the PN code outputted from the chip length counter 13 as a synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention, based on a correlation peak signal obtained each time a spread spectrum signal matches a bit pattern signal of a PN code, generates a spectrum for generating a synchronization signal corresponding to the cycle of the correlation peak signal. The present invention relates to a spread signal synchronization signal generator and a spread spectrum communication device including a demodulator including the same.

[0002]

In recent years, spread spectrum (hereinafter referred to as S) which is resistant to noise and excellent in confidentiality has been developed.
Communication systems have started to attract attention, and along with this, development of transmission / reception devices has been advanced.

Generally, in the SS communication system, an SS signal which is a transmission signal is obtained by first-modulating a predetermined code sequence having a predetermined high bit rate with an information signal, and thereafter,
The modulated signal is secondarily modulated to generate an SS signal in a wide frequency band.

In this case, the above code sequence includes, for example,
Pseudo Random Noise (hereinafter abbreviated as PN) code sequence is used, and SS modulation uses a direct modulation method (Dire
ct Sequense, hereinafter abbreviated as DS system) or frequency hopping system (Frequency Hopping, hereinafter abbreviated as FH system).

In such an SS communication system, as a receiver for receiving an SS signal modulated by the DS system using, for example, a PN code sequence, there is a receiver that demodulates using a matched filter. For this matched filter,
For example, there is a surface acoustic wave device having an input electrode on which an interdigital electrode pattern corresponding to the PN code is formed. When an SS signal is input, the signal pattern is the same as the interdigital electrode pattern of the input electrodes. When they match, that is, when they match the cycle of the PN code, the correlation peak signal is output. Then, the transmitted data can be demodulated by identifying the correlation peak signal in a state of being synchronized with the transmission cycle of the transmission data.

In this case, in order to synchronize with the transmission cycle of the data signal on the receiver side, there is one obtained by generating a synchronization signal using the correlation peak signal. This is because if the correlation peak signal itself is used, the demodulation operation may not be normally performed when the output timing of the correlation peak signal fluctuates or is missing depending on the reception state. In order to generate such a synchronization signal, for example, a PLL (Phase Locked L) as shown in FIG.
oop) circuit is used.

That is, in FIG. 5, the correlation detector 1 is composed of, for example, a matched filter made of a surface acoustic wave element, and an interdigital electrode pattern corresponding to one period of the same PN code as that at the time of modulation is formed as an input electrode. Was done,
When the SS signal is input, the correlation peak signal is output each time the PN code of the input electrode matches. The PLL circuit 2 includes a phase comparator 3, an LPF (low pass filter) 4, and a VC.
A general type composed of an O (voltage controlled oscillator circuit) 5, and when a correlation peak signal is input from the correlation detector 1,
Based on this, a synchronizing signal is generated and output.

In the above configuration, the correlation detector 1 to FIG.
When the correlation peak signal of the SS signal as shown in (a) is output, the PLL circuit 2 outputs the synchronization signal as follows. First, the phase comparator 3
Correlation peak signal and output signal from VCO 5 (Fig. (B))
(See (c) in FIG. 3) and outputs a signal corresponding to the phase difference. The VCO 5 outputs a signal having a frequency corresponding to the voltage signal corresponding to the DC component of the phase difference obtained from the phase comparator 3 via the LPF 4 as a synchronizing signal.

In this way, as the correlation peak signal is repeatedly input, the synchronization between the synchronization signal output from the PLL circuit 2 and the correlation peak signal can be accurately obtained, and it can be used as a stable synchronization signal. You will be able to.

In the above case, in order to stabilize the output of the synchronizing signal by the PLL circuit 2, it is necessary to increase the time constant of the LPF 4. This is because even if the correlation peak signal is missing or the output cycle fluctuates, the time constant of the LPF 4 is set to be large, so that the fluctuation is less adversely affected.

In the SS signal demodulation circuit,
A timing signal is generated by adjusting the delay time using a timing signal generation circuit, etc. using the synchronization signal obtained as described above, and transmitted by identifying the above correlation peak signal at the timing of generation of this timing signal. The data can be demodulated.

By the way, the time from the input of the first correlation peak signal to the PLL circuit 2 to the output of the synchronization signal corresponding to the period of the correlation peak signal, that is, PL
The time required to establish the synchronization of the L circuit 2 largely depends on the time constant of the LPF 4, so it is preferable to set the value to be small. On the other hand, as described above, in order to obtain a stable synchronization signal from the PLL circuit 2, it tends to be better to set the time constant of the LPF 4 larger.

That is, in setting the time constant of the LPF 4, there is a trade-off relationship between them, and in reality, an intermediate time constant that causes no practical problem is set. As a result, it is general that the time required for establishing the synchronization of the PLL circuit 2 is normally about several milliseconds.

On the other hand, the demand for faster data communication by wireless communication has been increasing year by year, and a communication speed of about several Mbps (bit per second) has been demanded as a practical level. In response to such a request, SS
Since the communication method has excellent anti-multipath characteristics,
It is drawing attention as a communication method suitable for high-speed communication even in an environment where radio wave conditions are bad, and its practical application is desired.

However, even when high-speed communication of about several Mbps is possible by the SS communication system as described above, the time required for generating the synchronization signal by the PLL circuit 2 is about several milliseconds as described above. In reality, the following problems are unavoidable.

That is, for example, if the time required to establish synchronization of the PLL circuit 2 is 1 millisecond when performing SS communication of 1 Mbps, the leading 1,000 bits are discarded, resulting in communication efficiency. However, there was a problem that In particular, in the half-duplex communication method in which transmission and reception are alternately switched and communication is performed, it is necessary to establish synchronization each time reception is started, and therefore, it takes time to obtain a stable synchronization signal each time. The first 1,000 needed
The bits were discarded, and the adverse effect on the deterioration of communication efficiency was great.

The present invention has been made in view of the above circumstances. An object of the present invention is to spread spectrum in which a synchronization signal corresponding to the period of a correlation peak signal can be quickly generated and communication efficiency can be improved. It is to provide a synchronizing signal generator for signals.

[0018]

A spread spectrum signal synchronizing signal generator according to the present invention receives a spread spectrum signal that matches a bit pattern signal of a PN (pseudo noise) code having a predetermined code length, Correlation peak detection means for outputting a correlation peak signal each time the cycles match, an oscillator set to the same oscillation frequency as the chip rate frequency of the spread spectrum signal, and the PN code of the PN code in synchronization with the oscillation frequency of this oscillator. The bit pattern signal is provided so as to be repeatedly output, and when the correlation peak signal is input from the correlation peak detection means, this is accepted as a set signal and a bit pattern signal of the PN code is newly added from a predetermined specific bit. Code length counter means for outputting, and the bit pattern signal output from the code length counter means Those having features at which a synchronization signal generating means for outputting a signal corresponding to the period of the PN code as a synchronization signal based on.

According to the above-mentioned spread spectrum signal synchronizing signal generator, the code length counter means receives the correlation peak signal output from the correlation peak detecting means as a set signal and receives the PN code. A bit pattern signal is newly output from a predetermined specific bit. Then, the synchronization signal generation means outputs a signal corresponding to the cycle as a synchronization signal based on the bit pattern signal of the PN code output from the code length counter means.

In this case, since the code length counter means repeatedly outputs the bit pattern signal of the PN code,
For example, when the correlation peak signal is not output by the correlation peak detection means, the bit pattern signal is repeatedly output in the absence of the set signal, so the synchronization signal generation means outputs the synchronization signal based on the bit pattern signal. Can be generated.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment in which the present invention is applied to a spread spectrum communication apparatus in which transmission / reception operations are performed by a half-duplex communication system will be described below with reference to FIGS. 1 to 4. To do.

First, referring to FIG. 3 showing the structure of the transmitting unit,
The PN code generator 11 is composed of a chip rate oscillator 12 as an oscillator and a chip length counter 13 as a code length counter means. The chip rate oscillator 12 is SS
The chip length counter 13 outputs a signal of the chip rate frequency of the PN code used for communication, and the chip length counter 13 outputs bit pattern data corresponding to the PN code based on the signal from the chip rate oscillator 12. In this case, in the bit pattern data, for example, when the PN code is n bits, the data PN (1), PN is configured so that each bit constitutes n bits as data corresponding to "1" or "0".
(2), ..., PN (n) are set, and the PN code is sequentially and repeatedly output.

The SS modulator 14 includes a chip length counter 13
The bit pattern data given from the output data acquisition unit 15 is SS-modulated by the transmission data from the transmission data acquisition unit 15 and output. The transmission data acquisition unit 15 synchronizes with the bit pattern data output from the chip length counter 13. It is supposed to be output. The carrier wave modulator 16 modulates a carrier wave with the signal SS-modulated by the SS modulator 14 and outputs the carrier wave. The carrier wave is supplied from the local oscillator 17. The signal output from the carrier wave modulator 16 is amplified via the power amplifier 18 and output as an SS signal via an antenna (not shown).

FIG. 4 shows an overall block configuration of a receiving section incorporated in the above spread spectrum communication apparatus. The correlation detector 19 as a correlation peak detecting means is composed of, for example, a matched filter composed of a surface acoustic wave element, and the cross finger electrode pattern is formed so as to have the same PN code as the PN code used at the time of modulation. A correlation peak signal is output each time an SS signal that matches the PN code is input. This correlation detector 1
The output terminal of 9 is connected to the input terminals of the arithmetic circuit 20 and the delay circuit 21, and the timing pulse generating circuit 2
2 is connected to the input terminal.

The output terminal of the delay circuit 21 is connected to the input terminal of the arithmetic circuit 20, and the input signal is P
The output is delayed by one cycle of the N code. Arithmetic circuit 2
0 has its output terminal connected to the input terminal of the discrimination and reproduction circuit 23, calculates the product of the delayed signal given from the delay circuit 21 and the signal inputted from the correlation detector 19, and obtains the calculation result. Output.

The output terminal of the timing pulse generation circuit 22 is connected to the discrimination and reproduction circuit 23, and the signal corresponding to the cycle of the correlation peak signal is synchronized based on the correlation peak signal input from the correlation detector 19. It is generated as a signal, and a timing pulse is generated with the synchronizing signal as a reference.

The identification / reproduction circuit 23 identifies the transmission data based on the signal of the operation result given from the arithmetic circuit 20, and reproduces the transmission data at a cycle based on the timing pulse given from the timing pulse generation circuit 22.

Now, the timing pulse generating circuit 22
Is for synthesizing a timing signal on the basis of a synchronizing signal generating circuit 24 for generating a synchronizing signal and a synchronizing signal generated by the synchronizing signal generating circuit 24. In FIG. Is shown.
In the synchronizing signal generating circuit 24, the PN code generating unit 11 used as the transmitting unit side is switched and used so as to be connected only during reception.

In this case, in the PN code generator 11,
As described above, the chip length counter 13 constantly outputs the bit pattern signal corresponding to the PN code in a state of being synchronized with the signal of the oscillation frequency of the chip rate oscillator 12, and outputs the same. It is supplied to the barrel decoding circuit 25. Then, the chip length counter 13 is adapted to receive the correlation peak detection signal from the correlation detector 19, and when the correlation peak signal is inputted, it is used as a set signal among the bit pattern signals of the PN code. The output is newly started from the data of PN (1) as the predetermined start data.

When the correlation peak signal is once input and the output from the data PN (1) of the PN code is started, the chip length counter 13 outputs the data PN (1) next in the subsequent operations. As a few bits before and after the time point, for example, only a period of 2 bits is set as a reception period of the correlation peak signal, and when the correlation peak signal is input outside the period, it is invalidated. Has become.

The reason why the PN code generator 11 used in the transmitter is used in the receiver is as follows. That is, in SS communication, the oscillation frequency of the chip rate oscillator of the transmitter and the oscillation frequency of the chip rate oscillator of the receiver are normally set to be the same, and therefore, the period of the correlation peak signal output from the correlation detector 19 ( In other words, this is the PN output by the transmitter.
This is because the cycle of the bit pattern signal of the code) and the cycle of the bit pattern signal of the PN code output by the receiver are set to have the same value.

The decoding circuit 25 outputs a signal corresponding to the cycle of the PN code as a predetermined square wave based on the bit pattern signal of the PN code output from the PN code generator 11.

Next, the operation of the SS spread communication device will be described with reference to FIG. In the present embodiment, for convenience of explanation, the following setting state will be shown as an example. That is, for example, the PN code output from the chip length counter 13 is set to "11100010010" 1
1-bit bit pattern signal, decoding circuit 25
, The upper 6 bits of those are "1110".
An example will be described in which the signal "00" is set to a high level and the signal of the lower 5 bits "10010" is set to a low level and is output as a decoded square wave.

Now, in the state where the chip length counter 13 outputs the PN code bit pattern signal in the free-run state in synchronization with the oscillation output of the chip rate oscillator 12 (see FIG. 2B) (see FIG. (See (c)), and accordingly, the above-mentioned square wave is output from the decoding circuit 25 (see (d) in the same figure). In this state, the correlation detector 19
When the SS signal is input to, the correlation detector 19 outputs a correlation peak signal for each cycle of the PN code (see (a) in the figure). When the correlation peak signal is input, the chip length counter 13 accepts this as a set signal and newly outputs the bit pattern signal of the PN code from the first bit, and the decoding circuit 25 also newly outputs the signal accordingly. The square wave obtained by decoding is output as a synchronizing signal.

In this case, since the chip length counter 13 repeatedly outputs the bit pattern signal of the PN code, it outputs the bit pattern signal even when the correlation peak signal is not output by the correlation detector 19, for example. The decoding circuit 25 can generate a synchronization signal based on the bit pattern signal.

Further, when the input timing of the correlation peak signal to the chip length counter 13 is shifted by 3 bits or more from the timing at which the next PN (1) is output, the chip length counter 13 will Since the correlation peak signal is not accepted as the set signal, even if the correlation peak signal is input at different timings due to noise or the like, it can be invalidated, and the output timing of the synchronization signal can be stably maintained.

Then, the timing pulse generation circuit 22
Generates and outputs a timing pulse based on the synchronization signal output from the decoding circuit 25 in synchronization with the period of the correlation peak signal. The identification reproduction circuit 23 performs identification reproduction processing based on the timing pulse output from the timing pulse generation circuit 22, and reproduces the transmission data.

According to the present embodiment as described above, the correlation detector 1 is configured so that the chip length counter 13 repeatedly outputs the bit pattern data at the oscillation frequency of the chip rate.
When the correlation peak signal is input from 9, the bit pattern data is newly output from a predetermined bit by using this as a set signal, and the decoding circuit 25 obtains the synchronization signal based on the bit pattern data. Since the synchronization signal can be generated at the time when at least one correlation peak signal is obtained, and the synchronization signal can be continuously output even when there is a gap in the detection of the correlation peak signal, As compared with the configuration described above, the reception process can be started more quickly.

Further, since the chip length counter 13 is configured to accept the correlation peak signal as a set signal only within a predetermined time range centered on the time point at which the correlation peak signal is expected to be output, the chip length counter 13 is set to a predetermined time. Even if a signal is input outside the range, it is not possible to accept it as a set signal, and the noise resistance characteristic can be improved.

In the case of the half-duplex communication system as in the present embodiment, it is necessary to newly obtain a synchronization signal each time the receiving operation is performed, so that the time required to obtain the synchronization signal is increased. The communication efficiency can be significantly improved because the communication efficiency can be significantly reduced.

Further, in the case of the transceiver of the half-duplex communication system, since the transmitter and the receiver are not used at the same time, the chip length counter 13 and the chip rate oscillator 12 used in the transmitter are used only when receiving. Since the timing pulse generating circuit 22 can be used by being switched and connected to the timing pulse generating circuit 22, the overall configuration can be made inexpensive and small.

The present invention is not limited to the above embodiment, but can be modified or expanded as follows. In the present embodiment, the chip length counter 13 newly outputs the bit pattern signal of the PN code from the first bit when the correlation peak signal is input, but the present invention is not limited to this.
You may make it output newly from a predetermined bit.

Further, although the decoding circuit 25 is used to generate the synchronizing signal from the PN code bit pattern signal, the present invention is not limited to this, and any signal corresponding to the cycle of the PN code bit pattern signal may be generated. Good.

[0044]

As is clear from the above description, according to the spread signal synchronizing signal generator of the first aspect, the code length counter means repeatedly outputs the bit pattern signal at the oscillation frequency of the oscillator. When a correlation peak signal is input from the correlation peak detection means, this is used as a set signal to output a new bit pattern signal from a predetermined bit, and the synchronization signal generation means obtains a synchronization signal based on this bit pattern signal. With this configuration, the synchronization signal can be generated when at least one correlation peak signal is obtained, and
Even if the detection of the correlation peak signal is missing, the synchronization signal can be output continuously, so the reception process can be started more quickly than in the conventional configuration, and the communication efficiency is greatly improved. Can be planned.

According to the spread signal synchronizing signal generator of the second aspect, the code length counter means is within a predetermined time range centered on the time when the next specific bit of the bit pattern signal of the PN code is output. Since the correlation peak signal is received only as a set signal when it is input, even if a signal such as noise other than the correlation peak signal is output from the correlation peak detection means outside the predetermined time range, It is possible to prevent the output of the synchronization signal from being disturbed by not accepting it and improve the noise resistance characteristic.

According to the spread spectrum communication apparatus of the third aspect, the demodulating apparatus including the synchronization signal generating apparatus for the spread spectrum signal according to the first or second aspect, and the modulation processing using the oscillator and the code length counter means. The modulator and the modulator that perform the above are configured to be switched and used according to each operation by the switching means, so that it is not necessary to separately provide the oscillator and the code length counter means for the demodulator and the modulator, and the overall configuration Can be inexpensive and miniaturized.

[Brief description of the drawings]

FIG. 1 is a functional block configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a signal waveform output from each block in FIG.

FIG. 3 is a functional block configuration diagram of a transmission unit.

FIG. 4 is a functional block configuration diagram of a demodulation device.

FIG. 5 is a diagram corresponding to FIG. 1 showing a conventional example.

FIG. 6 is a view corresponding to FIG.

[Explanation of symbols]

In the drawing, 12 is a chip rate oscillator (oscillator), 13 is a chip length counter (code length counter means), 19 is a correlation detector (correlation peak detection means), and 25 is a decoding circuit (synchronization signal generation means).

Claims (3)

[Claims] 1. A correlation peak detecting means for outputting a correlation peak signal each time a period thereof matches when a spread spectrum signal matching a bit pattern signal of a PN (pseudo noise) code having a predetermined code length is inputted. An oscillator set to the same oscillation frequency as the chip rate frequency of the spread spectrum signal; and a correlation peak detecting means provided to repeatedly output the bit pattern signal of the PN code in synchronization with the oscillation frequency of the oscillator. When the correlation peak signal is input from the above, it is received as a set signal, and a code length counter means for newly outputting the bit pattern signal of the PN code from a predetermined specific bit, and the code length counter means are output. A signal corresponding to the cycle of the PN code is output as a synchronization signal based on the bit pattern signal. A synchronizing signal generator for a spread spectrum signal, comprising: 2. The code length counter means counts when the correlation peak signal is input within a predetermined time range centered around a time point at which the next specific bit of the bit pattern signal of the PN code is output. 2. The synchronization signal generator for a spread spectrum signal according to claim 1, wherein the synchronization signal generator is configured to receive as a set signal. 3. A demodulation device configured to include the synchronization signal generator for spread spectrum signal according to claim 1 or 2 for demodulating a spread spectrum signal, and an oscillator and a code length counter means provided in the demodulation device. A modulator that is configured to include a component and that performs a modulation process to output a spread spectrum signal, and the oscillator and the code length counter means are set to be switched between a state of connecting to the demodulator and a state of connecting to the modulator. A spread spectrum communication device, comprising: a switching means capable of switching, wherein the switching means is configured to be switched and set corresponding to each operation of the demodulation device and the modulation device.