JPH09181219A - Power semiconductor module - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress warping of a heated metal substrate. SOLUTION: Electric circuits each including a power semiconductor chip are discretely formed on a plurality of, e.g. five ceramic plates 20, 30, 50, 70 and 90, and are placed on a metal substrate 10. Accordingly, when the ceramic plates and the metal substrate are heated for soldering even if the metal substrate 10 warps due to the difference between thermal-expansion coefficients of the ceramic plates and the substrate, the warp of the metal substrate 10 can be diffused. That is, the warp of the metal substrate 10 can be suppressed to a low level.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module having a structure in which an insulating substrate on which an electric circuit is formed is mounted on a metal substrate, and in particular, the insulating substrate and the metal substrate are The present invention relates to a power semiconductor module that is bonded by brazing such as soldering.

[0002]

2. Description of the Related Art In recent years, in welding machines, chargers, uninterruptible power supply devices, motor control devices, and the like, in order to reduce the size and weight of these devices, an inverter circuit is often used in the power supply part thereof. ing. FIG. 3 shows an example of a circuit diagram of a power supply unit using this inverter circuit.

In the figure, reference numeral 1 is an AC power supply, and a commercial AC voltage of, for example, 50 or 60 Hz is supplied from this AC power supply 1 to this power supply section. The commercial AC voltage supplied to this power supply unit is rectified by a bridge circuit composed of a series circuit 2 of thyristors 2a and 2b and a series circuit 3 of diodes 3a and 3b, and further smoothed by a series circuit 4 of capacitors 4a and 4b. After being converted into a DC voltage, it is input to the inverter circuit 5.

The inverter circuit 5 includes a switching element 5
a and 5b series circuit and each switching element 5a, 5b
A freewheeling diode 5c anti-parallel connected to
5d and converts the input DC voltage into a high frequency AC voltage of 20 to 50 kHz, for example. The switching elements 5a and 5b are formed of, for example, IGBTs, MOS-FETs, bipolar transistors, etc., and their switching operations are controlled by a control circuit (not shown).

The output of the inverter circuit 5 is insulated by the high frequency transformer 6 and transformed to a voltage level required for the load. And the output diode 7a,
It is rectified by the output rectifying circuit 7 composed of 7b, further smoothed by the reactor 8, that is, converted into a DC voltage again, and supplied to a load (not shown).

In the circuit shown in the figure, a triac 9 is provided between one end of the AC power supply 1, the connection point of the capacitors 4a and 4b, and one end of the primary winding 6a of the high frequency transformer 6. . That is, when the AC power supply 1 is 100 V system, the gate terminal of the triac 9 is turned on to
AC power supply 1 by turning it off in the 0V system
In both the 100V system and the 200V system, the levels of the DC voltage supplied to the inverter circuit 5 are configured to be substantially the same.

By the way, the power supply unit as shown in FIG.
In particular, power semiconductor devices (that is, thyristors 2a, 2b,
Diodes 3a and 3b, switching elements 5a and 5b,
The freewheeling diodes 5c and 5d, the output diodes 7a and 7b, and the triac 9) are generally integrated into a single case as a power semiconductor module, thereby further reducing the size and weight. There is. Conventionally, as this power semiconductor module, for example, there is one as shown in FIG.

In the figure, reference numeral 100 designates an insulating substrate, for example, a ceramics plate made of alumina, aluminum nitride, or the like. The ceramics plate 100 has a substantially rectangular shape with four corners cut out slightly in a fan shape. There is. A copper circuit (pattern) 100a is formed on one surface of the ceramic plate 100 (the front surface of the paper in FIG. 1A and the upper surface in FIG. 2B) by metallization or other processing. Has been done, this copper circuit 1
The chip component (semiconductor chip) of each of the power semiconductor elements described above is soldered to a predetermined portion of 00a. Further, if necessary, the power semiconductor chip and the copper circuit 100
Wire bonding (not shown) is carried out with a, whereby the circuit shown in FIG. 3 is formed. On the other hand, on the other surface of the ceramic plate 100,
The metal layer 100b made of, for example, copper is formed by the metallizing process or another process.

Reference numeral 10 in FIG. 4 is a metal substrate formed of, for example, iron, copper, aluminum, or the like. The metal substrate 10 has a slightly (planar) area smaller than that of the ceramic plate 100, for example, about one turn. It has a large rectangular shape. Then, on the metal substrate 10, the ceramic plate 100 with the surface on which the metal layer 100b is formed facing the one surface of the metal substrate 10,
Moreover, the metal substrate 10 is mounted so as not to protrude from the peripheral edge thereof. The metal substrate 10 and the ceramic plate 10
0 is bonded by brazing, for example, soldering. For example, cream solder is printed on one surface of the metal substrate 10, the ceramic plate 100 is placed on this, and the reflow furnace is used. It is possible to realize solder bonding between the two by heating at. Further, at the time of this solder bonding, cream solder is applied in advance to necessary portions on the copper circuit 100a, and, for example, a relay strip or an external lead terminal (not shown) for connecting the copper circuits 100a is placed thereon. By doing so, these can also be solder-bonded at the same time by heating the reflow furnace.

Then, after the above-described solder bonding, FIG.
As shown by the alternate long and short dash line, the peripheral edge and the upper portion of the metal substrate 10 are covered with, for example, a resin case, a predetermined amount of silicon gel is injected into the case, which is heat-cured, and further filled with epoxy resin. By heat-curing this,
The power semiconductor module has been completed. The external lead-out terminal described above is pulled out to the outside of the case, and the parts other than the power semiconductor chip that cannot be housed in the case, that is, the capacitors 4a and 4b, the high frequency transformer 6, the reactor 8 and the like are , Are connected to these external lead terminals on the outside of the case.

Further, this power semiconductor module is usually fixed to, for example, a cooling fin as shown by a dotted line in FIG. 2B in order to radiate the heat generated from each power semiconductor chip inside to the outside. To be done. The cooling fins are provided so as to come into close contact with the surface of the metal substrate 10 opposite to the side on which the ceramic plate 100 is placed, and the power semiconductor modules are provided at the four corners of the metal substrate 10. It is fixed to the cooling fin by bolts or the like via the mounting holes 11, 11 ,.

[0012]

When the metal substrate 10 and the ceramic plate 100 are heated in the reflow furnace as described above, both of them thermally expand, but the metal substrate 10
Since the coefficient of thermal expansion of is much larger than the coefficient of thermal expansion of the ceramic plate 100, the metal substrate 10 expands more than the ceramic plate 100. As a result, the metal substrate 10 is warped (deformed) at the bonding surface between the metal substrate 10 and the ceramic plate 100. Here, in the above-described conventional technique, the ceramic plate 100 has a size (area) slightly smaller than that of the metal substrate 10, that is, the ceramic plate 100 is solder-bonded over substantially the entire surface of the metal substrate 10. There is a problem in that the metal substrate 10 is largely warped over substantially the entire surface thereof, as exaggeratedly shown in FIG.

That is, if a large amount of warpage occurs on the substantially entire surface of the metal substrate 10 as described above, when the power semiconductor module is fixed to the cooling fin, it is not possible to sufficiently adhere the both. Therefore, the heat generated from the power semiconductor chip in the power semiconductor module is not sufficiently conducted to the cooling fin side, that is, the heat radiating effect by the cooling fin cannot be sufficiently obtained, and thus the power semiconductor chip is not heated. There is a problem that it may be destroyed.

In order to obtain the heat radiation effect of the cooling fins, a large force is applied in a direction opposite to the warp direction of the metal substrate 10 so that the power semiconductor module (metal substrate 10) and the cooling fins are connected to each other. If they are forcibly brought into close contact with each other (when the warp of the metal substrate 10 is attempted to be corrected), the ceramic plate 100 may not be able to withstand this stress and may be cracked (broken).

Further, as shown in FIG. 5, when the central side of the metal substrate 10 is warped in a convex shape so as to protrude in a direction opposite to the side where the ceramic plate 100 is located, the cream is applied during heating in the reflow oven. The gas and air remaining in the solder cannot escape to the outside, which causes voids (cavities: not shown) in the solder layer 12.
When voids are generated in the solder layer 12 as described above, the heat conduction efficiency between the ceramic plate 100 and the metal substrate 10 is deteriorated, and this also causes a decrease in the heat dissipation effect.

It is an object of the present invention to provide a power semiconductor module that overcomes the above problems by suppressing the warpage of the metal substrate 10.

[0017]

In order to achieve the above object, the invention according to claim 1 of the present invention is an insulator having an electric circuit including a power semiconductor element formed on one surface thereof. A substrate and a metal substrate on which the insulator substrate is mounted, the insulator substrate having the other surface adhered to the metal substrate surface by brazing such as soldering. In the power semiconductor module mounted on the metal substrate so as not to protrude from the peripheral edge, the insulator substrate is mounted on the metal substrate in a state of being divided into a plurality of parts. It is a thing.

That is, since the insulating substrate is divided,
The warp (deformation) generated in the metal substrate is also dispersed.

According to a second aspect of the present invention, in the power semiconductor module according to the first aspect, a plurality of the electric circuits are formed, and the insulating substrate is provided for each of the electric circuits and for some of the electric circuits. It is characterized in that it is divided according to both or one of each combination of circuits.

That is, one or a plurality of electric circuits are formed for each insulator substrate. In addition, the electric circuit referred to here means a circuit configured to perform a certain electric function by itself.

The third aspect of the present invention is the first or second aspect.
In the power semiconductor module according to, each maximum dimension in each direction along the brazing surface with the metal substrate of each insulator substrate is half or less of the maximum dimension in each of the metal substrate in all directions. It is characterized by being configured into a state.

That is, as compared with the case where the insulator substrate is adhered over substantially the entire surface of the metal substrate, the degree of warpage of the metal substrate is reduced to half or less.

According to a fourth aspect of the present invention, in the power semiconductor module according to the first, second or third aspect, the maximum in each direction along the brazing surface of the insulator substrate with the metal substrate. Among the dimensions, the maximum dimension of the insulating substrate having the largest dimension is configured to be 1 to 3 times the maximum dimension of the insulating substrate having the smallest dimension. .

That is, of the warpage that occurs on the metal substrate,
The degree of warp in the portion with the largest warp is 1 to 3 times the degree of warp in the portion with the smallest warp.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a power semiconductor module according to the present invention will be described with reference to FIG. The power semiconductor module according to the present embodiment is
Similar to the prior art described above, for example, the circuit configuration shown in FIG. 3, particularly each power semiconductor chip (thyristor 2a, 2
b, diodes 3a and 3b, switching elements 5a and 5
b, the freewheeling diodes 5c and 5d, the output diodes 7a and 7b, and the triac 9) are put together in one case, and FIG. 1A is a plan view showing a state before the case is attached. The same figure (b) is a side view.

The power semiconductor module according to the present embodiment is provided with a plurality of ceramic plates 100 of the prior art power semiconductor module shown in FIG.
For example, five ceramic plates 20, 30, 50, 70,
It is divided into 90 pieces, and these are placed and adhered on the metal substrate 10. This is a major feature of this embodiment. The configuration other than this is the same as that of the above-described conventional technique, and the same reference numerals are given to the same portions, and detailed description thereof will be omitted.

That is, the ceramic plate 2 shown in FIG.
0, 30, 50, 70, 90 are formed of, for example, alumina, aluminum nitride, or the like, similarly to the ceramic plate 100 in the above-mentioned conventional technique, and each is formed in, for example, a rectangular shape. Then, one side of each (Fig. 1
The copper circuits (patterns) 20a, 30a, 50a, 70 are formed on the front side surface of the paper in (a) and the upper surface in (b) of the figure by metallization or other processing.
a and 90a are formed. Further, metal layers 20b, 30b, 50b, 70b, 90b made of, for example, copper are formed on the other surface of each by metallizing treatment or other treatment.

Of these, the chip parts of the thyristors 2a and 2b shown in FIG. 3, for example, are soldered to predetermined positions of the copper circuit 20a formed on the ceramic plate 20, that is, on the ceramic plate 20. Form a series circuit 2 including the thyristors 2a and 2b.

Chip parts of the diodes 3a and 3b shown in FIG. 3, for example, are soldered to predetermined portions of the copper circuit 30a formed on the ceramic plate 30, that is, on the ceramic plate 30. , The diode 3
A series circuit 3 including a and 3b is formed.

Further, at predetermined positions of the copper circuit 50a formed on the ceramic plate 50, for example, the switching elements 5a and 5b and the free wheeling diode 5 shown in FIG.
The chip components c and 5d are soldered. That is,
On the ceramic plate 50, the switching elements 5a, 5b and the freewheeling diodes 5c, 5
An inverter circuit 5 composed of d is formed.

Further, for example, the chip parts of the output diodes 7a and 7b shown in FIG. 3 are soldered to predetermined portions of the copper circuit 70a formed on the ceramic plate 70, that is, on the ceramic plate 70. Forms an output rectifying circuit 7 including the output diodes 7a and 7b.

The chip parts of the triac 9 shown in FIG. 3, for example, are soldered to predetermined portions of the copper circuit 90a formed on the ceramic plate 90, that is,
On the ceramic plate 90, a so-called power supply voltage switching circuit by the triac 9 is formed.

That is, the above ceramic plates 20, 3
Each of the 0, 50, 70 and 90 electric circuits independently performs a predetermined electric function, that is, a series circuit 2 of thyristors 2a and 2b, a series circuit 3 of diodes 3a and 3b, an inverter circuit 5, and an output rectifying circuit 7. A power supply voltage switching circuit (triac 9) is formed. In each ceramic plate 20, 30, 50, 80, 90, each copper circuit 2
Wire bonding (not shown) is formed between 0a, 30a, 50a, 70a, 90a and each power semiconductor chip as needed to form each of the above electric circuits.

Then, the above ceramic plates 20, 3
0, 50, 70, 90 are the metal substrates 10 with the surface on which the metal layers 20b, 30b, 50b, 70b, 90b are formed facing the one surface of the metal substrate 10. They are mounted so that they do not protrude from the peripheral edge of 10 or interfere with each other. Each ceramic plate 20, 3
0, 50, 70 and 90 are bonded to the metal substrate 10 by brazing, for example, soldering.

Each of the ceramic plates 20, 30, 50,
Regarding solder bonding between the metal substrates 70 and 90 and the metal substrate 10, for example, cream solder is printed on one surface of the metal substrate 10, the ceramic plate 100 is placed on this, and this is heated in a reflow oven. As a result, the solder bonding can be realized. In addition, at the time of this solder bonding, cream solder is applied in advance to necessary portions on each of the copper circuits 20a, 30a, 50a, 70a, 90a, and on these, for example, a relay strip or an external lead terminal for connecting each to each other. By placing the like parts (not shown) on them, it is possible to simultaneously solder them by heating the reflow furnace. In addition, the copper circuits 20a, 30a, 50a, 7
0a and 90a are connected to each other by wire bonding, for example, in addition to the above-mentioned relay band, if necessary.

Each ceramic plate 20, 30, 5
0, 70, and 90 are along the surface to be soldered to the metal substrate 10 when mounted on the metal substrate 10 (see FIG. 1).
Each maximum dimension in all directions (along the plane of (a))
It is configured to be less than or equal to half the maximum dimension of the metal substrate 10 in each of the above directions. For example, FIG.
As shown in (a), each ceramic plate 20, 30, 5
When 0, 70, 90 are placed on the metal substrate 10 in such a manner that each side is substantially parallel to each side of the metal substrate 10, each of the ceramic plates 20, 30, 50, 70, 90 The length of each side is configured to be half or less than the length of each side of the metal substrate 10 that is substantially parallel to these. Therefore, according to this configuration, each ceramic plate 20, 30,
The area of 50, 70, 90 is not more than a quarter of the area of the metal substrate 10.

Further, each ceramic plate 20, 30, 5
Among the maximum dimensions of 0, 70, 90 in each of the above-mentioned all directions, the maximum dimension of the ceramic plate having the largest dimension is 1 to 3 times the maximum dimension of the ceramic plate having the smallest dimension. It is configured. For example, in the left-right direction of FIG. 1A, the ceramic plate 50 having the largest dimension in this direction.
Has a maximum dimension W ₅₀ of 1 to 3 times the maximum dimension W ₇₀ of the ceramic plate 70 having the smallest dimension in the above direction (W ₇₀ ≤W ₅₀ ≤W ₇₀ × 3). Further, in the vertical direction of the figure, the maximum dimension D ₉₀ of the ceramic plate 90 having the largest dimension in this direction is 1 to 3 times the maximum dimension D ₅₀ of the ceramic plate 50 having the smallest dimension in the above direction ( D ₅₀ ≤
D ₉₀ ≦ D ₅₀ × 3).

Then, each of the above ceramic plates 20 and 3
After solder bonding of 0, 50, 70, 90 and the metal substrate 10 and connection between the respective copper circuits 20a, 30a, 50a, 70a, 90a, as shown in FIG. As described above, a case (not shown) is attached, and further, cooling fins are attached as shown by a dotted line in FIG.

As described above, according to the present embodiment, the plurality of ceramic plates 20, 30, 50, 70, 90 are mounted on the metal substrate 10 in a dispersed state. Therefore, even if each ceramic plate 20, 30, 50, 70, 90 and the metal substrate 10 are heated in a reflow furnace for solder bonding, the warpage of the metal substrate 10 caused by the difference in thermal expansion coefficient between the two Since they are dispersed, the warp of the metal substrate 10 can be suppressed to be smaller than that in the above-described conventional technique. Therefore, the adhesion between the metal substrate 10 and the cooling fins can be improved, that is, the heat dissipation effect of the cooling fins can be improved.

Further, even if the metal substrate 10 is warped, since the degree of the warp is small, it is possible to correct the warp with a force smaller than the conventional one. That is, even if a force is applied in the direction opposite to the direction of the warp in order to correct the warp, the amount of correction is smaller than in the conventional case, so that the stress applied to each ceramic plate 20, 30, 50, 70, 90 is also in the conventional case. Will be smaller than. Therefore, the stress applied to each of the ceramic plates 20, 30, 50, 70, 90 at the time of this correction damages (breaks) them.
There is little concern.

Furthermore, since the degree of warpage of the metal substrate 10 is small, the ceramic plates 20, 30, 50,
In the solder layer between 70 and 90 and the metal substrate 10,
The generation of voids can be suppressed.

Further, each ceramic plate 20, 30, 5
An electric circuit that independently performs a predetermined electric function for each of 0, 70, and 90, that is, a series circuit 2 of thyristors 2a and 2b, a series circuit 3 of diodes 3a and 3b, an inverter circuit 5, an output rectifying circuit 7, and a power supply. Since the voltage switching circuit (triac 9) is formed, each ceramic plate 20,
Between 30, 50, 70, 90, that is, each copper circuit 20a,
It is possible to suppress the number of wirings such as a relay band and wire bonding for connecting between 30a, 50a, 70a and 90a.

Then, each ceramic plate 20, 30, 5
Nos. 0, 70, 90 are configured such that the maximum dimensions in all directions along the soldering surface with the metal substrate 10 are half or less than the maximum dimensions in all the above directions of the metal substrate 10. Therefore, even if the metal substrate 10 is warped by heating in the reflow furnace, the degree of the warp is about half or less as compared with the conventional technique in which the ceramic plate 100 is solder-bonded over substantially the entire surface of the metal substrate 10. Can be suppressed.

Further, each ceramic plate 20, 30, 5
Among the maximum dimensions of 0, 70, 90 in each of the above-mentioned all directions, the maximum dimension of the ceramic plate having the largest dimension is 1 to 3 times the maximum dimension of the ceramic plate having the smallest dimension. It is configured. Therefore, even if the metal substrate 10 warps due to heating in the reflow furnace, the degree of warpage in the portion with the largest warp is 1 to 3 times the degree of warpage in the portion with the smallest warp, that is, It is possible to suppress the difference (variation) in the degree between the large warp portion and the small warp portion within three times.

In the present embodiment, the electric circuit including the power semiconductor module is divided into five ceramic plates 20, 3, 50, 70, 90, but the ceramic plates 20, 30, 50 are used. , 70 and 90 are
The number of sheets is not limited to five, and a plurality of sheets other than this may be used.

Further, each ceramic plate 20, 30, 5
For each of 0, 70, 90, each independently has an electrical circuit having a predetermined electrical function (thyristor 2a in the present embodiment,
2b series circuit 2, diodes 3a and 3b series circuit 3, inverter circuit 5, output rectifier circuit 7, so-called power supply voltage switching circuit by triac 9 are formed, and each ceramic plate 20, 30, 50, 70, 90 is formed. In addition, a combination of some of the above electric circuits may be formed.

Further, although the power semiconductor module in which the circuits shown in FIG. 3 are integrated has been described here, the present technology can be applied to other circuit configurations.

Then, each ceramic plate 20, 30, 5
For solder bonding 0, 70, 90 and the metal substrate 10,
Although these are heated using a reflow furnace, the solder bonding may be performed by a heating means other than the reflow furnace. Then, the above ceramic plates 20, 30, 50, 70, 9
Bonding between 0 and the metal substrate 10 may be performed by brazing other than solder bonding.

Further, in this embodiment, the ceramic plates 20, 30, 50, 70, 90 and the metal substrate 1 are used.
The case where the shape of 0 is a rectangle has been described.
Not limited to this, the present technology can be applied even when each has a shape as shown in FIG. 2, for example.

That is, in the figure, 40 is a metal substrate, and this metal substrate 40 has a shape other than a rectangle, for example, a hexagonal shape. Then, it is assumed that two ceramic plates 60, 80 having a shape other than a rectangle, for example, an uneven shape, are mounted on the metal substrate 40.

Also in such a case, similarly to the above-mentioned conditions, the respective maximum dimensions in all directions along the soldering surface of the ceramic plates 60, 80 with the metal substrate 40 are the above-mentioned all directions of the metal substrate 40. It is configured to be less than half of the maximum dimension of each.

That is, each ceramic plate 60 shown in FIG.
Of the 80, for example, the maximum dimension W _{60 of the} ceramic plate 60 having the largest dimension in the left-right direction in FIG.
Is less than half the maximum dimension W ₄₀ of the metal substrate 40 in the same direction (W ₆₀ ≦ (1/2) W ₄₀ ).

As for the vertical direction of FIG.
Maximum dimension D ₈₀ of the ceramic plate 80 with the largest dimension in the same direction, configured to be less than half of the maximum dimension D ₄₀ of the metal substrate 40 in the same direction _{(D 80 ≦ (1/2) D} 40) .

Further, for example, also in the diagonal direction shown by the dotted line in FIG. 6B, the maximum dimension L ₆₀ of the ceramic plate 60 having the largest dimension in the same direction is the maximum dimension L ₄₀ of the metal substrate 40 in the same direction. Less than half (L ₆₀ ≤
(1/2) L ₄₀ ).

Of course, directions other than the above, for example, FIG.
The same applies to the diagonal direction and the like indicated by the alternate long and short dash line.

Regarding the mutual relationship between the respective dimensions of the respective ceramic plates 60, 80, similarly to the above-mentioned conditions, the largest dimension among the respective maximum dimensions of the respective ceramic plates 60, 80 in all the above-mentioned directions. The maximum size of the ceramic plate is set to be 1 to 3 times the maximum size of the ceramic plate having the smallest size.

That is, of the ceramic plates 60, 80, the maximum size W ₆₀ of the ceramic plate 60 having the largest dimension in the left-right direction of FIG.
1 to 3 times the maximum dimension of W ₈₀ (W ₈₀ ≤ W ₆₀ ≤ W ₈₀ × 3)
It is configured so that

Regarding the vertical direction of FIG.
Maximum dimension D ₈₀ of the ceramic plate 80 with the largest dimension in the same direction, 1 to 3 of the largest dimension D ₆₀ of the ceramic plate 60 having a smallest dimension in the same direction
Double (D ₆₀ ≤ D ₈₀ ≤ D ₆₀ × 3).

Further, for example, also in the oblique direction shown by the dotted line in FIG. 6B, the maximum size L ₆₀ of the ceramic plate 60 having the largest dimension in the same direction is the ceramic plate 80 having the smallest dimension in the same direction. The maximum dimension L ₈₀ is 1 to 3 times (L ₈₀ ≤L ₆₀ ≤L ₈₀ × 3).

Of course, directions other than the above, for example, FIG.
The same applies to the diagonal direction and the like indicated by the alternate long and short dash line.

[0061]

EXAMPLE As an example of the power semiconductor module according to the present invention, each ceramic plate 20, 30, shown in FIG.
Of the 50, 70, 90, for example, the dimensions of the ceramic plate 90 having the largest area and the metal substrate 10 are as follows.

That is, in the left-right direction of FIG.
A maximum dimension W ₁₀ of the metallic substrate 10 and W ₁₀ = 110mm,
The maximum dimension W ₉₀ of the ceramic plate 90 in the same direction is W
Was _{90 = 28mm (W S <(} 1/2) W B).

Further, in the vertical direction of the figure, the maximum dimension D ₁₀ of the metal substrate ₁₀ is D ₁₀ = 87 mm, and the maximum dimension D ₉₀ of the ceramic plate 90 in the same direction is D ₉₀ = 43 mm.
mm (D ₉₀ <(1/2) D ₁₀ ).

According to these dimensions, the area ratio of the ceramic plate 90 to the metal substrate 10 is about 12.
6%.

Further, each ceramic plate 20, 30, 5
Of the 0, 70, and 90, the maximum dimension W ₅₀ of the ceramic plate 50 having the largest dimension in the left-right direction in the figure is W ₅₀ = 49 mm, and the maximum dimension W _{70 of the} ceramic plate 70 having the smallest dimension in the above direction. To W ₇₀ = 1
It was set to 8 mm (W ₇₀ ≦ W ₅₀ ≦ W ₇₀ × 3).

Further, while the maximum dimension D ₉₀ of the ceramic plate 90 having the largest dimension in the vertical direction in the figure is D ₉₀ = 43 mm as described above, the ceramic having the smallest dimension in the above direction. The maximum dimension D ₅₀ of the plate 50 is set to D ₅₀ = 28 mm (D ₅₀ ≤D ₉₀ ≤D
₅₀ x 3).

Then, the power-requiring semiconductor module constructed on the basis of the above-mentioned dimensional conditions was attached to the above-mentioned cooling fin and actually used, and its operating temperature was observed. As a result, no abnormal temperature rise of this power semiconductor module was observed, that is, according to the above-mentioned conditions, the metal substrate 10 had a large warp causing an abnormal temperature rise of the power semiconductor module. The result is that there is no.

[0068]

According to the first aspect of the present invention, since the warp generated in the metal substrate is dispersed, there is an effect that the warp of the metal substrate can be suppressed to be smaller than that in the above-mentioned conventional technique. Therefore, a higher heat dissipation effect can be obtained as compared with the above-mentioned conventional technique. Further, even if a force is applied in the direction opposite to the warp direction in an attempt to correct the warp of the metal substrate, the amount of correction is smaller than in the conventional case, so the stress applied to the insulating substrate by this correction is also smaller than in the conventional case. As a result, there is less concern that the insulating substrate will be damaged (broken). Furthermore, voids are less likely to occur in the solder layer between the insulator substrate and the metal substrate.

According to the second aspect of the invention, one or a plurality of electric circuits are formed for each insulator substrate.
That is, since the basic circuit configuration is formed for each insulating substrate, there is an effect that the number of wirings connecting the insulating substrates can be made smaller than that of the invention described in claim 1. .

According to the third aspect of the invention, the degree of warpage of the metal substrate can be reduced to half or less as compared with the conventional technique in which the insulating substrate is adhered over substantially the entire surface of the metal substrate. Therefore, the same effect as that of the invention described in claim 1 or 2 can be obtained.

According to the fourth aspect of the present invention, of the warpage occurring in the metal substrate, the degree of warpage in the portion with the greatest warpage is 1 to 3 times the degree of warpage in the portion with the least warpage. Is configured to be. That is, there is an effect that it is possible to suppress the difference (variation) in the degree of warp between the large warp portion and the small warp portion of the metal substrate within three times.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of a power semiconductor module according to the present invention, in which (a) is a plan view of the power semiconductor module and (b) is a side view.

FIG. 2 is a plan view of a power semiconductor module showing a mutual relationship of respective dimensions of a ceramic plate and a metal substrate in the same embodiment, (a) shows a relationship in vertical and horizontal directions, and (b) shows FIG. 5 is a diagram showing a relationship in an oblique direction.

FIG. 3 is an electric circuit diagram of a power semiconductor module showing the same embodiment.

FIG. 4 is a diagram showing a conventional power semiconductor module,
(A) is a plan view and (b) is a side view.

FIG. 5 is a diagram showing a state in which a metal substrate is warped in a conventional power semiconductor module.

[Explanation of symbols]

2a, 2b Thyristor (power semiconductor element) 3a, 3b Diode (power semiconductor element) 5a, 5b Switching element (power semiconductor element) 5c, 5d Freewheeling diode (power semiconductor element) 7a, 7b Output diode ( Power semiconductor element) 9 Triac (power semiconductor element) 10 Metal substrate 20, 30, 50, 70, 90 Ceramic plate (insulator substrate) 20a, 30a, 50a, 70a, 90a Copper circuit (pattern) 20b, 30b, 50b, 70b, 90b Metal layer

Claims (4)

[Claims] 1. An insulating substrate having an electric circuit including a power semiconductor element formed on one surface thereof, and a metal substrate on which the insulating substrate is mounted. The insulating substrate is the other one. In the power semiconductor module mounted on the metal substrate in such a state that the surface of the metal substrate is adhered to the metal substrate surface by brazing and does not protrude from the peripheral edge of the metal substrate surface, the insulator substrate is divided into a plurality of parts. A power semiconductor module, which is mounted on the metal substrate in a closed state. 2. The power semiconductor module according to claim 1, wherein a plurality of the electric circuits are formed, and the insulating substrate is provided for each of the electric circuits and for each combination of some of the electric circuits, or A power semiconductor module characterized by being divided according to one side. 3. The power semiconductor module according to claim 1, wherein each maximum dimension in each direction along each brazing surface of each of the insulator substrates with the metal substrate is equal to that of the metal substrate. A power semiconductor module, characterized in that the power semiconductor module is configured so as to be half or less of the maximum dimension in each direction. 4. The power semiconductor module according to claim 1, 2 or 3, wherein the largest dimension among the maximum dimensions in all directions along the brazing surface of the insulator substrate with the metal substrate. The power semiconductor module is characterized in that the maximum size of the insulating substrate having the above is set to be 1 to 3 times the maximum size of the insulating substrate having the smallest size.