JPH09181159A - Semiconductor device and manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device in which the flatness of a trench is increased by a method wherein the distance between adjacent protruding parts partitioned and formed by dummy patterns is set at a value in a specific range and the ratio of the average area of required element regions to the area of a fundamental unit is set at a value in a specific range. SOLUTION: Dummy patterns 27 as groove or hole array patterns are formed in a region outside an element region and in a region excluding a trench pattern 21. Protruding parts which are partitoned and formed by the dummy patterns 27 exist so as to be repeated with regularity. In addition, the distance between the adjacent protruding parts is set at 10μm or lower, and the ratio of the average area of required element regions to the area of a fundamental unit is set at 0.5 or higher and 2 or lower. The trench pattern and the dummy patterns are buried with an insulating film. Thereby, the dependence of a pattern on the flatness of a trench can be reduced.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same.

[0002]

2. Description of the Related Art With the increase in density and miniaturization of semiconductor devices, it has been attempted to introduce a trench isolation technique as an element isolation technique.

As a method of flattening a trench pattern associated with such trench isolation, a resist as a flattening material is coated on the entire surface so as to fill the step of the insulating film deposited on the substrate on which the trench pattern is formed. A resist etch back method for etching or a chemical mechanical polishing method (CMP method) for mechanically shaving and flattening an insulating film deposited on a substrate having a trench pattern by using a chemical polishing agent, a pad or the like. ).

Planarization by the resist etch back method is
The flattening material is inevitably affected by the step of the insulating film, and the pattern dependence of the flatness is more remarkable than that of the CMP method. Therefore, the CMP method is a technique for completely flattening the insulating film. Is a technology that has been attracting attention as.

The following is a description of a conventional example using the CMP method.
This will be described with reference to FIG.

First, as shown in FIG. 16A, a trench pattern 21 is formed on a silicon substrate 11 by dry etching using an active region forming mask 51.

Next, as shown in FIG. 16B, a silicon oxide film 23 is deposited on the trench pattern 21 as an insulating film. Here, the silicon oxide film 23 is formed in the trench pattern 2
It should be deposited thicker than 1 depth.

Then, as shown in FIG. 16 (c),
The silicon oxide film 23 is polished by the CMP method using the chemical polishing material and the polishing pad 61. This polishing is continued until the surface of the silicon substrate is exposed, and at the end of polishing, the state shown in FIG. 16D is obtained.

Next, as shown in FIG. 16 (e), a transistor including a gate electrode 31, a source / drain 32 and the like and a wiring 41 are formed by a known technique.

[0010]

However, in such a conventional example, as shown in FIG. 16 (c), when the width of the trench pattern 21 is wide, the polishing pad is also formed in the concave portion on the surface of the silicon oxide film. 61 will be pressed. Therefore, not only the convex portions but also the concave portions on the surface of the silicon oxide film are polished, and after the polishing, as shown in FIG. 16D, a depression is formed on the surface of the central silicon oxide film 22. In particular, when the width of the trench pattern reaches several hundreds of μm, the silicon oxide film used for filling the trench pattern may be entirely polished.

As described above, since the step is formed even after the CMP polishing, the depth of focus cannot be ensured in the lithography process, which is a problem in miniaturizing the device.

On the other hand, a configuration shown in FIG. 17 in which the semiconductor device described in Japanese Patent Laid-Open No. 3-278533 is applied to a MOS device can be considered. Note that, in FIG. 17, parts corresponding to those in FIG. 16 are designated by the same reference numerals.

In the device of FIG. 17, a trench pattern 21 is formed in the peripheral portion of the active region 33, and a trench pattern 25 having the same structure as that of the peripheral portion of the active region, that is, the trench pattern 25 having the same depth and width is formed under the wiring 41. To form. Moreover, the width of the trench 25 is narrower than the width of the wiring 41, and the silicon oxide film 75 is formed as an insulating film for insulating the wiring 41 and the silicon substrate 11. By thus forming the trench pattern 25 under the wiring, the effect of reducing the capacitance between the wiring 41 and the silicon substrate 11 can be obtained.

In the conventional example shown in FIG. 17, the width of the trench pattern is the same everywhere, and there is no trench pattern having a wide width as in the conventional example of FIG. 16. Therefore, during CMP polishing, It is possible to prevent polishing of recesses on the surface of the insulating film.

However, in the planarization technique by the CMP method, the larger the surface area of the convex portion is, the longer the polishing time is. Therefore, in the conventional example of FIG. 17, in the trench pattern in the region where the surface area of the convex portion is narrow. The insulating film will be polished more than necessary, and the flatness of the surface will be impaired.

When there is no misalignment of the semiconductor mask, the sectional structure of the semiconductor device is as shown in FIG. 18A, and the capacitance between the wiring 41 and the substrate 11 is minimized, but the wiring is As shown in FIG. 18B, the proportion of the trench pattern 25 that does not exist under the wiring increases due to the misalignment of the mask as shown in FIG. This is because it is difficult to improve the misalignment accuracy of the semiconductor mask in the lithography process with the miniaturization of the processing dimension.
A misalignment of up to 30 to 50% of the processing size occurs with respect to the processing size of μm.

The present invention has been made in view of the above technical problems, and mainly aims to solve the problem of the depth of focus in the lithography process by improving the flatness of the trench by the CMP method or the etchback method. With the purpose
Further, it is intended to prevent an increase in capacitance between the wiring and the substrate due to misalignment of the semiconductor mask.

[0018]

According to the present invention, in a semiconductor device in which an element is formed in each of a plurality of element regions separated by a trench pattern, the trench pattern is formed in a region other than the element region. A dummy pattern, which is an array pattern of grooves or holes, is formed in the removed region, and the convex portions defined by the dummy pattern are present with regularity and repetition, and
The distance between the adjacent convex portions is 10 μm or less, and the ratio of the average area of the required element region to the area of the basic unit for repeating the convex portions is 0.5 or more and 2 or less, The trench pattern and the dummy pattern are buried in an insulating film.

According to the semiconductor device of the present invention, a dummy pattern, which is an array pattern of regularly repeated grooves or holes, is provided outside the element region, and the convex portions partitioned by the dummy pattern are regularly repeated. Since the convex portions are arranged in a uniform pattern and are uniformly distributed, the pattern dependence of the flatness of the trench is reduced, and the flatness of the trench by the CMP method or the etchback method is reduced. Therefore, the problem of depth of focus in the lithography process can be solved.

[0020]

The present invention according to claim 1 is a semiconductor device in which an element is formed in each of a plurality of element regions separated by a trench pattern. A dummy pattern, which is an array pattern of grooves or holes, is formed in a region excluding the trench pattern, and the convex portions partitioned and formed by the dummy pattern are present with regularity and repeatedly between adjacent convex portions. The distance is 10 μm or less, and the ratio of the average area of the required element region to the area of the basic unit for repeating the convex portion is 0.5 or more and 2 or less, and the trench pattern and the dummy are formed. The pattern is configured to be buried in an insulating film, and the dummy pattern reduces the pattern dependence of the flatness of the trench to perform CMP. Alternatively it is possible to improve the flatness of the trench by an etchback method, by which,
The problem of depth of focus in the lithography process can be solved.

In the present invention according to claim 2 or 3, the required element region is the entire element region of the plurality of element regions or the element region having the highest frequency of formation, and the dummy pattern is a trench pattern for element isolation. The flatness of the trench can be further improved.

According to the fourth aspect of the present invention, the dummy pattern has a regular lattice shape, and the flatness of the trench can be improved by the dummy pattern having a relatively simple structure.

According to a fifth aspect of the present invention, a well isolation trench pattern is formed at a boundary between an n-well and a p-well in a region where the dummy pattern is formed, and the well isolation trench pattern is formed. The trench pattern is buried in the insulating film, whereby the n-well and the p-well are electrically completely separated, diffusion of impurities can be prevented, and device characteristics can be obtained. Is improved.

According to a sixth aspect of the present invention, an under-wiring trench pattern is formed in a region where the dummy pattern is formed, and the under-wiring trench pattern is buried in the insulating film. A wiring having a width narrower than that of the wiring lower trench pattern is formed on the insulating film, so that the capacitance between the wiring and the substrate can be reduced and the wiring between the wiring and the substrate due to misalignment of the semiconductor mask. It is possible to prevent the capacity from increasing.

According to a seventh aspect of the present invention, the insulating film is
This is a laminated film, and for example, by using a laminated film having excellent embedding characteristics such as polysilicon, the element can be miniaturized.

In the method of manufacturing a semiconductor device according to the present invention, at least two patterns, that is, a trench pattern surrounding each of the peripheral portions of a plurality of element regions and a dummy pattern that is an array pattern of grooves or holes, are simultaneously formed. A mask pattern forming step of forming a mask pattern for forming, an etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, and an insulating film deposition for depositing an insulating film A step of polishing and flattening the insulating film by a chemical mechanical polishing method, and an element forming step of forming an element in the element region, wherein the dummy pattern is a region other than the element region. hand,
Further, the dummy pattern is formed in a region excluding the trench pattern, and the dummy pattern has protrusions defined by the dummy pattern that are regularly repeated and have a distance between adjacent protrusions. Is 10μ
an average area of required element regions that is less than or equal to m, and
The ratio with the area of the basic unit of repeating the convex portion is 0.5
The above is 2 or less, which can improve the flatness of the trench by the CMP method and solve the problem of the depth of focus in the lithography process.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device in which at least two patterns, that is, a trench pattern surrounding each of the peripheral portions of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes, are simultaneously formed. A mask pattern forming step of forming a mask pattern for forming, an etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, and an insulating film deposition for depositing an insulating film A step, a flattening material forming step of forming a flattening material, an etchback step of etching back the insulating film and the flattening material by a dry etching technique, and an element forming step of forming an element in the element region. And the dummy pattern is a region other than the element region. And it is intended to be formed in a region except for the trench pattern, the dummy pattern,
The convex portions defined by the dummy pattern are present in a regular and repeated manner, the distance between adjacent convex portions is 10 μm or less, and the average area of the required element region and the convex portion The ratio to the area of the basic unit of repeated parts is 0.5 or more and 2 or less, which can improve the flatness of the trench by the etch-back method and reduce the problem of depth of focus in the lithography process. It can be resolved.

According to a tenth or eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein the required element regions are all the element regions of the plurality of element regions or the element regions having the highest frequency of formation, and the dummy pattern is The trench pattern for element isolation is provided, and the flatness of the trench can be further improved by the CMP method or the etchback method.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device, the mask pattern in the mask pattern forming step is n in a region where the dummy pattern is formed.
-Well and p-well well isolation trench patterns are formed at the same time, and in the etching step, at least the trench pattern, the dummy pattern and the well isolation trench pattern are simultaneously formed by dry etching. Is what
As a result, the n-well and the p-well are electrically completely separated, the diffusion of impurities can be prevented, and the device characteristics are improved.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device, the mask pattern in the mask pattern forming step is formed in a region where the dummy pattern is formed.
The wiring pattern is for simultaneously forming a trench pattern for wiring under, and the etching step is for simultaneously forming at least the trench pattern, the dummy pattern and the trench pattern for wiring under by dry etching. And a wiring forming step of forming a wiring having a width narrower than the width of the wiring underlying trench pattern on the insulating film in which the wiring trench pattern is buried, thereby reducing the capacitance between the wiring and the substrate. In addition, it is possible to prevent increase in capacitance between the wiring and the substrate due to misalignment of the semiconductor mask.

A method of manufacturing a semiconductor device according to a fourteenth aspect of the present invention comprises a laminated film forming step of forming a laminated film made of different films in the trench pattern and the dummy pattern, for example, polysilicon. The element can be miniaturized by using a laminated film having excellent burying characteristics such as.

Embodiments of the present invention will be described in detail below with reference to the drawings.

(Embodiment 1) FIG. 1 is a plan view of a semiconductor device according to one embodiment of the present invention as seen from above, and FIG. 2 shows a main part from which the dummy pattern in FIG. 1 is removed. FIG. 3 is a plan view, and FIG. 3 is a structural cross-sectional view and a plan view showing an enlarged main part of FIG.

In this embodiment, a wiring 41, a trench pattern 21 for element isolation, and a wiring lower portion are formed in a region outside the active region 33, which is an element region formed of the gate electrode 32 and the source / drain regions 32. A trench pattern 25 for separating the n-well 34 and the p-well 35, and a dummy pattern 27 in which a groove array pattern is formed in a grid pattern are formed. It is buried in the silicon oxide film 22. Each configuration will be specifically described below.

The trench pattern 21 around the active region 33 has a certain width so as to surround the active region 33 in a ring shape, and is filled with the silicon oxide film 22. The trench pattern 21 functions as an element isolation, and therefore, the trench pattern 21
The width of is not less than the minimum width that can function as element isolation. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.

On the other hand, the maximum width is determined by the limit at which digging does not occur during polishing by the CMP method. Alternatively, the wiring formed on the trench pattern is determined within a range that does not cause a problem in the depth of focus even if digging occurs. It goes without saying that this maximum width changes depending on the polishing conditions in the CMP method, such as pressure, rotation speed, pad material, and type of polishing material.

The dummy pattern 27 is shown in FIG.
As shown in (a), the purpose is to reduce the pattern dependence of the planarization of the trench by the CMP method or the etchback method, and to keep the area density of the pattern per required unit area substantially constant. In other words, in order to make the distribution of the convex portions uniform, in this embodiment, the convex portions are regularly arranged in a grid pattern and are formed by the dummy patterns 27. The island-shaped pattern 36 is set such that the distance between the adjacent island-shaped patterns 36 is 10 μm or less, which is a distance that does not cause digging due to polishing by the CMP method.

In general, in the flattening technique by the CMP method, the smaller the area forming the convex portion on the surface, the faster the polishing rate. Since the pattern having a larger area forming the convex portion of the surface requires a longer polishing time,
In the region where the area of the convex portion is small, the insulating film in the trench pattern is polished more than necessary, and the flatness of the surface is impaired.

Therefore, considering that the CMP method is applied to the planarization of the trench pattern in the present invention, one area of the rectangular island-shaped pattern 36 which is a basic unit of repetition defined by the dummy pattern 27 is It is desirable to select an element region of a semiconductor element that is most frequently used repeatedly and to make it approximately equal to the area of the source / drain region of the semiconductor element. In order to further reduce the pattern dependency of the flatness, it is preferable to keep the required pattern area density per unit area substantially constant.

However, in the logic LSI, it is difficult to keep the pattern area density per unit area constant because the sizes of the semiconductor elements in the same chip are not constant and the arrangement is not constant. Therefore, the average area of each source / drain region and one area of the island pattern, which is the basic unit for repeating the dummy pattern, are made substantially constant.

On the other hand, the pattern dependence of the flatness as described above in the CMP method changes depending on the polishing conditions of CMP, such as pressure, rotation speed, pad material, and type of polishing material. It is possible to give a width to the ratio of the average area per hit and the area of one of the island patterns defined by the dummy pattern. Actually, there is no problem if the ratio of the above areas is 0.5 or more and 2 or less.

That is, in the present invention, the ratio of the average area of the element region and the area of the basic unit of the repeating of the convex portion by the dummy pattern is set to 0.5 or more and 2 or less,
In this embodiment, the ratio of the average area of the source / drain regions 32 to the area of one of the island-shaped patterns 36 is
It should be 0.5 or more and 2 or less.

Instead of the average area of all the element regions, the average area of the element regions of the elements having the highest frequency of formation may be used.

In a semiconductor memory, since the memory cell portion occupies the largest area in the semiconductor chip, the area of the island pattern should be almost the same as the source / drain region portion constituting the memory cell. so,
The pattern area density per unit area is almost constant.

In this embodiment, the trench pattern 2
The presence of 6 electrically separates the n-well 34 and the p-well 35, and the width of the trench pattern 26 at the boundary between the n-well 34 and the p-well 35 can function as well-to-well separation. The minimum width is not less than that. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions. On the other hand, the maximum width is determined by the limit that does not cause digging due to polishing by the CMP method. Alternatively, the wiring formed on the trench pattern is determined within a range that does not cause a problem in the depth of focus even if digging occurs. This maximum width is
It goes without saying that it changes depending on the polishing conditions in the CMP method, such as pressure, rotation speed, pad material, and type of polishing material.

The trench pattern 25 under the wiring 41 functions as an insulator with the silicon substrate when the wiring 41 and the silicon oxide film 22 are in direct contact with each other. Therefore, as the features of the trench pattern 25, as shown in the structural cross-sectional view of the semiconductor device of FIG. 3A, the mask misalignment between the wiring pattern 41 and the trench pattern 25, the overlap capacitance between the wiring 41 and the silicon substrate, In consideration of the above, the width of the trench pattern 25 is wider than the width of the wiring 41.

Wiring pattern 41 and trench pattern 25
The alignment margin of 1 may have a width on one side that is equal to or larger than the maximum alignment shift amount of the mask. That is, the width of the trench pattern 25 is {(wiring width) + (2 which is the maximum misalignment amount).
)} Or more, the wiring 41 and the silicon substrate 11 do not come into contact with each other even if misalignment occurs as shown in FIG. It goes without saying that the alignment margin also changes depending on the semiconductor manufacturing process conditions and the like.

In this embodiment, the silicon oxide film is used as the film embedded in the trench pattern.
Other insulating films such as a silicon nitride film may be used. Also,
Different films such as a CVD oxide film and a thermal oxide film may be laminated and used.

The semiconductor device having the above structure has the following operational effects.

That is, when the CMP method is applied to the flattening of the trenches by the structure in which the dummy pattern having the regularity such that the distribution of the convex portions becomes uniform and the pattern area density becomes constant, The pattern dependency of the polishing rate can be reduced, and the effect of overetching the silicon oxide film 22 used for filling can be reduced.

Further, the flatness using a dry etching technique such as a resist etch back method instead of the CMP method can reduce the pattern dependence of the flatness.
By reducing the pattern dependence of the flatness, it becomes possible to completely flatten the trench and solve the problem of securing the depth of focus in the lithography process.

Furthermore, the structure in which the trench pattern 26 is present at the boundary between the n-well and the p-well results in n
The -well and the p-well are electrically completely separated, diffusion of impurities can be prevented, and device characteristics can be improved.

The trench pattern 25 under the wiring is
Considering the misalignment of the semiconductor mask and the overlap capacitance between the wiring and the silicon substrate, it is wider than the wiring width,
Even if there is no insulating film between the wiring and the trench pattern, there is no contact between the wiring and the silicon substrate due to misalignment. Furthermore, as in the conventional example, the misalignment prevents the trench pattern from existing immediately below the wiring, resulting in an increase in capacitance. There is no such thing.

In this embodiment, the dummy pattern 27 is used.
Is an array pattern of grooves, and the protrusions are formed in an island shape and a lattice shape, but it is a regular repeating pattern, and the distance between the protrusions and the area ratio satisfy the above conditions. For example, the shape or arrangement of the dummy patterns does not matter.
Further, it is also possible to carry out in the same manner in a state where the concavities and convexities are reversed, that is, when the dummy pattern 27 is an array pattern of holes scattered like holes. In this case, the convex portions defined by the dummy pattern are continuous, but the basic unit of repetition is the L-shaped portion A shown in FIG.

(Embodiment 2) FIG. 5 is a structural cross-sectional view of a main part of a semiconductor device according to Embodiment 2 of the present invention, and the same reference numerals are used for the portions corresponding to those of Embodiment 1 described above. Add a sign.

In the first embodiment described above, the silicon oxide film is used to fill the trench pattern, but in the second embodiment, polysilicon is used instead of the silicon oxide film.

That is, the trench patterns 21, 25,
26 and the dummy pattern 27 are filled with the polysilicon 72 and the silicon oxide film 71, and the upper portion of the trench pattern is covered with the silicon oxide film 73, so that the polysilicon 72 and the wiring 41 are not in direct contact with each other. Other configurations are the same as those in the first embodiment.

The presence of the silicon oxide films 71 and 73 around the polysilicon 72 is to prevent the characteristics of the element from deteriorating due to the diffusion of impurities in the polysilicon and to improve the insulating property.

Further, polysilicon has a better filling property than a silicon oxide film, and it is possible to fill a groove having a higher aspect ratio. Therefore, by using polysilicon for burying the trench pattern, the width of the trench pattern can be narrowed and the device can be further miniaturized.

(Third Embodiment) FIG. 6 is a cross-sectional view of a main part of a semiconductor device according to a third embodiment of the present invention, in which parts corresponding to those in the above-described first embodiment are designated by the same reference numerals. Attach.

In the third embodiment, an insulating film layer is present between the wiring 42 and the semiconductor substrate composed of the trench pattern and the active region 33.

That is, the silicon oxide film 74 is formed as an insulating film between the semiconductor substrate 11 and the wiring 42. Other configurations are the same as those in the first embodiment.

In the third embodiment, since the silicon oxide film layer 74 is formed on the semiconductor substrate 11 before the wiring is formed, the active region 33 is formed without detouring around the active region as compared with the above-described embodiments. The wiring 42 can be crossed over, and the effect that high integration of the device can be achieved is produced.

(Fourth Embodiment) Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings.

First, a method of manufacturing a semiconductor mask required to obtain a semiconductor device will be described with reference to FIGS.
explain.

In this embodiment, the active region forming mask, the gate electrode pattern forming mask, the wiring pattern forming mask, the n-well forming mask, and the grid-like dummy pattern forming data are automatically used by a computer. A trench pattern forming mask is produced so that all the trench patterns can be formed at once with one semiconductor mask.

The trench pattern forming mask is shown in FIG.
Computer processing is performed on the three semiconductor mask data of the active region forming mask of (a), the gate electrode pattern forming mask of FIG. 7 (b) and the wiring pattern forming mask of FIG. 7 (c) by the following procedure. It is automatically obtained by doing.

First, as a procedure 1, as shown in FIG. 8A, the active region 101 is enlarged graphically with a constant width to form a first intermediate mask region 102. The expansion width at this time is set to be equal to or larger than the minimum width capable of element isolation, and the maximum width is set to be equal to or smaller than a limit at which digging occurs by polishing by the CMP method. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.

Next, in step 2, as shown in FIG. 8B, the gate electrode pattern 201 is enlarged in a graphic form with a constant width to form a second intermediate mask region 202. The expansion width at this time is set to be equal to or more than the maximum mask misalignment amount that can occur.

As a procedure 3, as shown in FIG. 8C, the wiring pattern 301 is graphically enlarged with a constant width to form a third intermediate mask region 302. The expansion width at this time is set to be equal to or more than the maximum mask misalignment amount that can occur.

As procedure 4, as shown in FIG. 9A, the active region 101 is simply inverted in a graphic manner to form a fourth intermediate mask region 103.

The procedure 1, procedure 2, procedure 3, procedure 4 may be performed in any order.

Next, in step 5, as shown in FIG. 9B, the logical sum of the first intermediate mask region 102, the second intermediate mask region 202, and the third intermediate mask region 302 is calculated, A fifth intermediate mask region 401 is formed.

Next, in step 6, as shown in FIG. 10B, the n-well region 501 of FIG. 10A is enlarged graphically with a constant width to form a sixth intermediate mask region 502. Form.

As step 7, as shown in FIG. 11A, a seventh intermediate mask obtained by graphically reducing the n-well region 501 to a constant width from the sixth intermediate mask region 502. The region 503 is subtracted to obtain the eighth intermediate mask region 50.
4 is formed.

Here, the enlargement width and the reduction width in FIGS. 10B and 11A are the minimum width or more at which the n-well and the p-well can be electrically separated, and the maximum width is CMP. It is set below the limit at which digging occurs when polishing by the method. Needless to say, the minimum width is determined by the generation and characteristics of the semiconductor device and the semiconductor manufacturing process conditions.

As step 8, as shown in FIG. 11B, the fifth intermediate mask region 40 formed in FIG. 9B is formed.
The logical sum of 1 and the 8th intermediate mask area 504 is taken, and the 9th
Forming an intermediate mask region 411.

Next, as step 9, as shown in FIG. 12A, mask data of a lattice-shaped dummy pattern 601 in which dummy regions 602 are arranged in a lattice is prepared. Here, the area covered by the diagonal lines is the area surrounded graphically. In addition, A is a repeating basic unit of the above-described other embodiments. The pattern area density of the dummy pattern is constant in order to prevent pattern dependency of the polishing rate of CMP. Further, the area of the dummy region 602, that is, the area of the island pattern serving as the convex portion is equal to that of the active region pattern 10 shown in FIG.
It is desirable to make it the same as the area of 1.

As a procedure 10, as shown in FIG. 12B, the logical sum of the ninth intermediate mask region 411 formed in FIG. 11B and the lattice dummy pattern 601 is calculated,
A tenth intermediate mask region 421 is formed.

Next, in step 11, as shown in FIG. 13A, the logical product of the fourth intermediate mask region 103 and the twelfth intermediate mask region 421 formed in FIG. The intermediate mask region 422 is formed.

As the procedure 12, as shown in FIG. 13B, the eleventh intermediate mask region 422 is simply inverted in a graphic manner. The semiconductor mask data obtained at this time serves as a trench pattern forming mask, and the pattern 424, which is a blank portion in the drawing, serves as a trench pattern forming portion.

Although the case where the mask data for forming the n-well is used has been described here, the same operation can be performed by using the mask data for forming the p-well.

The semiconductor mask manufacturing method described here is an example in which a mask is manufactured according to a specific mask processing logical expression, and if the same logical expression is given, the same procedure can be applied even if the procedure is changed. It is possible to manufacture a semiconductor mask having the above structure.

An actual manufacturing process of a semiconductor device will be described using the semiconductor mask manufactured as described above.

First, as shown in FIG. 14A, a resist pattern 81 is formed on the silicon substrate 11 using the trench pattern forming mask produced as described above, and the trench pattern 21, Two
5, a dummy pattern 27 and a well separating trench pattern 26 are formed.

As the trench pattern forming mask, the element isolation trench pattern 2 arranged in the peripheral portion of the active region is formed.
1. Since all of the trench pattern 25 arranged under the wiring, the well separation trench pattern 26 formed at the boundary between the n-well and the p-well, and the dummy pattern 27 which is a lattice-shaped trench pattern are drawn. A desired trench pattern is formed once. Further, the trench pattern 25 formed at this time corresponds to the wiring 4 to be formed later.
It is wider than the width of 1.

Next, as shown in FIG. 14B, a silicon oxide film 23 is deposited as an insulating film on the trench patterns 21, 25 and 27. Here, the silicon oxide film 23 needs to be deposited thicker than the depth of the trench pattern.

Then, as shown in FIG.
The silicon oxide film 23 is polished by the CMP method. Polishing is continued until the surface of the silicon substrate is exposed, and the state shown in FIG.

Next, as shown in FIG. 14E, a transistor including a gate electrode 31, a source / drain region 32 and the like and a wiring 41 are formed by a well-known technique, and the semiconductor device of the above-described embodiment is formed. I will get it.

According to the manufacturing method of this embodiment, since the lattice-shaped dummy patterns are arranged so that the pattern area density is substantially constant, the CMP as in the conventional example is performed.
It is possible to prevent the pattern dependence of the flatness such as the digging of the recess of the trench pattern by the method, to prevent the pattern dependence of the polishing rate, and reduce the over-etching amount of the insulating film used for filling when polishing. Therefore, a surface state having no step can be obtained after polishing. Therefore, a sufficient depth of focus can be ensured in the lithography process, which facilitates miniaturization of the device.

The trench pattern forming mask in this embodiment is automatically prepared from the mask data such as the active region forming mask, the gate electrode pattern forming mask, the wiring pattern forming mask, the well forming mask and the dummy dummy pattern data. To be done. Therefore, it is not necessary to newly input a mask for forming the trench pattern. Therefore, it can be directly applied to the semiconductor mask data that has been owned in the past, and the past assets can be effectively used.

Further, in manufacturing the semiconductor device of the present invention, it is sufficient to replace the conventional active region forming mask with a trench pattern forming mask, and no new process is added.

As for the method of manufacturing the semiconductor device of the embodiment shown in FIG. 5, the manufacturing method of this embodiment is different from the method of manufacturing the semiconductor device in the step of depositing a stacked film of polysilicon and a silicon oxide film.
This can be carried out only by adding the step of forming an oxide film on polysilicon, and regarding the method of manufacturing the semiconductor device of the embodiment shown in FIG. 6, the manufacturing method of this embodiment includes an insulating film deposition step. It can be implemented just by adding
Both can achieve the same effect as this embodiment.

(Fifth Embodiment) Next, a method of manufacturing a semiconductor device according to another embodiment of the present invention will be described with reference to the drawings.

First, in the same manner as in the above-mentioned fourth embodiment,
A semiconductor mask, that is, a trench pattern forming mask is manufactured.

Next, as shown in FIG. 15A, a resist pattern 81 is formed on the silicon substrate 11 using the prepared trench pattern forming mask, and the trench patterns 21 and 25 and the dummy pattern are formed by dry etching. 27, a well isolation trench pattern 26 is formed. As the trench pattern forming mask, the element isolation trench pattern 21 arranged in the peripheral portion of the active region, the trench pattern 25 arranged under the wiring, the n-well and the p-type are formed.
Since the well separating trench pattern 26 and the dummy pattern 27, which is a lattice-shaped trench pattern, are all formed on the well boundary portion, a desired trench pattern is formed at one time. The trench pattern 25 formed at this time is wider than the width of the wiring 41 formed later.

Next, as shown in FIG. 15B, a silicon oxide film 23 is deposited as an insulating film on the trench patterns 21, 25, 26 and 27. Here, the silicon oxide film 23 is
It should be deposited thicker than the depth of the trench pattern.

Then, as shown in FIG.
A planarizing resist 82 is applied to planarize the surface. If the maximum width of the trench pattern is 1 to 1.5 μm, complete flattening is possible only by the silicon oxide film deposition conditions and the resist coating conditions. If a trench pattern having a wide width of 2 μm or more exists, a resist block may be formed in the surface recess before applying the planarizing resist.

Next, as shown in FIG. 15D, the silicon oxide film 23 and the flattening resist 82 are etched back using a dry etching technique in which the etching rates are equal.

Then, as shown in FIG.
The transistor including the gate electrode 31, the source / drain region 32, and the like and the wiring 41 are formed by a known technique to obtain the semiconductor device of the above-described embodiment.

According to the manufacturing method of this embodiment, since the lattice-shaped dummy patterns are arranged so that the pattern area density is substantially constant, the film thickness variations of the silicon oxide film 23 and the planarizing resist 82 are not uniform. Since the pattern aperture ratio per unit area is constant in the plane of the semiconductor substrate, the dependence of the etching rate on the pattern aperture ratio can be prevented.

Therefore, even with the etch back method using the dry etching technique, complete flattening without pattern dependence can be realized, a sufficient depth of focus in the lithography process can be secured, and the device can be easily miniaturized.

Regarding the method of manufacturing the semiconductor device of the embodiment shown in FIG. 5, the method of manufacturing the semiconductor device of this embodiment is different from the method of manufacturing the semiconductor device in this embodiment in that
This can be carried out only by adding the step of forming an oxide film on polysilicon, and regarding the method of manufacturing the semiconductor device of the embodiment shown in FIG. 6, the manufacturing method of this embodiment includes an insulating film deposition step. It can be implemented just by adding
Both can achieve the same effect as this embodiment.

In each of the above-described embodiments, the description has been made by applying it to the MOS transistor.
Of course, not only the OS transistor but also other elements can be similarly applied.

[0105]

As described above, according to the present invention, a dummy pattern, which is a repetitive pattern having regularity, is formed so that the distribution of convex portions is uniform and the pattern area density is substantially constant. It is possible to reduce the dependency, it is possible to form a trench pattern that achieves complete flattening without steps on the surface, which improves the depth of focus in the lithography process and contributes to miniaturization of the element, Even if a dry etching technique is applied for flattening, complete flattening without pattern dependence can be realized.

Further, in the trench pattern under the wiring, even if misalignment of the semiconductor mask occurs, since the trench pattern always exists under the wiring, the parasitic capacitance between the wiring and the substrate can be reduced, and the semiconductor pattern can be reduced. It can also contribute to speeding up of the device.

[Brief description of the drawings]

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a plan view of a main part of the semiconductor device of FIG. 1 with a dummy pattern removed.

3A and 3B are an enlarged structural sectional view and a plan view of a main part of FIG.

FIG. 4 is a structural cross-sectional view showing misalignment of a semiconductor mask.

FIG. 5 is a structural cross-sectional view of a semiconductor device according to a second embodiment of the present invention.

FIG. 6 is a structural cross-sectional view of a semiconductor device according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a method of manufacturing a semiconductor mask in a method of manufacturing a semiconductor device according to the present invention.

FIG. 8 is a diagram showing a method of manufacturing a semiconductor mask in the method of manufacturing a semiconductor device according to the present invention.

FIG. 9 is a diagram showing a method of forming a semiconductor mask in the method of manufacturing a semiconductor device of the present invention.

FIG. 10 is a diagram showing a method of forming a semiconductor mask in the method of manufacturing a semiconductor device of the present invention.

FIG. 11 is a diagram showing a method of forming a semiconductor mask in the method of manufacturing a semiconductor device of the present invention.

FIG. 12 is a diagram showing a method of forming a semiconductor mask in the method of manufacturing a semiconductor device of the present invention.

FIG. 13 is a diagram showing a method for forming a semiconductor mask in the method for manufacturing a semiconductor device of the present invention.

FIG. 14 is a structural cross-sectional view showing the method of manufacturing a semiconductor device according to the fourth embodiment of the present invention.

FIG. 15 is a structural cross-sectional view showing the method of manufacturing a semiconductor device according to the fifth embodiment of the present invention.

FIG. 16 is a structural cross-sectional view showing a manufacturing method of a conventional example.

FIG. 17 is a structural cross-sectional view of a conventional semiconductor device.

FIG. 18 is a structural cross-sectional view showing misalignment of a semiconductor mask.

[Explanation of symbols]

 11 Silicon Substrate 21, 25, 26 Trench Pattern 27 Dummy Pattern 22-24, 71, 73-75 Silicon Oxide Film 31 Gate Electrode 32 Source / Drain 33 Active Region 34 n-Well 35 p-Well 36 Island Pattern 41, 42 Wiring 61 Polishing pad 81 Resist pattern 82 Flattening resist

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsunari Yamanaka 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (14)

[Claims] 1. A semiconductor device in which an element is formed in each of a plurality of element regions separated by a trench pattern, wherein a groove or a hole is formed in a region other than the element region and excluding the trench pattern. A dummy pattern, which is an array pattern of, is formed, and the convex portions defined by the dummy pattern are present in a repeating manner with regularity, and the distance between adjacent convex portions is 10 μm or less and The ratio of the average area of the element region to the area of the basic unit of repeating the convex portion is 0.5 or more and 2 or less, and the trench pattern and the dummy pattern are buried with an insulating film. Characteristic semiconductor device. 2. The semiconductor device according to claim 1, wherein the required element regions are all element regions of the plurality of element regions. 3. The semiconductor device according to claim 1, wherein the required element region is an element region of an element that is most frequently formed. 4. The semiconductor device according to claim 1, wherein the dummy pattern has a regular lattice shape. 5. A well isolation trench pattern is formed at a boundary between an n-well and a p-well in a region where the dummy pattern is formed, and the well isolation trench pattern is formed in the insulating film. The semiconductor device according to claim 1, wherein the semiconductor device is buried in. 6. An under-wiring trench pattern is formed in a region in which the dummy pattern is formed, and the under-wiring trench pattern is buried in the insulating film, and the wiring is formed on the insulating film. The semiconductor device according to claim 1, wherein a wiring having a width narrower than that of the lower trench pattern is formed. 7. The semiconductor device according to claim 1, wherein the insulating film is a laminated film. 8. A mask pattern forming step for forming a mask pattern for simultaneously forming at least two patterns of a trench pattern surrounding each of the peripheral portions of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes. An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, an insulating film depositing step of depositing an insulating film, and a chemical mechanical polishing method to form the insulating film. A polishing step of polishing and flattening, and an element forming step of forming an element in the element region, wherein the dummy pattern is formed in a region other than the element region and excluding the trench pattern. The dummy pattern is divided by the dummy pattern. With protrusions made is present in repeated with regularity, the distance between adjacent convex portions is 1
The ratio of the average area of the required element region that is 0 μm or less and the area of the basic unit of repeating the convex portion is
A method of manufacturing a semiconductor device, which is 0.5 or more and 2 or less. 9. A mask pattern forming step for forming a mask pattern for simultaneously forming at least two patterns, that is, a trench pattern surrounding each peripheral portion of a plurality of element regions and a dummy pattern which is an array pattern of grooves or holes. An etching step of simultaneously forming at least the trench pattern and the dummy pattern by dry etching using the mask pattern as a mask, an insulating film depositing step of depositing an insulating film, and a planarizing material forming of a planarizing material. A step of etching back the insulating film and the planarizing material by a dry etching technique, and an element forming step of forming an element in the element region, wherein the dummy pattern is formed in a region other than the element region. Formed in a region other than the trench pattern. Is what is, the dummy pattern is a convex portion that is partitioned and formed by the dummy pattern, as well as present in repeatedly with regularity, the distance between adjacent convex portions is 1
The ratio of the average area of the required element region that is 0 μm or less and the area of the basic unit of repeating the convex portion is
A method of manufacturing a semiconductor device, which is 0.5 or more and 2 or less. 10. The method of manufacturing a semiconductor device according to claim 8, wherein the required element regions are all element regions of the plurality of element regions. 11. The method of manufacturing a semiconductor device according to claim 8, wherein the required element region is an element region of an element that is most frequently formed. 12. The mask pattern in the mask pattern forming step is for simultaneously forming a well separating trench pattern for an n-well and a p-well in a region where the dummy pattern is formed, 12. The method for manufacturing a semiconductor device according to claim 8, wherein in the etching step, at least the trench pattern, the dummy pattern, and the well isolation trench pattern are simultaneously formed by dry etching. 13. The mask pattern in the mask pattern forming step is for simultaneously forming an under-wiring trench pattern in a region where the dummy pattern is formed, and the etching step is performed by dry etching. , At least the trench pattern, the dummy pattern and the wiring lower trench pattern are formed at the same time, on the insulating film in which the wiring lower trench pattern is buried, than the width of the wiring lower trench pattern A wiring forming step for forming a wiring having a narrow width is provided.
3. The method for manufacturing a semiconductor device according to any one of 2. 14. The method of manufacturing a semiconductor device according to claim 8, further comprising a laminated film forming step of forming a laminated film made of different films in the trench pattern and the dummy pattern.