JP2014187377A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To raise precision of a resistance value for improved reliability by forming a resistive element of a required shape on an element separation oxide film.SOLUTION: In the semiconductor device, a plurality of resistive elements 4 are formed on an element separation oxide film 2 in a predetermined region formed on the surface of a semiconductor substrate 1. An active region 3 is provided at the position close to the resistive element 4. The element separation oxide film 2 near the resistive element 4 can be partitioned to be a required range. A recess is suppressed from being formed at the central part of the element separation oxide film 2 when polishing the element separation oxide film 2 by CMP method, resulting in improved dimension precision in the shape of the resistance element 4.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and is particularly suitable for application to a semiconductor device having a resistance element.

  Resistive elements used in semiconductor devices are roughly classified into diffused resistors using a diffusion layer formed on the surface of a semiconductor substrate and polyresistors using a polycrystalline silicon film. Among these, a resistance element by polyresistor is often formed on an element isolation film on a semiconductor substrate.

  FIG. 13 is a schematic view showing an example in which a resistance element is formed on an element isolation oxide film using a gate layer. Here, FIG. 13A is a plan view of a semiconductor device in which a resistance element is formed, and FIGS. 13B and 13C are cross sections taken along the alternate long and short dash line IV-IV in FIG. It is a schematic diagram which shows.

  With miniaturization, recently, element isolation is generally performed by a shallow trench (STI) method using a CMP (chemical mechanical polishing) method. Also in the semiconductor device shown in FIG. 13, element isolation of the semiconductor substrate 101 is achieved by the element isolation oxide film 102 formed by the STI method. The formation of the element isolation oxide film 102 by the STI method is performed by forming a groove in the semiconductor substrate 101 by etching, depositing an insulating film such as a silicon oxide film on the entire surface, and filling the groove, and by performing a CMP method on the semiconductor substrate in a region other than the groove This is performed by polishing and removing an excess insulating film on 101.

  In the semiconductor device of FIG. 13, a plurality of resistance elements 104 are formed on the element isolation oxide film 102 after the element isolation oxide film 102 is formed. Each resistance element 104 is further connected to the upper wiring layer 105 via the contact layer 106 in the subsequent wiring formation process. The size of the resistance element 104 is about the total length (L) = 100 μm, and since it is necessary to form a large number of resistance elements 104 on the semiconductor substrate 101, a vast element isolation oxide film 102 is formed, and a large number of them are formed thereon. The resistor elements 104 are collectively formed.

  The resistance value of the resistance element 104 thus formed depends on various factors such as the pattern width, the total length of the element, the thickness, the film growth method, the concentration of impurities to be added, the profile in the thickness direction, and the heat treatment. It is determined by.

  However, if the element isolation oxide film 102 is formed with a large area, the amount of polishing by the CMP method increases from the periphery of the element isolation oxide film 102 toward the center, so that the thickness of the element isolation oxide film 102 in the center is increased. The problem that becomes thin. This is due to a so-called dishing phenomenon in the planarization technique in the CMP method, and this phenomenon forms a recess as shown in FIG. 13C in the central portion of the element isolation oxide film 102. End up.

  When the resistance element 104 is formed on the element isolation oxide film 102 in which the recess is formed, a shape is formed between the resistance element 104 formed in the central portion of the element isolation oxide film 102 and the resistance element 104 formed in the peripheral portion. The above difference will occur.

  The difference in shape is as follows: (1) Since a polycrystalline silicon film, which is a material of the resistance element 104, is formed on the element isolation oxide film 102 in which the depression is formed, the central part is formed thicker than the peripheral part. (2) a difference in width of the resistance element 104 due to a difference in height position where the resistance element 104 is formed, and (3) a difference in cross-sectional shape of the resistance element. Such a difference in shape increases as the width of the element isolation oxide film 102 increases.

FIG. 14 shows the relationship (solid line) of the height position (H) of the central portion of the element isolation oxide film 102 with respect to the width of the element isolation oxide film 102 and the shift of the overall length of the resistance element 104 with respect to the width of the element isolation oxide film 102. It is a characteristic view which shows the relationship (dotted line) with quantity (L _shift ). As shown in FIG. 14, as the width of the element isolation oxide film 102 increases, the height position of the element isolation oxide film 102 decreases and the shift amount of the dimension also increases. When the width of the element isolation oxide film 102 is 100 μm, the shift amount of the overall length of the resistance element 104 reaches 13%, and as a result, the shift amount of the resistance value also becomes 13%.

  Thus, in the conventional method, since the shape of the resistance element 104 on the element isolation oxide film 102 cannot be kept constant, a difference occurs in the resistance value of the resistance element 104, and the required accuracy is high as in an analog circuit. It has been difficult to apply to circuits.

  The present invention has been made to solve the above-mentioned problems. The first object is to form a resistance element having a desired shape on the element isolation oxide film, thereby improving the accuracy of the resistance value and increasing the reliability. An object is to provide a semiconductor device with improved performance.

  A second object is to provide a semiconductor device suitable for miniaturization by improving the arrangement efficiency of a region where a resistance element is formed.

A semiconductor device of the present invention includes a semiconductor substrate,
An active region disposed on a main surface of the semiconductor substrate;
An isolation region made of an oxide film buried in a groove disposed on the main surface of the semiconductor substrate,
The separation region includes a first separation region and a second separation region, and the first separation region and the second separation region are short sides of the separation regions perpendicular to the longitudinal direction of the separation regions. Are placed next to each other in parallel,
The active region includes a first active region disposed between the first and second isolation regions, and the first active region facing the first active region along the short direction of the respective isolation regions. A second active region disposed adjacent to one another with one isolation region interposed therebetween, and the second isolation region sandwiching the second isolation region along the short direction of each of the isolation regions facing the first active region Including a third active region disposed adjacent to each other;
Each of the separation regions includes a resistance element disposed one by one along the longitudinal direction of the separation region,
Each of the isolation regions under the resistor element is defined to have a predetermined width by the respective active regions.
The present invention can also be expressed as follows.
The semiconductor device according to the present invention includes a semiconductor substrate, an active region disposed on the main surface of the semiconductor substrate, and an oxide film buried in a groove disposed on the main surface of the semiconductor substrate disposed in the active region. A plurality of separation regions, each of the separation regions, and one resistive element arranged along the longitudinal direction of the separation region,
The isolation region below the resistive element is defined to have a predetermined width by the active region;
The plurality of separation regions include a first separation region and a second separation region disposed adjacent to each other in parallel with each other in a short direction of the separation region perpendicular to the longitudinal direction of the separation region,
A first active region disposed between the first and second isolation regions, and disposed adjacent to each other across the first isolation region along a short direction of the first active region and the isolation region A second active region formed;
A third active region is provided, which is disposed adjacent to the first active region and the separation region along the short direction of the second separation region.

  The semiconductor device according to the present invention is characterized in that, in the semiconductor device, the resistance elements are evenly arranged with a certain length, width and film thickness.

  The semiconductor device according to the present invention is characterized in that, in the semiconductor device, the resistance element is formed inside each of the isolation regions.

  The semiconductor device according to the present invention is characterized in that, in the semiconductor device, each of the isolation regions below the resistance element is defined to be 20 μm or less by the active region.

In addition, in the semiconductor device manufacturing method of the present invention, in a predetermined region on the semiconductor substrate, the insides of the plurality of rectangular regions arranged are removed by etching, and the grooves are perpendicular to the longitudinal direction of the grooves. A first step of disposing first and second grooves disposed adjacent to each other in parallel;
A second step of depositing an insulating film on the semiconductor substrate and embedding the first and second grooves;
The surface of the insulating film is polished, the insulating film in a region other than the groove is removed, and the surface of the insulating film on the first and second grooves is flattened to be in the first and second grooves. First and second insulating films are formed, a first active region disposed between the first and second insulating films, and the first active region and the insulating film along the short direction of the insulating film A second active region is disposed adjacent to the first insulating film, and is adjacent to the first active region along the short direction of the insulating film with the second insulating film interposed therebetween. A third step of disposing a third active region, and disposing first to third active regions defining the first and second insulating films to a predetermined width;
A fourth step of disposing a conductive film made of a material having a predetermined resistance value on the semiconductor substrate;
The method includes a fifth step of patterning the conductive film on the insulating film to dispose a resistance element.

  The semiconductor device manufacturing method according to the present invention is characterized in that, in the fifth step, the resistance elements are uniformly arranged with a certain length, width and film thickness.

  The semiconductor device manufacturing method of the present invention is characterized in that, in the fifth step, the resistance element is formed inside the insulating film.

  In the method of manufacturing a semiconductor device according to the present invention, in the third step, the insulating film below the resistance element on the insulating film is defined to be 20 μm or less by the active region. To do.

  Since the present invention is configured as described above, the following effects can be obtained.

  By providing an active region at a position close to the resistive element, the insulating film in the vicinity of the resistive element can be divided into the required range, and a recess is formed in the central part of the insulating film when polishing the insulating film by the CMP method. Therefore, it is possible to improve the dimensional accuracy of the shape of the resistance element and increase the reliability of the resistance value.

  By using the element isolation film formed by the shallow trench method as the insulating film, the flatness of the polishing of the insulating film by the CMP method can be improved.

  A plurality of resistive elements are arranged side by side on the insulating film, and the width of the insulating film below each resistive element is regulated to a predetermined width by the active region, thereby dividing the insulating film near each resistive element into a necessary range. be able to.

  By defining the predetermined width of the insulating film based on the shift amount of the resistance value of the resistance element that changes due to the width of the insulating film, the shift amount of the resistance value can be set to a desired value. .

  By providing the dummy gate electrode in the region including on the active region, it is possible to prevent the pattern of the resistive element from being isolated, and the shape of the resistive element can be formed with high accuracy.

  The area of the dummy gate electrode is formed wider than the area of the active region, and by completely covering the active region with the dummy gate electrode, it is possible to achieve stabilization of the shape of the dummy gate electrode. Can be formed with higher accuracy.

  By forming a plurality of dummy gate electrodes on one active region, the resistance element and the dummy gate electrode can be brought close to each other even when the area of the active region is relatively large. In addition, it is possible to pass the gate wiring between the dummy gate electrodes on the active region.

  By setting the distance between the resistance element and the dummy gate electrode to the same value in the plurality of resistance elements, the resistance value of each resistance element can be made uniform while the process conditions are optimized.

  By forming a plurality of resistance elements between adjacent active regions, the arrangement efficiency of the resistance elements can be improved.

  By setting the distance between the plurality of resistance elements formed between adjacent active regions to the minimum value of the distance between the patterns formed on the semiconductor substrate, the resistance conditions of the resistance elements are optimized. Patterning can be performed.

  By causing the active region to reach the vicinity of the end in the longitudinal direction of the resistance element and surrounding the periphery of the resistance element with the active region, the insulating film on which the resistance element is formed can be formed into an island-like pattern. The flatness of the insulating film surface during polishing by the method can be further improved.

  By causing the dummy gate electrode to reach the vicinity of the end in the longitudinal direction of the resistance element and surrounding the resistance element with the dummy gate electrode, the shape of the resistance element can be formed with high dimensional accuracy.

  The resistive element is composed of a polycide structure laminated film made of a polycrystalline silicon film and a silicide film, and the silicide film is selectively removed on the upper surface of the resistive element, thereby using a polycide structure gate layer as a gate layer. Even if it exists, the resistance element which has a desired resistance value can be formed.

  By forming the dummy gate electrode from a polycide structure laminated film made of a polycrystalline silicon film and a silicide film, it is possible to achieve stabilization of the shape of the resistance element even when a polycide structure gate layer is used. .

  By introducing a predetermined impurity into the active region and connecting the contact layer, and functioning the active region as a diffusion layer resistance element, the diffusion layer resistance element can be disposed in the vicinity of the resistance element on the element isolation film, The arrangement efficiency of the resistance element can be increased.

  By arranging the active region in the vicinity of both ends in the longitudinal direction of the resistance element and extending in the direction perpendicular to the direction in which the resistance element extends, it is possible to arrange the diffusion layer resistance element by effectively utilizing the space. it can.

  A wiring film having a predetermined pattern is formed on the upper layer of the resistance element, and the ratio of the area of the resistance element to the area of the area where the resistance element and the wiring film overlap on the resistance element is made almost constant in each resistance element. Thus, it is possible to prevent the uniformity of the resistance value of the resistance element from being impaired due to the influence of the wiring layer.

  Since the resistor element is formed of the same layer as the gate electrode of the MOS transistor, the resistor element can be formed simultaneously with the gate formation.

1 is a schematic diagram showing a semiconductor device according to a first embodiment of the present invention. It is a schematic diagram which shows the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 2 of this invention. It is a schematic diagram which shows the semiconductor device which concerns on Embodiment 3 of this invention. It is a schematic diagram which shows another example of the semiconductor device which concerns on Embodiment 3 of this invention. It is a schematic diagram which shows the semiconductor device which concerns on Embodiment 4 of this invention. It is a schematic diagram which shows the conventional semiconductor device. It is a characteristic view showing the relationship between the height position of the central portion of the element isolation oxide film and the shift amount of the overall length of the resistance element with respect to the width of the element isolation oxide film.

Hereinafter, several embodiments of the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a schematic view showing a semiconductor device according to the first embodiment of the present invention. FIG. 1A is a plan view showing a planar configuration of the semiconductor device according to the first embodiment, and FIG. FIG. 2 is a schematic cross-sectional view showing a cross section taken along one-dot chain line II in FIG.

  First, the configuration of the semiconductor device according to the first embodiment will be described with reference to FIG. In the semiconductor device shown in FIG. 1, an element isolation oxide film 2 is formed on a surface region of a semiconductor substrate 1 by an STI method, and a rectangular resistance element having a width W using a gate layer of a MOS transistor on the element isolation oxide film 2. 4 is formed. As a material of the resistance element 4, for example, a polycrystalline silicon film which is a material of the gate layer can be used. And as shown to Fig.1 (a), the element active region 3 is formed so that it may adjoin to the left and right of the width direction of each resistance element 4. As shown in FIG. Therefore, the element isolation oxide film 2 is partitioned by the element active regions 3 formed corresponding to the individual resistance elements 4, and the width thereof is defined to a predetermined value.

The resistance element 4 is covered with an interlayer insulating film (not shown), and the wiring layer 5 formed on the interlayer insulating film is connected to the resistance element 4 via the contact layer 6 as shown in FIG. Connected to both ends. In FIG. 1, one contact layer 6 that connects the resistor element 4 and the wiring layer 5 is shown in a simple manner, but preferably a number of contact layers whose contact resistance is equal to or less than an allowable variation of the resistor element 4. 6 is desirable. That is, it is desirable that the number of contact layers 6 satisfy the following formula.
(One resistance value of contact layer 6) / (number of contact layers 6) ≦ allowability × (resistance value of resistance element 4)

Thus, the element isolation region 2 is formed by forming the element active region 3 corresponding to the resistance element 4 and setting the width (W _sti ) of the element isolation oxide film 2 to the minimum necessary width. It is possible to prevent the recess from being formed due to the thinning of the film thickness at the central portion of the element isolation oxide film 2 due to the CMP polishing.

Since the element active region 3 plays a role of defining the width of the element isolation oxide film 2 and dividing the element isolation oxide film 2 into a strip shape, the width (W _a ) of the element active region 3 is not particularly limited. As the width of the element active region 3 is smaller, more resistor elements 4 can be arranged in the same range, and the efficiency of arranging the resistor elements 4 is improved. Therefore, the width of the element active region 3 is reduced to the minimum width that can be created. It is desirable to keep it narrow.

In addition, the width (W _sti ) of the element isolation oxide film 2 is preferably specified to be equal to or less than the dimensional shift amount allowed from the function of the resistance element 4, and this width is based on, for example, the measurement result shown in FIG. Can be determined. Thereby, the shift amount of the resistance value of the resistance element 4 can be suppressed to a desired value or less, and the resistance value of the resistance element 4 can be set within a design allowable range.

Next, a method for manufacturing the semiconductor device of the first embodiment will be described. First, the element isolation oxide film 2 is formed on the semiconductor substrate 1 by the STI method. Specifically, a groove is formed in a predetermined region on the semiconductor substrate 1 by etching, an insulating film such as a silicon oxide film is deposited on the entire surface to fill the groove, and the semiconductor substrate 1 in a region other than the groove is formed by CMP. The excess insulating film is polished and removed, thereby forming an element isolation oxide film 2 that fills a predetermined region of the semiconductor substrate 1. At this time, in the region where the resistance element 4 is formed, the element isolation oxide film 2 is formed by arranging the element active region 3 so that the width of the element isolation oxide film 2 is equal to or less than W _sti .

  Next, a polycrystalline silicon film is formed so as to cover the semiconductor substrate 1. Impurities are added to the polycrystalline silicon film to ensure predetermined conductivity. Thereafter, the polycrystalline silicon film is patterned by photolithography and subsequent dry etching, and the resistance element 4 made of this polycrystalline silicon film is formed on the element isolation oxide film 2. Simultaneously with the patterning of the resistance element 4, the gate electrode made of the polycrystalline silicon film is patterned in the formation region of the MOS transistor.

  Thereafter, an interlayer insulating film covering the resistance element 4 is formed, contact holes reaching both ends of the resistance element 4 are opened, a contact layer 6 filling the contact hole is formed, and wiring connected to the contact layer 6 The semiconductor device shown in FIG. 1 is completed by forming the layer 5 on the interlayer insulating film and patterning it.

  As described above, in the first embodiment, the resistance element 4 is formed on the element isolation oxide film 2, and the element active region 3 is formed so as to be adjacent to the left and right in the width direction of the resistance element 4. The element isolation oxide film 2 in the region where the resistance element 4 is formed can be divided into strips according to the resistance element 4. As a result, the width of the element isolation oxide film 2 can be regulated to the minimum necessary width, and the flatness of the surface of the element isolation oxide film 2 can be greatly improved during polishing by the CMP method. Therefore, it is possible to form the resistance element 4 having a desired resistance value having a stable shape in the element isolation oxide film 2, and the resistance value of each resistance element 4 can be set uniformly.

Further, by setting the width (W _sti ) of the element isolation oxide film 2 to be equal to or smaller than the dimension shift amount allowed from the function of the resistance element 4, the resistance value of the resistance element 4 can be kept within the design value. It becomes possible to improve the reliability of a semiconductor device having a strict requirement accuracy of a resistance value such as an analog circuit.

Embodiment 2. FIG.
FIG. 2 is a schematic diagram showing a semiconductor device according to the second embodiment of the present invention. FIG. 2A is a plan view showing a planar configuration of the semiconductor device according to the second embodiment, and FIG. These are schematic sectional drawings which show the cross section along the dashed-dotted line II-II of Fig.2 (a).

  In the semiconductor device of the second embodiment, the element active regions 3 provided on the left and right in the width direction of each resistance element 4 define the width of the element isolation oxide film 2 in the same manner as the semiconductor device of the first embodiment. It is the same. The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that dummy gate electrodes 7 are provided on the element active regions 3 on both sides of the resistance element 4 as shown in FIG. Is different. In the following description of each embodiment, the same components as those in the semiconductor device according to the first embodiment shown in FIG.

  As shown in FIG. 2, the shape and size of the dummy gate electrode 7 formed on the element active region 3 are substantially the same as those of the resistance element 4. As shown in FIG. It is narrower than the width of the active region 3 and is arranged substantially in parallel with the resistor element 4 so as to straddle the element isolation oxide film 2 from the element active region 3.

  The dummy gate electrode 7 is formed using the same layer as the gate layer of the MOS transistor in the MOS transistor formation region, like the resistance element 4. Therefore, the dummy gate electrode 7 is formed on the element active region 3 via the gate oxide film.

  As shown in FIG. 2A, the dummy gate electrodes 7 and the resistance elements 4 in the plurality of resistance elements 4 are separated by the same gate interval S. Then, by aligning the gate intervals S of the plurality of resistance elements 4 having the same resistance value to the same value, the resistance values of the respective resistance elements 4 can be aligned to the same value. More preferably, the gate interval S is set to a value close to the minimum value of the interval between the patterns formed on the semiconductor substrate 1.

  In a normal semiconductor device manufacturing process, process conditions are optimized based on the minimum pattern interval. Therefore, as the gate interval S increases, the process conditions are not met and the dimensional accuracy of the pattern of the resistive element 4 deteriorates. . In the second embodiment, since the gate interval S is set to a value close to the minimum value, the dimensional accuracy of the shape of the resistance element 4 and the dummy gate electrode 7 can be maintained with high accuracy.

  Since the dummy gate electrode 7 is not used as a resistance element, but exclusively for increasing the accuracy of the shape of the resistance element 4, the potential of the dummy gate electrode 7 is fixed to the ground potential in order to reduce noise components. . The potential of the element active region 3 below the dummy gate electrode 7 is preferably set to the same potential as that of the well. A contact is connected to the same potential as the well, or the same conductivity type as the well. As it is formed.

  Next, another example of the semiconductor device of the second embodiment will be described based on the plan view of FIG. In the semiconductor device shown in FIG. 3, when the width of the element active region 3 formed between the resistor elements 4 is relatively large, the dummy gate electrode 7 on the element active region 3 is replaced with the resistor element 4 on the element isolation oxide film 2. The example provided so that it may adjoin to is shown.

  In this way, the shape degradation of the resistance element 4 can be suppressed by bringing the dummy gate electrode 7 close to the resistance element 4 without being restricted by the width and size of the element active region 3, and a plurality of resistances By setting the distance between the dummy gate electrode 7 and the resistance element 4 in the element 4 to the same gate distance S, it is possible to improve the dimensional accuracy of each resistance element 4 in accordance with the process conditions. More preferably, the resistance value of each resistance element 4 is set to the same value by setting the distance between the dummy gate electrode 7 and the resistance element 4 in the plurality of resistance elements 4 having the same resistance value to the same gate distance S. be able to. In addition, the gate wiring can be passed between the dummy gate electrodes 7 on the element active region 3.

  Next, still another example of the semiconductor device of the second embodiment will be described based on the plan view of FIG. The semiconductor device of FIG. 4 shows an example in which a dummy gate electrode 7 is provided on the element active region 3 and a plurality of resistance elements 4 are arranged on the element isolation oxide film 2. Also in this case, the distance between the resistance element 4 and the dummy gate electrode 7 in the plurality of resistance elements 4 is set to the same gate distance S, and the distance between the resistance elements 4 on the element isolation oxide film 2 is also the same. It is desirable that the gate interval S be set to a predetermined value. More preferably, in the plurality of resistance elements 4 having the same resistance value, the resistance of each resistance element 4 is set by setting the distance between the resistance element 4 and the dummy gate electrode 7 or the resistance element 4 to the same gate distance S. The value can be set to the same value.

  In this way, the resistance element 4 is formed on the element isolation oxide film 2 in the vicinity of the resistance element 4 and the resistance element 4 and the dummy gate electrode 7 are brought close to each other, thereby making the wiring structure in the vicinity of the resistance element 4 uniform. And an arrangement suitable for improving accuracy can be performed. Preferably, the distance between the resistance element 4 and the adjacent resistance element 4 or dummy gate electrode 7 is set to the same gate distance S in each resistance element 4, and the left and right (upper and lower) sides of the resistance element 4 are arranged symmetrically. Thus, matching accuracy can be improved, and the resistance value can be set to the same value while keeping the shape of each resistance element 4 with high accuracy. In the example of FIG. 4, even when a plurality of resistance elements 4 are formed on the element isolation oxide film 2, the dimensional accuracy of each resistance element 4 can be kept high. Further, by arranging a plurality of resistance elements 4 on the element isolation oxide film 2, the arrangement efficiency of the resistance elements 4 can be increased.

  Next, still another example of the semiconductor device of the second embodiment will be described with reference to FIG. The semiconductor device of FIG. 5 shows an example in which a dummy gate electrode 7 having a width wider than the width of the element active region 3 is provided on the element active region 3 and the element active region 3 is completely covered with the dummy gate electrode 7. . Here, FIG. 5A is a plan view showing a planar configuration of the semiconductor device, and FIG. 5B is a schematic sectional view showing a cross section taken along the alternate long and short dash line III-III in FIG. is there.

  In the overlap of the element active region 3 and the dummy gate electrode 7, if the element active region 3 is exposed or not exposed, the shape stability of the dummy gate electrode 7 cannot be obtained. It will not be possible to maintain and supply stably. As shown in FIG. 5, the element active region 3 having a width smaller than the width of the dummy gate electrode 7 is formed on the left and right sides of the resistance element 4, and the dummy gate electrode 7 is formed so as to completely cover the element active region 3. Thus, the shape stability of the dummy gate electrode 7 can be obtained. Then, by bringing the dummy gate electrode 7 whose shape is stabilized and the resistor element 4 close to each other, the resistor element 4 with high dimensional accuracy can be stably formed.

  As described above, since the element active region 3 plays a role of dividing the element isolation oxide film 2 into strips, the width of the element active region 3 is not particularly limited. Therefore, by reducing the width of the element active region 3, the width of the element isolation oxide film 2 can be increased and the arrangement efficiency of the resistance element 4 can be increased.

  Next, still another example of the semiconductor device of the second embodiment will be described with reference to FIG. In the semiconductor device of FIG. 6, the element active region 3 is formed so as to surround the element isolation oxide film 2 in which the resistance element 4 is formed. As described above, by enclosing the periphery of the resistance element 4 with the element active region 3, the dimension of the element isolation oxide film 2 can be defined by the element active region 3 not only in the width direction but also in the longitudinal direction of the resistance element 4. .

  As a result, the element isolation oxide film 2 on which the resistance element 4 is formed becomes an island-like independent pattern, and can be surely flattened during polishing by the CMP method, and a dent is formed at the center. Can be deterred.

  Next, still another example of the semiconductor device of the second embodiment will be described based on FIG. In this example, the arrangement of the element active region 3 is the same as that described with reference to FIG. 2 except that the dummy gate electrode 7 is formed so as to surround each resistance element 4.

  Thus, by surrounding the periphery of the resistance element 4 with the dummy gate electrode 7, the shape of the resistance element 4 can be formed with high accuracy. In particular, it is possible to accurately form the shape of the end portion of the resistance element 4 in the longitudinal direction. Further, as described above, by defining the distance between the resistance element 4 and the dummy gate electrode 7 with the minimum gate distance S, the shape of the resistance element 4 can be formed with very high accuracy.

  FIG. 8 shows an example in which the element active region 3 is formed so as to surround the resistance element 4, and the dummy gate electrode 7 is formed on the element active region 3 so as to also surround the resistance element 4. In this example, by making the element isolation oxide film 2 into an island shape, the flatness of the element isolation oxide film 2 at the time of polishing by the CMP method can be improved, and the dummy gate electrode so as to surround the resistance element 4 By forming 7, it becomes possible to ensure shape stability when the resistance element 4 is patterned.

  Next, still another example of the semiconductor device of the second embodiment will be described with reference to FIG. The semiconductor device of FIG. 9 shows an example in which the resistance element 8 and the dummy gate electrode 9 are formed using a stacked structure (polycide gate structure) of a polycrystalline silicon film and a silicide film. This is particularly suitable when the gate electrode in the MOS transistor formation region is formed with a polycide gate structure. Since the resistance element 8 needs to secure a predetermined resistance value, the silicide layer is removed except for the end portion, and the lower polycrystalline silicon film 8 a becomes the upper surface of the resistance element 8 in this region. On the other hand, since it is not necessary to consider the resistance value of the dummy gate electrode 9, a silicide layer is formed on the entire surface.

  Thus, for example, when the gate electrode is formed with a polycide structure in the MOS transistor formation region, the polycide structure resistance element 8 and the dummy gate electrode 9 can be formed. By selectively removing the silicide layer of the resistance element 8, the resistance value of the resistance element 8 can be set to a desired value.

  The method for manufacturing each semiconductor device according to the second embodiment as described above is obtained by adding the step of forming the dummy gate electrode 7 to the method for manufacturing the semiconductor device according to the first embodiment. That is, simultaneously with the patterning of the resistance element 4, the dummy gate electrode 7 having a predetermined shape as shown in FIGS. 2 to 5 and FIGS. The semiconductor device can be manufactured. As shown in FIG. 6, in order to surround the periphery of the element isolation oxide film 2 with the element active region 3, the element isolation oxide film 2 is formed during the trench formation by the STI method described in the first embodiment. A rectangular groove corresponding to the region is formed to bury an insulating film such as a silicon oxide film.

  As described above, in the second embodiment, the dummy gate electrode 7 arranged almost in parallel with the resistance element 4 is provided on the element active region 3 so that the distance between the dummy gate electrode 7 and the resistance element 4 is close. Thus, the stabilization of the shape of the resistance element 4 can be achieved. In particular, by setting the distance between the dummy gate electrode 7 and the resistance element 4 to the minimum value of the pattern distance, the resistance element 4 and the dummy gate electrode 7 can be formed under optimum process conditions. Thereby, the shape of the resistance element 4 can be formed with higher dimensional accuracy, and the resistance value of the resistance element 4 can be set to a desired value.

Embodiment 3 FIG.
FIG. 10 is a schematic view showing a semiconductor device according to the third embodiment of the present invention, and is a plan view showing a planar configuration of the semiconductor device. In this semiconductor device, an impurity is introduced into the element active region 3 of the semiconductor device of FIG. 1 to form a diffusion layer 10 that functions as a resistance element. Both ends of each diffusion layer 10 are connected to an upper wiring layer 11 via a contact layer 12.

  In the semiconductor device of the third embodiment, as in the first embodiment, the element isolation oxide film 2 in which each resistance element 4 is formed is divided by the element active region 3 so that the element isolation oxidation is performed during polishing by the CMP method. The flatness of the surface of the film 2 can be improved, and the diffusion layer 10 is formed in the element active region 3 so that the resistance element (diffusion layer resistance element) by the diffusion layer 10 is in the same region as the resistance element 4. Can be formed adjacent to.

  Therefore, according to the third embodiment, the dimensional accuracy of the resistance element 4 can be improved, and the diffusion layer resistance element can be formed using the element active region 3 formed between the resistance elements 4. A resistance element can be efficiently formed in the space.

  In the method of manufacturing each semiconductor device according to the third embodiment, an impurity introduction step is added to the element active region 3 of the semiconductor device according to the first embodiment. That is, after the element active region 3 is formed, a predetermined impurity is introduced into the element active region 3 by ion implantation, whereby the element active region 3 can be a diffusion layer 10 having a desired resistance value. Thereafter, the semiconductor device of the third embodiment is completed through the steps of forming the interlayer insulating film, forming the contact layer 12 connected to the diffusion layer 10 and forming the wiring layer 11.

  FIG. 11 is a plan view showing another example of the semiconductor device of the third embodiment. The semiconductor device of FIG. 11 is provided with element active regions 3 on the left and right sides of the resistance element 4 in the width direction, and also provided with element active regions 3 extending so as to be close to the end portions of the resistance elements 4 in the longitudinal direction. A diffusion layer 10 that functions as a resistance element is formed by introducing a predetermined impurity into the element active region 3. Both ends of each diffusion layer 10 are connected to an upper wiring layer 11 via a contact layer 12.

  Thus, by enclosing the four directions around the resistance element 4 with the diffusion layer 10 (element active region 3), the spread of the element isolation oxide film 2 can be restricted, and the element isolation oxide film 2 is polished by CMP. It is possible to improve the flatness at the time. Further, by using the element isolation oxide film 2 as the diffusion layer 10 functioning as a resistance element, it becomes possible to configure the resistance element by the resistance element 4 and the diffusion layer 10 and greatly increase the efficiency of arrangement of the resistance element in the same range Can be increased.

Embodiment 4
12 is a plan view showing a semiconductor device according to the fourth embodiment of the present invention. In the semiconductor device of FIG. 12, dummy gate electrodes 7 are formed in the element active regions 3 adjacent to both sides of the resistor element 4 as in the semiconductor device of FIG. In this way, the wiring layer 13 is formed.

  In general, when there is a wiring layer passing directly above the resistance element, the activation rate of the polycrystalline silicon film changes due to the influence of the wiring layer. For this reason, there is a difference in resistance value between a resistance element having a wiring layer immediately above and a resistance element having no wiring layer directly above.

  In the fourth embodiment, the wiring layer 13 covers the resistance elements 4 directly at a uniform rate. Specifically, the ratio of the area of the resistive element 4 and the area of the wiring layer 13 overlapping the area of the resistive element 4 is set to the same ratio in each resistive element 4. Thereby, even when the activation rate of the polycrystalline silicon film changes due to the influence of the wiring layer 13, the resistance difference generated in each resistance element 4 can be made substantially the same, and the resistance value of each resistance element 4 Can be made uniform. In order to make the resistance value of the resistance element 4 uniform, it is desirable that the arrangement of the wiring layer 13 with respect to the resistance element 4 is the same as described above, but the wiring layer 13 is completely formed on the resistance element 4. This makes it possible to achieve uniform resistance values.

  As described above, in the fourth embodiment, the ratio of the area of the resistive element 4 and the area of the area where the wiring layer 13 formed on the resistive element 4 and the resistive element 4 overlap (overlapping) is represented by each resistive element. By making 4 constant, the difference in resistance value caused by the wiring 13 can be made the same, and the resistance element 4 having almost the same resistance value can be formed.

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 2 Element isolation oxide film, 3 Element active region, 4,8 Resistance element, 5,11 Wiring layer, 6,12 Contact layer, 7,9 Dummy gate electrode, 10 Diffusion layer

Claims (8)

A semiconductor substrate;
An active region disposed on a main surface of the semiconductor substrate;
An isolation region made of an oxide film buried in a groove disposed on the main surface of the semiconductor substrate,
The separation region includes a first separation region and a second separation region, and the first separation region and the second separation region are short sides of the separation regions perpendicular to the longitudinal direction of the separation regions. Are placed next to each other in parallel,
The active region includes a first active region disposed between the first and second isolation regions, and the first active region facing the first active region along the short direction of the respective isolation regions. A second active region disposed adjacent to one another with one isolation region interposed therebetween, and the second isolation region sandwiching the second isolation region along the short direction of each of the isolation regions facing the first active region Including a third active region disposed adjacent to each other;
Each of the separation regions includes a resistance element disposed one by one along the longitudinal direction of the separation region,
2. The semiconductor device according to claim 1, wherein each of the isolation regions below the resistance element is defined to have a predetermined width by the respective active regions.   The semiconductor device according to claim 1, wherein the resistance elements are uniformly arranged with a certain length, width, and film thickness.   The semiconductor device according to claim 1, wherein the resistance element is formed inside each of the isolation regions.   2. The semiconductor device according to claim 1, wherein the respective isolation regions under the resistance element are defined to be 20 μm or less by the respective active regions. In a predetermined region on the semiconductor substrate, the insides of the plurality of rectangular regions arranged are removed by etching, and the first and first adjacently arranged in parallel to each other in the lateral direction of the groove perpendicular to the longitudinal direction of the groove A first step of arranging two grooves;
A second step of depositing an insulating film on the semiconductor substrate and embedding the first and second grooves;
The surface of the insulating film is polished, the insulating film in a region other than the groove is removed, and the surface of the insulating film on the first and second grooves is flattened to be in the first and second grooves. First and second insulating films are formed, a first active region disposed between the first and second insulating films, and the first active region and the insulating film along the short direction of the insulating film A second active region is disposed adjacent to the first insulating film, and is adjacent to the first active region along the short direction of the insulating film with the second insulating film interposed therebetween. A third step of disposing a third active region, and disposing first to third active regions defining the first and second insulating films to a predetermined width;
A fourth step of disposing a conductive film made of a material having a predetermined resistance value on the semiconductor substrate;
A method of manufacturing a semiconductor device, comprising: a fifth step of patterning the conductive film on the insulating film to dispose a resistance element.   6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the fifth step, the resistance elements are uniformly arranged with a certain length, width and film thickness.   6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the fifth step, the resistance element is formed inside the insulating film.   6. The method of manufacturing a semiconductor device according to claim 5, wherein, in the third step, the insulating film below the resistance element on the insulating film is defined to be 20 [mu] m or less by the active region.

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