JPH0917993A - Ohmic electrode, manufacturing method thereof, semiconductor device and photoelectric integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the contact resistance and elevate the reliability by comprising a Pt layer of less than specified thickness, contacted onto a compd. semiconductor contg. a p type InGaAs main component. SOLUTION: After washing the surface of a semi-insulative InP substrate 1 with acid, a compd. semiconductor 2 contg. a p type InGaAs main component is epitaxially grown thereon. On the semiconductor 2 the vapor of Pt is deposited to form a Pt layer 3 of 400 Angstrom or less thick. On this layer 3 the vapors of Ti, Pt and Au are deposited successively and annealed in an atmosphere of about 400 deg. C for one minute to form a Ti layer 41, Pt layer 42 and Au layer 43, thereby completing an Ohmic electrode 5. Thereby, the contact resistance can be made low to provide a high reliability product.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ohmic electrode on a compound semiconductor containing hole conduction type (hereinafter also referred to as p type) or electron conduction type (hereinafter also referred to as n type) InGaAs as a main component. The present invention relates to a manufacturing method thereof, a semiconductor device including the same, and an optoelectronic integrated circuit.

[0002]

2. Description of the Related Art Conventionally, ohmic electrodes on compound semiconductors have been disclosed in JP-A-3-240242, JP-A-5-136175, IEEE. ELECTRON
DEVICE LETTER vol. EDL-5
No6 214 (1984), etc.
A uGe / Ni alloy metal is used.

However, since the elemental elements of this alloy metal are diffused into the semiconductor crystal layer, the reliability of the device cannot be said to be sufficiently high, and improvement is desired.

On the other hand, regarding non-alloy type ohmic electrodes on compound semiconductors, p-type GaAs and AlGaAs are used.
The Pt / Ti / Pt / Au electrode laminated on top is described in Japanese Patent Application No. 2-88040.

Further, an InGaAs pin photodiode, which is a light receiving element for optical communication in a long wavelength (1 to 1.6 μm) band, and an InP / InGaAs HBT capable of high-speed operation.
In (heterojunction bipolar transistor) etc., In
Since it is necessary to form an electrode on GaAs, InGa
Various proposals have been made for the ohmic electrode on As.

Among these, the following are known as non-alloy type p ohmic electrodes on p-type InGaAs.

Technical Report of ED93-162 (1994-
01) Pt / Ti / Pt / Au electrode J. Appl. Phys. 68 (3), 1 August 1990 Ti / P
t / Au electrode Sumitomo Electric Technical Review No.35 January
AuZn electrode described in 1993 However, in the Ti / Pt / Au electrode (above) on p-type InGaAs, etc., there is a problem that the reliability is deteriorated due to the diffusion of the electrode material to the InGaAs crystal side. Also,
The contact resistance is not sufficiently low as compared with the alloy type ohmic electrode.

Further, Japanese Patent Application Laid-Open No. 63-228762 also reports an example in which a Ti / Pt / Au ohmic electrode is used as a non-alloy type electrode on a compound semiconductor containing InGaAs as a main component. , This is also not reliable enough.

On the other hand, p-type InGaAs and Ti / Pt / A
A Pt layer interposed between the u electrode, that is, p
Although the Pt / Ti / Pt / Au electrode on InGaAs is described in the above-mentioned document, the contact resistance or reliability has not been examined, and the optimum electrode structure is not clear.

[0010]

The present invention has been made in view of the above, and is a non-alloy which is formed on a compound semiconductor containing p-type or n-type InGaAs as a main component and has a low contact resistance and high reliability. An object is to provide a system ohmic electrode and a method for manufacturing the same. Moreover, it aims at providing a highly reliable semiconductor device and an optoelectronic integrated circuit.

[0011]

In order to solve the above-mentioned problems, the first ohmic electrode according to the present invention has a thickness in contact with a compound semiconductor whose main component is p-type (hole conduction type) InGaAs. It is characterized by having a Pt layer of about 400 angstroms or less.

According to the knowledge of the present inventors, p-type InG
An ohmic contact in which a Pt layer having a thickness of about 400 Å or less is formed on a compound semiconductor containing aAs as a main component exhibits a sufficiently low contact resistance, and also when a metal layer is formed on the Pt layer, Little diffusion of metal element into the compound semiconductor layer, and little change in characteristics under high temperature environment. In particular, when the thickness of the Pt layer is 200 angstroms or less, the characteristic change under a high temperature environment becomes extremely small.

The first non-alloy type ohmic electrode according to the present invention in which a Pt layer having a thickness of 400 angstroms or less is brought into contact with a compound semiconductor whose main component is p-type InGaAs has the above ohmic contact. Due to the excellent property of the ohmic contact, the diffusion of the electrode material into the compound semiconductor layer is small, the contact resistance is sufficiently low, and the reliability is high. In particular, a compound semiconductor in which a Pt layer having a thickness of about 200 Å or less is brought into contact has extremely high reliability.

The second ohmic electrode according to the present invention is characterized by including a Pt layer in contact with a compound semiconductor whose main component is n-type (electron conduction type) InGaAs.

According to the knowledge of the present inventors, n-type InG
The second non-alloy type ohmic electrode according to the present invention in which the Pt layer is in contact with the compound semiconductor containing aAs as the main component has a small diffusion of the electrode material into the compound semiconductor layer and is stored in a high temperature environment for a long time. In addition, the contact resistance is kept low and the reliability is high.

The first and second ohmic electrodes according to the present application are a Ti layer and a P layer, which are sequentially stacked on the Pt layer.
It may further include a t layer and an Au layer.

Next, the semiconductor optical device according to claim 4 of the present application and the semiconductor electronic device according to claim 5 of the present application are characterized by including the first or second ohmic electrode according to the present application. Here, the semiconductor optical device refers to a device in which one or more semiconductor elements (semiconductor laser, photodiode, etc.) having a light emitting or light receiving function are formed on a single substrate. What is a semiconductor electronic device?
One in which one or more semiconductor elements (diodes, transistors, etc.) that handle electrons are formed on a single substrate.

Due to the excellent properties of the ohmic electrode according to the present invention, the semiconductor optical device and the semiconductor electronic device described above have little change in characteristics even when stored for a long time in a high temperature environment and have high reliability.

Next, an optoelectronic integrated circuit (OEIC) according to claim 6 of the present application integrates the semiconductor optical device and the semiconductor electronic device of the present invention. Here, the optoelectronic integrated circuit refers to a circuit that has a predetermined function by integrating and forming a semiconductor optical device or a semiconductor electronic device on a substrate.

The optoelectronic integrated circuit according to claim 6 of the present application also comprises
Due to the excellent properties of the ohmic electrode of the present invention, there is little change in properties even when stored for a long time in a high temperature environment, and high reliability is achieved.

Next, a semiconductor device according to claim 7 of the present application is provided by (a) a compound semiconductor containing p-type or n-type InGaAs as a main component and (b) being in contact with this compound semiconductor. An ohmic electrode having a Pt layer, and P in the vicinity of the interface between the compound semiconductor and the Pt layer.
It is characterized by containing an alloy of t and In.

Since the alloy of Pt and In is thermally stable, the existence of such an alloy near the boundary surface between the compound semiconductor and the Pt layer means that when the semiconductor device is stored in a high temperature environment. This is one factor that prevents the diffusion of the electrode material into the compound semiconductor. Therefore, the semiconductor device according to claim 7 of the present application has high reliability with little fluctuation in contact resistance even when placed in a high temperature environment.

The above alloys include PtIn, PtIn ₂ , P
It may be one or more alloys selected from the group consisting of t ₃ In ₂ , Pt ₄ In ₃ and Pt ₁₃ In ₉ .

Next, an optoelectronic integrated circuit according to claim 9 of the present application is characterized by integrating the semiconductor device according to claim 7.

This optoelectronic integrated circuit has high reliability based on the excellent properties of the semiconductor device according to claim 7 of the present application.

Next, a first ohmic electrode forming method according to the present application comprises a first step of depositing a Pt layer having a thickness of about 400 Å or less on a compound semiconductor containing p-type InGaAs as a main component, A second step of forming a predetermined metal layer on the Pt layer.

In the first ohmic electrode forming method according to the present application, a Pt layer is vapor-deposited on a compound semiconductor containing p-type InGaAs as a main component, so that Pt and In are formed near the boundary surface between the compound semiconductor and the Pt layer. Produces an alloy of. Therefore,
By forming electrodes on the compound semiconductor containing p-type InGaAs as a main component by this method, the semiconductor device according to claim 7 of the present application can be easily manufactured.

In the second ohmic electrode forming method according to the present application, a first step of depositing a Pt layer on a compound semiconductor containing n-type InGaAs as a main component and a predetermined step on the Pt layer are performed. A second step of forming a metal layer.

In the second ohmic electrode forming method according to the present application, a Pt layer is vapor-deposited on a compound semiconductor containing n-type InGaAs as a main component, so that Pt and In near the boundary surface between the compound semiconductor and the Pt layer. Produces an alloy of. Therefore,
By forming electrodes on the compound semiconductor containing n-type InGaAs as a main component by this method, the semiconductor device according to claim 7 of the present application can be easily manufactured.

In the first or second ohmic electrode forming method according to the present application, the second step is the step of forming a Ti layer, a Pt layer and an A layer on the Pt layer deposited on the compound semiconductor.
It may be a step of sequentially forming the u layer.

[0031]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements will be denoted by the same reference symbols, without redundant description. Also, the dimensional ratios in the drawings do not always match those described.

(Embodiment 1) Embodiment 1 relates to a first ohmic electrode according to the present application. FIG. 1 is a schematic cross-sectional view showing the structure of the ohmic electrode 5 of this embodiment. The ohmic electrode 5 of the present embodiment is the Pt layer 3 stacked on the hole conduction type (p type) InGaAs layer 2.
And a Ti layer 41 and a Pt layer 4 laminated on the Pt layer 3.
2 and a Ti / Pt / Au electrode layer 4 consisting of three layers of Au layer 43. The thickness of the Pt layer 3 is 40
0 angstrom or less. In addition, p-type InGaA
The s layer 2 is formed on the semi-insulating InP substrate 1.

The ohmic electrode 5 comprises a Pt layer 3, a Ti layer 41, a Pt layer 42 and an Au layer 4 on the p-type InGaAs layer 2.
It can be formed by depositing 3 sequentially. Specifically, first, the surface of the semi-insulating InP substrate 1 is washed with acid, and then the p-type InGaAs layer 2 is epitaxially grown. Next, Pt is vapor-deposited on the p-type InGaAs layer 2, and then Ti, Pt, and Au are vapor-deposited on Pt sequentially. After that, by annealing for 1 minute in an atmosphere of about 400 ° C., the Pt layer 3, the Ti layer 41, the Pt layer 42, and the Au layer 43 are formed. Thereby, the ohmic electrode 5 is completed.

FIG. 2 shows an InGaAs pin photodiode including the ohmic electrode 5 of the present embodiment (hereinafter referred to as
Abbreviated as PD. ) Is a schematic cross-sectional view showing 100. This p
The inPD 100 includes an n ⁺ -InP layer 6, an i-InGaAs layer 7, and a p ⁺ -InGaAs layer 2 that are sequentially stacked on a semi-insulating InP substrate 1, and further includes p ⁺ -InGa.
The p-ohmic electrode 5 of the present embodiment which is in contact with the As layer 2 and the n-electrode 8 which is in contact with the n ⁺ -InP layer 6 are provided. The surface of the pin PD 100 is covered with the SiN passivation film 9. This pinPD
100 can be manufactured by a normal manufacturing process. Incidentally, on the InP substrate 1, n ⁺ -InGaAs layer may be formed instead of the n ⁺ -InP layer 6.

As described above, the ohmic electrode 5 of this embodiment can be easily applied to a semiconductor optical device such as a pin PD. In addition to pin PD, avalanche photodiode, MSM photodiode,
It can be applied to semiconductor optical devices such as light emitting diodes (LEDs) and semiconductor lasers (LDs).

FIG. 3 is a schematic sectional view showing an InGaAs heterojunction bipolar transistor (hereinafter abbreviated as HBT) 200 including the ohmic electrode 5 of this embodiment. This HBT 200 is of a tunnel barrier type, and has n ⁺ − layers sequentially stacked on the semi-insulating InP substrate 1.
InGaAs subcollector 10 layer, n-InGaAs collector layer 11, p-InGaAs base layer 12, InP
The tunnel barrier layer 13 and the n ⁺ -InGaAs emitter layer 14 are provided, and further the ohmic electrode 5 (base electrode) of the present embodiment which is in contact with the p-InGaAs base layer 12 and the Au / Ge which is in contact with the emitter layer 14 are provided. / Ni
Au / Ge / Ni electrode 16 (collector electrode) in contact with electrode 15 (emitter electrode) and subcollector layer 10
It has. The surface of the HBT 200 is covered with the SiN passivation film 9. This HBT
200 can also be manufactured by a normal manufacturing process.

As described above, the ohmic electrode 5 of this embodiment can be easily applied to a semiconductor electronic device such as an HBT. In addition to the HBT, it can be applied to semiconductor optical devices such as FETs including HEMT.

Regarding the ohmic electrode 5 (FIG. 1) of the present embodiment, the present inventors have sought to find a suitable thickness of the Pt layer 3 in contact with the p-type InGaAs layer 2 in order to obtain the contact resistance and reliability of the ohmic electrode. The relationship between Pt and the thickness of Pt layer 3 was investigated.

FIG. 4 is a graph showing changes in the contact resistivity of the ohmic electrode 5 of this embodiment when the thickness of the Pt layer 3 is varied between 0 and 400 angstroms. The sudden change in the vicinity of the thickness of 0 indicates that p-type InGaA
It is shown that the Pt layer 3 is interposed between the s layer 2 and the Ti / Pt / Au electrode layer 4 to reduce the contact specific resistance to about 1/2. The contact resistivity also increases slightly with increasing thickness, but at least the thickness of 4
If it is less than 00 angstrom, the contact resistivity is sufficiently reduced.

FIG. 5A is a graph showing the result of measuring the reliability of the ohmic electrode 5 of this embodiment using the HBT (FIG. 3) having the ohmic electrode 5 of this embodiment as a base electrode. . This is a plot of changes in the on-voltage (V _ON ) of the HBT when the HBT was stored for a predetermined storage time in a high temperature environment of 250 ° C. The Pt layer 3 has a thickness of 200 Å.

The horizontal axis of FIG. 5A is a logarithmic axis,
init. Indicates that the storage time is 0, that is, the storage has not been performed in a high temperature environment. The vertical axis represents the variation of the on-voltage before and after the storage, and specifically shows (on-voltage after storage-on-voltage before storage) / (on-voltage before storage) [%]. ON voltage is 1 × 10 ⁴ A / during storage time
The collector current (I _C ) having a current density of cm ² is HB
Continue to flow to T, and then take out the HBT from the high temperature environment and measure.

On the other hand, FIG. 5B shows a conventional Ti / Pt / Au electrode in which the Pt layer 3 is not interposed between the p-type InGaAs layer 2 and the Ti / Pt / Au electrode layer 4 as a base electrode. It is a graph showing the result of having measured reliability similarly to the above using HBT provided.

As is clear from comparing these figures,
The HBT including the ohmic electrode 5 of the present embodiment suppresses the fluctuation of the on-voltage in a high temperature environment and has improved reliability as compared with the conventional HBT including the Ti / Pt / Au electrode. This is based on the high reliability of the ohmic electrode 5.

Next, FIGS. 6 and 7 are graphs showing the variation of the contact resistance (Rc) with respect to the ohmic electrode 5 (FIG. 1) of this embodiment according to the storage time under a high temperature (250 ° C.) environment. is there. As in FIG. 5, the horizontal axis of the graph is a logarithmic axis, and init. Indicates that the storage time is 0, that is, the storage is not performed. The vertical axis represents the change in contact resistance before and after storage, and specifically shows (contact resistance after storage-contact resistance before storage) / (contact resistance before storage) [%]. The contact resistance is measured by a known transmission line model (TLM) method. Regarding the TLM method,
It is described on pages 200 to 202 of "Ultrafast compound semiconductor device" (edited by Masamichi Omori, Baifukan).

The thickness of the Pt layer 3 is 50 angstroms in FIG. 6 (a), 100 angstroms in FIG. 6 (b), 200 angstroms in FIG. 7 (c), and FIG.
In (d), it is 400 angstrom.

On the other hand, FIG. 8E shows a conventional Ti / Pt in which the Pt layer has a thickness of 0, that is, the Pt layer 3 is not interposed between the p-type InGaAs layer 2 and the Ti / Pt / Au electrode layer 4. /
FIG. 8 is a graph showing changes in contact resistance with respect to the Au electrode, as in FIGS. 6 and 7. FIG.

As is clear from comparison of these graphs, the ohmic electrode 5 (Pt layer 3 having a thickness of 400 angstroms or less) according to the present embodiment has a conventional Ti / P ratio.
Compared to the t / Au electrode, the contact resistance changes less when stored in a high temperature environment and has higher reliability. In particular, Pt
When the thickness of the layer 3 is 200 angstroms or less, the fluctuation of the contact resistance is extremely low, and the ohmic electrode has a very high reliability.

From the above consideration, a compound semiconductor containing p-type InGaAs as a main component (in this embodiment, p-type InG) is used.
Pt with a thickness of 400 Å or less is formed on the aAs layer 2).
In the ohmic contact in which the layers are stacked, a metal electrode layer (Ti / Pt / A in this embodiment) formed on the Pt layer is formed.
The diffusion of the electrode material (mainly Au in the present embodiment) from the u electrode layer 4) to the compound semiconductor is small, so that a sufficiently low contact resistance is exhibited, and the characteristics of the characteristics are also maintained when stored for a long time in a high temperature environment. It is estimated that there is little change. As a result, the ohmic electrode 5 of the present embodiment exhibits a sufficiently low contact resistance and has high reliability. In addition, the semiconductor optical device and the semiconductor electronic device including the ohmic electrode 5 also include the ohmic electrode 5.
Due to its excellent properties, it has high reliability.

An optoelectronic integrated circuit (hereinafter abbreviated as OEIC) can be manufactured by integrating these semiconductor optical devices and semiconductor electronic devices using a normal integration technique. FIG. 9 shows the pin PD100 of FIG. 2 and FIG.
3 is a schematic cross-sectional view showing an OEIC 300 in which the HBT 200 of FIG. In the OEIC 300, the wiring 20 connects the n ⁺ -InP layer 6 of the pin PD 100 to the collector electrode 16. The wiring 20 is also connected to the ohmic electrode 5 of the present embodiment. Note that pi
Under the nPD100, due to the manufacturing process, HBT2
Although the semiconductor layers 10 to 14 which are stacked when the 00 is formed remain, they do not affect the operation of the OEIC.

Since this OEIC 300 also includes the ohmic electrode 5 of this embodiment, it has high reliability due to the excellent properties of the ohmic electrode 5.

The first ohmic electrode according to the present application is not limited to the above embodiment, but various modifications can be made. For example, the ohmic electrode 5 of this embodiment is Pt.
Although the Ti / Pt / Au layer 4 is laminated on the layer 3, another metal layer may be laminated instead of the Ti / Pt / Au layer 4. The excellent properties of the first ohmic electrode according to the present application are due to the structure in which the Pt layer having a thickness of 400 angstroms or less is laminated on the compound semiconductor whose main component is InGaAs. / Metal layers other than Au layer (Ti / Au, Mo
/ Au, etc.) has a sufficiently low contact resistance and high reliability.

(Embodiment 2) Embodiment 2 relates to a second ohmic electrode according to the present application. FIG.
It is a schematic cross section which shows the structure of the ohmic electrode 25 of this embodiment. The ohmic electrode 25 of the present embodiment is a Pt layered on the electron conduction type (n type) InGaAs layer 22.
Layer 23 and Ti layer 24 laminated on this Pt layer 23
1, a Pt layer 242, and an Au layer 243.
It is composed of an i / Pt / Au electrode layer 24. The n-type InGaAs layer 22 is formed on the semi-insulating InP substrate 21.

This ohmic electrode 25 is made of InGaAs.
It can be formed by sequentially depositing a Pt layer 23, a Ti layer 241, a Pt layer 242 and an Au layer 243 on the layer 22. Specifically, first, the surface of the semi-insulating InP substrate 21 is washed with acid, and then the n-type InGaAs layer 22 is epitaxially grown. Then, the InGaAs layer 22
Pt is vapor-deposited on Pt, and then Ti, Pt and Au are added to P
It vapor-deposits on t sequentially. After that, if the Pt layer 23 and the Ti layer 2 are annealed in an atmosphere of about 400 ° C. for 1 minute,
41, the Pt layer 242 and the Au layer 243 are formed. As a result, the ohmic electrode 25 is completed.

FIG. 11 shows the ohmic electrode 2 of this embodiment.
5 is a schematic cross-sectional view showing an InGaAs pin photodiode (hereinafter, abbreviated as PD) 101 including No. 5. The pin PD 101 includes an n ⁺ -InGaAs layer 26 and an i-InG layer sequentially stacked on a semi-insulating InP substrate 21.
a p-electrode 50 provided with the aAs layer 27 and the p-InGaAs layer 2, and further in contact with the p-InGaAs layer 2;
The n electrode 28 formed of the ohmic electrode 25 of the present embodiment is in contact with the n ⁺ -InGaAs layer 26. The surface of the pin PD 101 is covered with the SiN passivation film 29. This pinPD
101 can be manufactured by a normal manufacturing process.

As described above, the ohmic electrode 25 of this embodiment can be easily applied to a semiconductor optical device such as a pin PD. In addition to pin PD, avalanche photodiode, MSM photodiode, light emitting diode (LED), semiconductor laser (LD)
Can be applied to semiconductor optical devices such as.

Next, FIG. 12 is a schematic sectional view showing an InGaAs heterojunction bipolar transistor (hereinafter abbreviated as HBT) 201 including the ohmic electrode 25 of this embodiment. The HBT 201 includes an n ⁺ -InGaAs subcollector layer 210, an n-InGaAs collector layer 211, which are sequentially stacked on a semi-insulating InP substrate 21.
p-InGaAs base layer 212, InP emitter layer 2
13 and n ⁺ -InGaAs emitter contact layer 21
4 and further includes a base electrode 225 (Ti / Pt / Au) in contact with the p-InGaAs base 212, an emitter electrode 215 including the ohmic electrode 25 of the present embodiment in contact with the emitter contact layer 214, and a sub electrode. The collector electrode 216 is formed of the ohmic electrode 25 of this embodiment, which is in contact with the collector layer 210. The surface of the HBT 201 is covered with the SiN passivation film 9. Although the Ti / Pt / Au electrode is used as the base electrode 225 in the present embodiment, the base electrode 225 is not limited to this, and the Pt / Ti / Pt / Au electrode according to the present embodiment is of course AuZn / A.
A u electrode or the like can also be used. This HBT201 is
It can be manufactured by a normal manufacturing process.

As described above, the ohmic electrode 25 of this embodiment can be easily applied to a semiconductor electronic device such as an HBT. In addition to HBT, HEMT
It can be easily applied to semiconductor optical devices such as FETs including.

FIG. 13 shows the ohmic electrode 2 of this embodiment.
11 is a graph showing the results of measuring the reliability of the ohmic electrode 25 of the present embodiment shown in FIG. 10 using the HBT 201 (FIG. 12) including 5 as the emitter electrode 215 and the collector electrode 216. This is a graph showing the variation of the contact resistance (R _c ) of the ohmic electrode 25 according to the storage time under a high temperature (250 ° C.) environment. The horizontal axis of the graph is a logarithmic axis, and init. Indicates that the storage time is 0, that is, the storage has not been performed in a high temperature environment. The vertical axis represents the change in the on-voltage before and after storage, and specifically, (contact resistance after storage-contact resistance before storage) / (contact resistance before storage) [%]. The contact resistance is the same as that of the first embodiment.
It is measured by the transmission line model (TLM) method described in (1).

As shown in FIG. 13, the HBT 201 including the ohmic electrode 25 of this embodiment has a sufficiently small fluctuation in contact resistance even when stored for a long time in a high temperature environment and has high reliability. ing.

The inventors of the present invention have made the Pt layer 2 in contact with the compound semiconductor layer 22 in the ohmic electrode 25 of this embodiment.
In order to show the effect of No. 3, as a comparative example, Ti / Pt / Au
Using an HBT having an ohmic electrode 51 made of an electrode layer as an emitter electrode and a collector electrode (in which the ohmic electrode 25 is replaced with the ohmic electrode 51 in the HBT 201), the change in contact resistance with time was measured under the same conditions as in FIG. . FIG. 14 is a graph showing the measurement result.

Further, the present inventors have made a conventional alloy type A
An HBT (H) having an ohmic electrode 52 composed of a uGe / Ni-based electrode layer as an emitter electrode and a collector electrode
The contact resistance was measured under the same conditions as in FIGS. 13 and 14 using the BT201 in which the ohmic electrode 25 was replaced with the ohmic electrode 52). FIG. 15 is a graph showing the measurement result.

The structure of the ohmic electrode 51 used to obtain FIG. 14 is shown in FIG. This ohmic electrode 5
1 is the Pt layer 23 from the ohmic electrode 25 of the present embodiment.
N-type InGaAs layer 22 having a structure excluding
A Ti layer 241, a Pt layer 242, and an A layer that are sequentially stacked on top
It is composed of a Ti / Pt / Au electrode layer composed of three u layers 243. The n-type InGaAs layer 22 is formed on the semi-insulating InP substrate 21. The ohmic electrode 51 includes a Ti layer 241 and a P layer on the InGaAs layer 22.
It can be formed by sequentially depositing the t layer 242 and the Au layer 243.

FIG. 17 shows the structure of the ohmic electrode 52 used to obtain FIG. This ohmic electrode 5
2 is A sequentially stacked on the n-type InGaAs layer 22.
AuGe / Ni composed of uGe layer 244 and Ni layer 245
The system is composed of an alloy type metal layer. n-type In
The GaAs layer 22 is formed on the semi-insulating InP substrate 21. The ohmic electrode 52 can be formed by sequentially depositing the AuGe layer 244 and the Ni layer 245 on the InGaAs layer 22.

As is clear from comparison between FIG. 13 and FIG. 15, the ohmic electrode 25 of the present embodiment is 40% thicker than the case of the conventional alloy type AuGe / Ni based electrode layer 52.
Highly reliable with little change in contact resistance over 0 hr.

Further, by comparing FIG. 13 and FIG. 14, it can be seen that this effect is mainly due to the use of the Pt layer as the contact layer.

From these results, the pin PD101, which is a semiconductor optical device including the ohmic electrode 25, is also shown.
The HBT 201, which is a semiconductor electronic device, also has high reliability based on the excellent properties of the ohmic electrode 25.

An optoelectronic integrated circuit (hereinafter abbreviated as OEIC) can be manufactured by integrating these semiconductor optical devices and semiconductor electronic devices using a normal integration technique. FIG. 18 is a schematic sectional view showing an OEIC 301 in which the pin PD 101 of FIG. 11 and the HBT 201 of FIG. 12 are integrated. In this OEIC301, the wiring 20
The pin PD 101 and the HBT 201 are connected by. The n electrode 28, the emitter electrode 215, and the collector electrode 2 of these semiconductor optical devices and semiconductor electronic devices
16 is the ohmic electrode 25 according to the present embodiment.
Therefore, the OEIC 301 also has high reliability based on the excellent properties of the ohmic electrode 25 of the present embodiment.

Note that the semiconductor layers 210 to 214 laminated when the HBT 201 was formed remain under the pin PD 101 due to the manufacturing process.
It does not affect the operation of 301.

The second ohmic electrode according to the present application is not limited to the above embodiment, but various modifications can be made. For example, the ohmic electrode 25 of this embodiment is P
The Ti / Pt / Au layer 24 is laminated on the t layer 23, but other metal layers (Ti / Au, Mo / Au, etc.) are laminated in place of the Ti / Pt / Au layer 24. It may be one. Since the excellent properties of the second ohmic electrode according to the present application are due to the structure in which the Pt layer is laminated on the compound semiconductor containing n-type InGaAs as a main component, the Ti / Pt / Au layer is formed on the Pt layer. Even in the case of an ohmic electrode in which metal layers other than the above are laminated, the contact resistance does not fluctuate when stored for a long time in a high temperature environment and has high reliability.

(Embodiment 3) The present inventors
The following analysis was performed on the semiconductor device manufactured by forming the ohmic electrode on the compound semiconductor containing InGaAs as the main component by the same method as in Embodiment 2. That is, a semiconductor device 400 having a structure as shown in FIG. 19 was prepared, and the vicinity of the interface between the InGaAs layer 72 and the Pt layer 73 in contact with the InGaAs layer 72 was analyzed by a transmission electron microscope. The semiconductor device 400 has an InGaAs layer 72 and a thickness of 200 on a semi-insulating InP substrate 71.
Angstrom Pt layer 73 and Ti layer 341, P
Ti / P consisting of three layers of t layer 342 and Au layer 343
The t / Au electrode layer 74 is sequentially formed. Specifically, first, the surface of the semi-insulating InP substrate 71 is washed with acid, and then the InGaAs layer 72 is epitaxially grown. Then, Pt is vapor-deposited on the InGaAs layer 72, and subsequently, Ti, Pt, and Au are vapor-deposited on Pt sequentially. After that, if the Pt layer 73, the Ti layer 341, and the Pt layer 3 are annealed for 1 minute in an atmosphere of about 400 ° C.
42 and the Au layer 343 are formed. As a result, In
The ohmic electrode 75 is formed on the GaAs layer 72, and the semiconductor device 400 of this embodiment is completed.

When the InGaAs layer 72 was p-type and n-type, respectively, the semiconductor device 400 was stored in a high temperature environment of 250 ° C. for 200 hours and then analyzed by a transmission electron microscope. ,
The vicinity of the interface between the InGaAs layer 72 and the Pt layer 73 was stable, and there was no phenomenon such that the material of the electrode layer 74 formed on the Pt layer 73, particularly Au, diffused into the InGaAs layer 72. .

Furthermore, the present inventors have found that the InGaAs layer 7
Qualitative analysis was performed by the energy dispersive X-ray spectroscopy (EDX) and the X-ray diffraction method in the vicinity of the boundary surface between the 2 and the Pt layer 73. The analysis results when the InGaAs layer 72 is n-type are shown in FIGS. Here, FIG. 20 shows EDX.
FIG. 21 shows the result of elemental analysis by X.
2 shows the results of composition analysis by line diffraction. FIG.
In, the peak labeled Pt _x In _y indicates that some alloy of Pt and In is present. PtIn and PtI are alloys of Pt and In.
Since there are n ₂ , Pt ₃ In ₂ , Pt ₄ In ₃ , Pt ₁₃ In _9, and the like, one of these alloys is present near the interface between the InGaAs layer 72 and the Pt layer 73, as shown in FIG. One or two or more exist. Note that FIG.
In, the alloy of Pt and In is represented by a dot pattern.

Since the alloy of Pt and In is thermally stable, the presence of such an alloy layer at the boundary between the InGaAs layer 72 and the Pt layer 73 means that the semiconductor device of the present embodiment is operated under a high temperature environment. This is one factor that prevents the material of the ohmic electrode 75, especially Au, from diffusing into the InGaAs layer 72 when 400 is stored. Therefore, as in the present embodiment, a compound semiconductor containing InGaAs as a main component,
A semiconductor device including an ohmic electrode having a Pt layer provided in contact with the compound semiconductor and containing an alloy of Pt and In near the interface between the InGaAs layer and the Pt layer has a high temperature environment. Even when placed underneath, the diffusion of the electrode material into the compound semiconductor is suppressed, so that the contact resistance varies little and has high reliability.

Further, an optoelectronic integrated circuit (hereinafter abbreviated as OEIC) can be manufactured by integrating such a semiconductor device using a normal integration technique, and such an OEIC is also described above. The excellent properties of semiconductor devices lead to their high reliability.

The semiconductor device according to the present application is not limited to the above embodiment, but various modifications can be made. For example, the ohmic electrode 75 included in the semiconductor device 400 of the present embodiment has the Pt layer 73 with Ti / Pt /
The Au layer 74 is laminated, but this Ti / Pt
Instead of the / Au layer 74, another metal layer may be laminated. The excellent property of the semiconductor device according to the present application is that In
Since the alloy of Pt and In exists near the boundary surface between the compound semiconductor containing GaAs as a main component and the Pt layer in contact with the compound semiconductor, Ti / Pt is formed on the Pt layer.
A semiconductor device in which metal layers (Ti / Au, Mo / Au, etc.) other than the / Au layer are laminated also has high reliability.

[0076]

As described in detail above, the first ohmic electrode according to the present invention is an ohmic contact in which a Pt layer having a thickness of 400 Å or less is in contact with a compound semiconductor whose main component is p-type InGaAs. Due to its excellent properties, it has sufficiently low resistance and high reliability.

Further, the second ohmic electrode according to the present application exhibits sufficiently low resistance based on the excellent property of the ohmic contact in which the Pt layer is in contact with the compound semiconductor whose main component is n-type InGaAs. , Has high reliability.

Next, a semiconductor optical device or a semiconductor electronic device provided with the first or second ohmic electrode according to the present application, and an optoelectronic integrated circuit in which these are integrated are excellent as the first or second ohmic electrode according to the present application. It has high reliability based on its characteristics.

Next, since the alloy of Pt and In contains the vicinity of the interface between the compound semiconductor and the Pt layer in the semiconductor device according to claim 7 of the present application, when the semiconductor device is stored in a high temperature environment. In addition, the contact resistance varies little and has high reliability.

The optoelectronic integrated circuit in which the semiconductor device according to claim 7 of the present application is integrated has high reliability because of the excellent properties of the semiconductor device according to claim 7 of the present application.

Next, in the first ohmic electrode forming method according to the present application, a Pt layer is vapor-deposited on a compound semiconductor containing p-type InGaAs as a main component to form a compound semiconductor and Pt.
Since an alloy of Pt and In is formed in the vicinity of the interface with the layer,
The semiconductor device according to claim 7 of the present application can be easily manufactured.

In the second ohmic electrode forming method according to the present application, the compound semiconductor and the Pt layer are formed by depositing the Pt layer on the compound semiconductor whose main component is n-type InGaAs.
Since an alloy of Pt and In is formed in the vicinity of the interface with the layer,
The semiconductor device according to claim 7 of the present application can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view showing a structure of an ohmic electrode according to a first embodiment.

FIG. 2 shows InGa including an ohmic electrode according to the first embodiment.
It is a schematic cross section which shows As pin PD.

FIG. 3 shows InGa including an ohmic electrode according to the first embodiment.
It is a schematic cross section which shows As HBT.

FIG. 4 is a graph showing changes in the contact resistivity of the ohmic electrode of Embodiment 1 when the thickness of the Pt layer is changed between 0 and 400 angstroms.

FIG. 5 is a graph showing variations in on-voltage (V _ON ) under a high temperature environment.

FIG. 6 is a graph showing variations in contact resistance (Rc) under a high temperature environment for ohmic electrodes having Pt layer thicknesses of 50 and 100 Å.

FIG. 7 is a graph showing changes in contact resistance (Rc) under a high temperature environment for ohmic electrodes having Pt layer thicknesses of 200 and 400 Å.

FIG. 8 is a graph showing changes in contact resistance (Rc) under a high temperature environment for a conventional Ti / Pt / Au electrode.

FIG. 9 is a schematic cross-sectional view showing an optoelectronic integrated circuit including an ohmic electrode according to the first embodiment.

FIG. 10 is a schematic cross-sectional view showing the structure of the ohmic electrode of the second embodiment.

FIG. 11 is an InG provided with an ohmic electrode according to the second embodiment.
It is a schematic cross section which shows aAs pin PD.

FIG. 12 is an InG provided with an ohmic electrode according to the second embodiment.
It is a schematic cross section which shows aAs HBT.

FIG. 13 is a graph showing changes in contact resistance (Rc) under a high temperature environment for the Pt / Ti / Pt / Au electrode of the second embodiment.

FIG. 14 is a graph showing changes in contact resistance (Rc) under a high temperature environment for the Ti / Pt / Au electrode of the comparative example.

FIG. 15 shows a conventional AuGe / Ni metal electrode,
It is a graph which shows the change of contact resistance (Rc) under a high temperature environment.

FIG. 16 is a schematic cross-sectional view showing the structure of an ohmic electrode of a comparative example.

FIG. 17 is a schematic cross-sectional view showing the structure of the conventional ohmic electrode.

FIG. 18 is a pin including an ohmic electrode according to the second embodiment.
It is a schematic cross section which shows the optoelectronic integrated circuit which integrated PD and HBT.

FIG. 19 is a schematic cross-sectional view showing the structure of the semiconductor device according to the third embodiment.

FIG. 20 is a diagram showing a result of qualitative analysis performed by energy dispersive X-ray spectroscopy (EDX) on the semiconductor device of Embodiment 3;

FIG. 21 is a diagram showing a result of qualitative analysis performed by an X-ray diffraction method on the semiconductor device of Embodiment 3;

[Explanation of symbols]

1, 21 and 71 ... Semi-insulating InP substrate, 2 ... P-type In
GaAs layer, 22 ... N-type InGaAs layer, 3, 23 and 73 ... Pt layer, 4, 24 and 74 ... Ti / Pt / Au electrode layer, 5, 25 and 75 ... Ohmic electrode, 41, 24
1 and 341 ... Ti layer, 42, 242 and 342 ... Pt
Layer, 43, 243 and 343 ... Au layer, 400 ... Semiconductor device.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location // H01L 27/15 H01L 29/46 R 31/10 H

Claims (12)

[Claims] 1. An ohmic electrode comprising a Pt layer having a thickness of about 400 angstroms or less, which is in contact with a p-type InGaAs-based compound semiconductor. 2. An ohmic electrode comprising a Pt layer in contact with a compound semiconductor containing n-type InGaAs as a main component. 3. Ti sequentially deposited on the Pt layer
The ohmic electrode according to claim 1 or 2, further comprising a layer, a Pt layer, and an Au layer. 4. A semiconductor optical device comprising the ohmic electrode according to claim 1. 5. A semiconductor electronic device comprising the ohmic electrode according to claim 1. 6. An optoelectronic integrated circuit in which the semiconductor optical device according to claim 4 and the semiconductor electronic device according to claim 5 are integrated. 7. A semiconductor device comprising a compound semiconductor containing p-type or n-type InGaAs as a main component, and an ohmic electrode having a Pt layer provided on and in contact with the compound semiconductor. In the vicinity of the interface between the semiconductor and the Pt layer, P
A semiconductor device comprising an alloy of t and In. 8. The alloy is PtIn, PtIn ₂ , P
The semiconductor device according to claim 7, which is one or more alloys selected from the group consisting of t ₃ In ₂ , Pt ₄ In ₃ , and Pt ₁₃ In ₉ . 9. An optoelectronic integrated circuit in which the semiconductor device according to claim 7 is integrated. 10. A first step of depositing a Pt layer having a thickness of about 400 Å or less on a compound semiconductor containing p-type InGaAs as a main component, and forming a predetermined metal layer on the Pt layer. A second step; and a method for forming an ohmic electrode, comprising: 11. A first step of depositing a Pt layer on a compound semiconductor containing n-type InGaAs as a main component, and a second step of forming a predetermined metal layer on the Pt layer. A method for forming an ohmic electrode, comprising: 12. The ohmic electrode forming method according to claim 10, wherein the second step is a step of sequentially forming a Ti layer, a Pt layer and an Au layer on the Pt layer. .