JPH0917965A - Semiconductor integrated circuit device, and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To materialize a RAM high in integration degree which has a nonvolatile memory function. SOLUTION: A memory cell MC is composed of a flip flop circuit consisting of MISFETs Qd1 and Qd2 for driving and MISFETs Qp1 and Qp2 , MISFETs Qt1 and Qt2 for transfer, and ferroelectric capacitors Qf1 and Qf2 connected, respectively, to the storage nodes N1 and N2 of the flip flop circuit. When the power of the memory cell is cut, the direction of polarization of ferroelectric capacitors Qf1 and Qf2 is set by controlling the power voltage VL and plate voltage Vp each, based on the information accumulated each in the storage nodes N1 and N2 , and the information accumulated in the storage nodes N1 and N2 is read out to the ferroelectric capacitors Cf1 and Cf2 and is kept.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technique, and more particularly to a technique effective when applied to a semiconductor integrated circuit device having a memory function.

[0002]

2. Description of the Related Art A RAM (Rand), which is a type of semiconductor memory,
om Access Memoey) has dynamic RAM (Dynami
c RAM, DRAM) and static RAM (Static
RAM, SRAM).

A memory cell of a DRAM is a MISFET (Metal Insulator Semiconductor) that functions as a switch.
A field effect transistor) and a capacitor for accumulating information charges, and this MISFET selectively couples the capacitor and a data line for transferring information of the memory cell to a peripheral circuit. Due to this simple structure, the DRAM memory cell can be manufactured in a small area and with high density.

However, since there is a leakage current in the pn junction of the MISFET, the amount of information charges initially given to the capacitor disappears due to this leakage current. That is, the stored information is destroyed. Therefore, it is necessary to read the memory cell before the charge amount completely disappears and periodically perform an operation (refresh operation) of giving a sufficient initial charge amount to the capacitor based on the read information.

The point that the SRAM is composed of memory cells that do not need to perform the refresh operation is DRA.
Different from M. The memory cell of the SRAM is composed of a flip-flop circuit for storing information and two transfer MISFETs. By turning on the transfer MISFET, the data pair line (DL ₁ , Dl ₂ ) and the flip-flop circuit are connected. Information is exchanged.

At the time of writing, a high voltage ("H") is applied to one of the data pair lines, and a low voltage ("L") is applied to the other, which is applied to a pair of storage nodes. Combination (DL ₁ and DL ₂ are "H" and "L" respectively)
Alternatively, "L", "H") is associated with binary write information.

Reading is performed by detecting the voltage appearing on the data pair line corresponding to the combination of the high and low voltages of the pair of storage nodes. Even if there is a leak current in the storage node, as long as the power supply of the flip-flop circuit is applied, the reduced charge amount is supplied from the power supply through the load, so that the refresh operation is not necessary.

However, since the SRAM memory cell has a large number of elements, the cell area is larger than that of the DRAM memory cell, and therefore it cannot be mounted on a semiconductor chip at a high density.

Both DRAM and SRAM have the advantage of being randomly accessible, but have volatile memory cells. That is, information is lost when the power is turned off from the memory cell. D
In the RAM, the charge stored in the capacitor in the memory cell disappears, and in the SRAM, the voltage holding the flip-flop state in the memory cell drops to 0V, so that the flip-flop loses the information.

Therefore, the MISFE functioning as a switch
A RAM (Ferroelectric RAM, FRAM) using a memory cell composed of T and a ferroelectric capacitor has been developed. This FRAM is a non-volatile memory. In other words, a ferroelectric capacitor is one in which a ferroelectric material is inserted between a pair of electrode plates, and the polarization state of the ferroelectric material does not change even when the power supply is turned off from the memory cell, so information is stored. to continue.

Ferroelectric materials have two different stable polarization states, which are defined by a hysteresis loop shown by plotting polarization against applied voltage. The polarization state of the ferroelectric material can be determined by measuring the charge that flows when a voltage is applied to the ferroelectric capacitor.

By assigning a binary value "0" to one polarization state and a binary value "1" to the other polarization state, the ferroelectric capacitor can be used for storing binary information. . However, when a ferroelectric capacitor is used as an information storage element of a memory cell, the ferroelectric capacitor is repeatedly inverted from one polarization state to the other polarization state, and the ferroelectric material deteriorates due to fatigue. , The polarization charge is reduced.

Therefore, a ferroelectric capacitor is used,
A high-speed, long-life non-volatile semiconductor memory capable of random access and solving the problem of polarization fatigue of the ferroelectric material is provided.

For example, it is a non-volatile semiconductor memory in which a volatile memory cell of SRAM and a ferroelectric circuit described in JP-A-64-66899 are combined. This semiconductor memory is composed of a memory cell MC in which a ferroelectric circuit is connected to each storage node of a flip-flop circuit forming a memory cell of SRAM via a coupling transistor.

During the normal operation of the memory cell MC, the coupling transistor is turned off to disconnect the flip-flop circuit and the ferroelectric circuit. Therefore, the memory cell MC is S
It functions perfectly as a memory cell of RAM, and can access and read / write information to / from a flip-flop circuit by its data line and word line.

However, when the power is cut off from the memory cell, the coupling transistor is turned on, the flip-flop circuit and the ferroelectric circuit are connected, and the information of the flip-flop circuit is read to the ferroelectric circuit.
Store the information.

Therefore, the memory cell MC is normally SRA.
It operates as an M memory cell, but does not lose information even when the power is turned off. Further, since the ferroelectric circuit is used only when the power of the memory cell MC is turned off, the FRA
Compared with M, the number of times the ferroelectric material of the memory cell MC undergoes polarization reversal is reduced, and the life of the ferroelectric material is significantly extended.

Next, the operating characteristics of the memory cell MC will be described. The power supply voltage of the flip-flop circuit is V _CC
, The voltage of each storage node is at high level (V _CC ) and low level (reference voltage V _SS ).
The reference voltage V _SS is, for example, 0 V (ground potential),
The power supply voltage V _CC is, for example, 5V.

When the coupling transistor connected to the high level (V _CC ) storage node is turned on, the voltage of the upper plate of the ferroelectric capacitor connected to this storage node rises to V _CC . At this time, assuming that the voltage of the lower plate of the ferroelectric capacitor is V _SS , the ferroelectric capacitor is driven to one polarization state (referred to as “high” polarization state).

On the other hand, when the coupling transistor connected to the low level (V _SS ) storage node is turned on, the voltage of the upper plate of the ferroelectric capacitor connected to the storage node becomes V _SS . At this time, when the voltage of the lower plate of the ferroelectric capacitor is V _CC , the ferroelectric capacitor is driven to the other polarization state (referred to as "low" polarization state).

In this way, the high level of the storage node of the flip-flop circuit is stored in the "high" polarization state in the ferroelectric capacitor connected to this storage node, and the low level of the storage node is stored in this storage node. It is stored in the "low" polarization state in the connected ferroelectric capacitor. Even if the power is turned off from the memory cell MC, the polarization state of the ferroelectric capacitor still exists, so that the information is retained in the ferroelectric circuit.

When power is supplied to the memory cell MC again, the coupling transistor is turned on, the flip-flop circuit and the ferroelectric circuit are connected, and information is recovered from the ferroelectric circuit and written in the flip-flop circuit. .

First, the pair of storage nodes of the flip-flop circuit are both precharged to 0V. After that, the voltage of the lower plate of the ferroelectric capacitor is set to V _CC , and then the coupling transistor is turned on. This time,"
Ferroelectric capacitors in the "high" polarization state cause polarization reversal.

The ferroelectric capacitor having the polarization inversion supplies a larger current to the corresponding storage node of the flip-flop circuit than the ferroelectric capacitor written in the other "low" polarization state. By utilizing this current imbalance, each storage node of the flip-flop circuit is set so that the storage node on the high current side corresponds to the high level.

Thus, the "high" of the ferroelectric capacitor
The polarization state causes the storage node of the flip-flop circuit connected to this ferroelectric capacitor to be at a high level (V _CC ).
The "low" polarization state of the ferroelectric capacitor causes the storage node of the memory cell connected to this ferroelectric capacitor to be at a low level (V _SS ).

[0026]

However, in the nonvolatile semiconductor memory obtained by combining the flip-flop circuit and the ferroelectric circuit,
It has been found by the present inventors that the following problems exist.

That is, a coupling transistor is arranged between the flip-flop circuit and the ferroelectric circuit,
The pair of storage nodes of the flip-flop circuit are coupled to the upper plates of the pair of ferroelectric capacitors via the source region-drain region paths of the pair of coupling transistors.

By turning off the coupling transistor, the flip-flop circuit is disconnected from the ferroelectric circuit, the voltage transition occurring at the storage node is not directly transmitted to the ferroelectric capacitor, and the memory cell MC is SRAM.
Function as a memory cell. Further, by turning on the coupling transistor, it becomes possible to exchange information between the flip-flop circuit and the ferroelectric circuit.

Therefore, the coupling transistor is an important gate for operating the memory cell MC. However, by providing the coupling transistor, the area of the memory cell MC becomes large, and it is difficult to realize high integration of the semiconductor memory.

It is an object of the present invention to provide a technique capable of realizing a highly integrated RAM having a non-volatile memory function.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0032]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, (1) the semiconductor integrated circuit device of the present invention is connected to each of the SRAM memory cell including the transfer MISFET controlled by the word line and the flip-flop circuit, and the two storage nodes included in the flip-flop circuit. It has a memory cell having a non-volatile function, which is composed of two ferroelectric capacitors.

(2) Further, the semiconductor integrated circuit device of the present invention is the semiconductor integrated circuit device according to (1), wherein the flip-flop circuit comprises a load MISFET and a drive MIS.
It is composed of a pair of cross-coupled CMOS transistors formed of FETs, and further has a first node coupled to a first operating voltage source, a second node coupled to a reference voltage source, and two storage nodes. In addition, one plate of each of the two ferroelectric capacitors is connected to the storage node of the flip-flop circuit, and the other plate of each of the two ferroelectric capacitors is connected to the second operating voltage. Connected to a third node coupled to the source.

(3) Further, the semiconductor integrated circuit device according to the present invention is the semiconductor integrated circuit device according to (1), in which a load MISFET and a drive MISFET constituting a transfer MISFET and a flip-flop circuit are provided above the load MISFET and the drive MISFET. A ferroelectric capacitor is formed.

(4) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (3), in which the transfer MI is first formed on the main surface of the semiconductor substrate.
After forming the SFET and the driving MISFET, a load MISFET having a bottom gate structure is formed above the driving MISFET. Next, a contact hole reaching the silicon film is formed in the insulating film deposited on the silicon film forming the drain region of the load MISFET. Next, after depositing the first conductive film on the semiconductor substrate, the first conductive film is processed to form one plate of the ferroelectric capacitor connected to the silicon film. Then, a ferroelectric film and a second conductive film are sequentially deposited on the semiconductor substrate, the second conductive film is processed to form the other plate of the ferroelectric capacitor, and then the ferroelectric film is formed. The film is processed to form a ferroelectric capacitor.

(5) The method for manufacturing a semiconductor integrated circuit device according to the present invention is the method for manufacturing a semiconductor integrated circuit device according to (3), in which the transfer MI is first formed on the main surface of the semiconductor substrate.
Driving MIS having SFET and common gate electrode
An FET and a load MISFET are formed. Next, a contact hole reaching the silicon film is formed in the insulating film deposited on the silicon film forming the common gate electrode of the driving MISFET and the load MISFET. Next, after depositing the first conductive film on the semiconductor substrate, the first conductive film is processed to form one plate of the ferroelectric capacitor connected to the silicon film. Next, after sequentially depositing a ferroelectric film and a second conductive film on the semiconductor substrate, the second conductive film is processed to form the other plate of the ferroelectric capacitor, and then the ferroelectric film. Is processed to form a ferroelectric capacitor.

[0037]

According to the above-mentioned means, it is possible to realize a memory cell having a non-volatile function with a structure in which a ferroelectric capacitor is directly connected to each storage node of a flip-flop circuit, and a transfer MISFET. , A load MISFET and a drive M that form a flip-flop circuit
Since the ferroelectric capacitor can be formed above the ISFET, it is possible to prevent the memory cell area from increasing due to the provision of the ferroelectric capacitor. Therefore, it is possible to form a ferroelectric capacitor that can retain information in the storage node of the flip-flop circuit without increasing the area of the memory cell and thus the highly integrated RAM having a nonvolatile memory function. Can be realized.

[0038]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A RAM having a nonvolatile memory function according to an embodiment of the present invention and a method of manufacturing the RAM will be described with reference to FIGS. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 shows a transfer M of this embodiment.
An equivalent circuit diagram of a memory cell MC in which an SRAM memory cell composed of ISFETs Qt ₁ and Qt ₂ and a flip-flop circuit and ferroelectric capacitors Cf ₁ and Cf ₂ are combined is shown. As shown in the figure, the memory cell MC has two n-channel MISFETs (driving MISFETs) Qd.
₁ , Qd ₂ and two p-channel MISFETs (MI for load)
SFET) Qp ₁ and Qp ₂ are included in the flip-flop circuit.

The transfer MISFETs Qt ₁ and Qt ₂ connect the storage nodes N ₁ and N ₂ of the flip-flop circuit to the data lines DL ₁ and
Bind to DL ₂ respectively. Transfer MISFET Qt ₁ ,
The gate electrode of Qt ₂ is coupled to word line WL.

Further, the storage node N _1, N ₂ is the ferroelectric capacitor Cf _1, Cf one are respectively coupled to the electrode plate _2, the other plate of the ferroelectric capacitor Cf _1, Cf ₂ nodes electrically coupled with N _3, the node N ₃ plate voltage (V _P) is applied.

The ferroelectric capacitors Cf ₁ and Cf
₂ is composed of one electrode plate, the other electrode plate, and a ferroelectric film formed between these electrode plates.

First, the operating characteristics of the memory cell MC will be described with reference to the equivalent circuit diagrams shown in FIGS. 2 to 8, the transfer MISFET Qt ₁ ,
Qt ₂ is omitted.

Further, FIG. 9 is a timing chart of switching of the power supply voltage (V _L ) and plate voltage (V _P ) of the flip-flop circuit, and FIG. 10 is a voltage change at the storage node N ₁ and the storage node N _2. Indicates.

During the normal operation from instant t ₀ to t ₁ ,
V _CC is applied to the power supply of the flip-flop circuit. As a result, one storage node of the flip-flop circuit becomes high level (V _CC ) and the other storage node becomes low level (V _SS ).

At this time, the power supply voltage V _CC is set within a voltage range in which polarization inversion does not occur in the ferroelectric capacitor connected to the storage node, and the ferroelectric capacitors Cf ₁ and Cf.
The plate voltage applied to one of the plates of f ₂ is set to the ground potential. Therefore, even if one of the storage nodes rises to the high level (V _CC ), the ferroelectric capacitors Cf ₁ and Cf ₂ connected to it have the "high" polarization state as they are. Are retained, and those in the "low" polarization state are also retained in the "low" polarization state without reversing the polarization.

That is, as shown in FIG. 23, the electric field E _v due to the power supply voltage V _CC is set to be smaller than the electric field E _R which causes polarization reversal. 23 shows a hysteresis loop of the ferroelectric film of the ferroelectric capacitor, the horizontal axis shows the electric field E, and the vertical axis shows the polarization R.

That is, when the flip-flop circuit is operated at the power supply voltage V _CC , the memory cell MC is S.
It functions as a memory cell of RAM, and its data line DL ₁ ,
Information can be read from and written to the flip-flop circuit by being accessed by DL ₂ and the word line WL.

Although not particularly limited, _{one of} the ferroelectric capacitors Cf ₁ and Cf ₂ is kept in the “high” polarization state and the other is kept in the “low” polarization state during normal operation.

Next, a method of reading information from the flip-flop circuit to the ferroelectric capacitors Cf ₁ and Cf ₂ will be described (FIGS. 2 and 3).

When it is necessary to transfer the information stored in the flip-flop circuit to the ferroelectric capacitors Cf ₁ and Cf _{2 at the} instant t ₁ , it is necessary to transfer the information to the ferroelectric capacitors Cf ₁ and Cf ₂ while keeping the plate voltage at V _SS . The power supply voltage is increased from V _CC to V _CC '. For the sake of explanation, the information stored in the flip-flop circuit at the instant t ₁ is that the storage node N ₁ is at high level (V _CC ') and the storage node N ₂ is at low level (V _SS ). To do.

V _CC 'is a ferroelectric capacitor Cf ₁ , Cf
_The voltage is sufficient to invert the polarization of ₂ . That is,
The electric field due to V _CC 'is larger than the electric field E _R that causes polarization reversal. Since the node N ₃ is at the low level (V _SS ) and the voltage of the storage node N ₁ rises, as shown in FIG.
Strongly connected to the storage node N ₁ dielectric capacitors Cf ₁
The "high" polarization state is written to.

The ferroelectric capacitor Cf ₁ maintains the “high” polarization state as it is if the state at the instant t ₀ is the “high” polarization state. When the state at the instant t ₀ is the “low” polarization state, the polarization inversion occurs and the state is rewritten to the “high” polarization state. At this time, the polarization inversion current changes to the load MISFET.
It flows from qp ₁ to the storage node N _1, the storage node N ₁
The voltage at fluctuates.

However, the voltage (V ₁ ) at the storage node N ₁ depends on the capacitance (C ₁ ) of the ferroelectric capacitor Cf ₁ and the load MIS.
It is determined by the parasitic capacitance (C ₂ ) of the FET Qp ₁ and the storage node N ₁ , and is represented by the following equation (1). Equation (1) V ₁ = (C ₁ / (C ₁ + C ₂ )) V _CC ′ Normally, C ₁ is much larger than C ₂ , so V
₁ will be approximately V _CC '.

Next, it is necessary to transfer information to the ferroelectric capacitor Cf ₂ connected to the storage node N ₂ . Instantaneous t _2, 'while set, a plate voltage from V _SS V _CC' power supply voltage of the flip-flop circuit is V _CC increases the node N ₃ is raised to a high level (V _CC '). As shown in FIG. 3, since the storage node N ₂ is at a low level (V _SS ), the ferroelectric capacitor C connected to the storage node N ₃ is
The "low" polarization state is written into f ₂ .

As in the case of the "high" write, the ferroelectric capacitor Cf ₂ is maintained in the "low" polarization state as it is if the state at the instant t ₁ is the "low" polarization state. When the state at the instant t ₁ is the “high” polarization state, polarization inversion occurs and is rewritten to the “low” polarization state. At this time, the polarization inversion current is transferred from the storage node N ₂ to the driving MISFET Q.
The voltage of the storage node N ₂ fluctuates by flowing to d ₂ .

However, the voltage (V ₂ ) at the storage node N ₂ also depends on the capacitance (C ₁ ) of the ferroelectric capacitor Cf ₂ and the driving MIS.
It is determined by the parasitic capacitance (C ₃ ) of the FET Qd ₂ and the storage node N ₂ , and is represented by the following equation (2). Equation (2) V ₂ = (C ₁ / (C ₁ + C ₃ )) V _SS Normal C ₁ is much larger than C ₃ , so V
₂ is approximately V _SS .

[0059] instant t _1, by the operation of t _2, information of the flip-flop circuit ferroelectric capacitor Cf _1, Cf ₂
Is accumulated in The high level (V _CC ') of one storage node N ₂ is the ferroelectric capacitor Cf connected to it.
Corresponding to the "high" polarization state written in ₁ , the low level (V _SS ) of the other storage node N ₂ becomes the "low" polarization state written in the ferroelectric capacitor Cf ₂ connected to it. Correspond.

At the instant t ₃ , all the voltages become 0 V, and even if the information at the storage nodes N ₁ and N ₂ is lost, the polarization states of the ferroelectric capacitors Cf ₁ and Cf ₂ continue to exist.
Information of the flip-flop circuit is used as the ferroelectric capacitor Cf.
It can be held at ₁ and Cf ₂ .

Next, a method of writing information from the ferroelectric capacitors Cf ₁ and Cf ₂ to the flip-flop circuit will be described with reference to FIGS. 4 to 8.

At the instant t ₄ , the ferroelectric capacitors Cf ₁ and Cf
When it is necessary to post the information stored in the ₂ to the flip-flop circuit, while maintaining the supply voltage of the flip-flop circuit to V _SS, thereby increasing the plate voltage from V _SS to V _CC '. Since the power supply voltage is set to V _SS , the load MISFETs Qp ₁ and Qp ₂ are always off.

However, at the instant t ₄ , the load MIS is
A current flows from the FET Qp ₁ and the driving MISFET Qd ₁ to the storage node N _1, and the voltage of the storage node N ₁ rises to the instant V _N1 . Similarly, the load MISFET Qp
₂ and the driving MISFET Qd ₂ to the storage node N ₂
Current flows into the voltage of the storage node N ₂ rises instantaneously V _N1. V _N1 is the capacitance of the ferroelectric capacitors Cf ₁ and Cf ₂ , the load MISFETs Qp ₁ and Qp ₂ and the drive MI.
The voltage level is determined by the parasitic capacitance of the SFETs Qd ₁ and Qd ₂ .

[0064] Voltage of the storage node N _1, N ₂ rises to V _N1, the V _N1 is higher than the threshold voltage of the driving MISFETQd _1, Qd _2, driving MISFET Qd _1, Qd
₂ is turned on. As a result, a current flows from the storage node N ₁ to the driving MISFET Qd _1, and the voltage of the storage node N ₁ drops to almost 0V. Similarly, a current flows from the storage node N ₂ to the driving MISFET Qd _2, and the voltage of the storage node N ₂ drops to almost 0V.

As a result, at the instant t ₅ , the ferroelectric capacitor Cf whose state at the instant t ₄ is the “high” polarization state.
₁ is rewritten to "low" polarization state. Note that the instant t ₄
Ferroelectric capacitor C whose state is a "low" polarization state
f ₂ remains in the “low” polarization state.

When the ferroelectric capacitor Cf ₁ undergoes polarization reversal, a polarization reversal current flows and the voltage (V _N2 ) at the storage node N ₁ becomes higher than the voltage (V _N3 ) at the storage node N ₂ . A potential difference is generated between the storage node N ₁ and the storage node N ₂ . In this state, when the power supply voltage of the flip-flop circuit is raised to V _CC 'at the instant t ₆ , positive feedback is applied to the flip-flop circuit, the storage node N ₁ goes high (V _CC '), and the storage node N ₂ goes. Is set to a low level (V _SS ).

Next, the plate voltage is lowered to V _SS at the instant t ₇ , and the ferroelectric capacitor Cf ₁ in the "low" polarization state at the instant t ₆ is rewritten to the "high" polarization state. lowering the power supply voltage of the flip-flop circuit to V _CC at t _8. Thus, the voltage of the storage node N ₁ is set from the V _CC 'to V _CC, returns to the ascertained by routine operation.

By the above method, the normal operation of the flip-flop circuit, the reading of information from the flip-flop circuit to the ferroelectric capacitors Cf ₁ and Cf ₂ , and the writing of information from the ferroelectric capacitor to the flip-flop circuit are carried out. The action is taken.

Next, a specific first example of the memory cell MC will be described.
The configuration (memory cell MC ₁ ) will be described with reference to FIGS. 11 to 16.

12 to 16 show the ferroelectric capacitor Cf ₁ ,
A plan view of a memory cell MC ₁ provided with Cf ₂ (a plan view of a semiconductor substrate showing approximately one memory cell MC ₁ ) is shown.
FIG. 11 is a sectional view of the semiconductor substrate taken along the line (a)-(a) 'of FIG. The flip-flop circuit of the memory cell MC ₁ has a TFT (Thin Film Transistor) type S.
This is the same as the flop flop circuit used for the memory cell of the RAM.

As shown in FIG. 11, on the main surface of the semiconductor substrate (semiconductor chip) 1 made of n ^-- type silicon single crystal,
A p ⁻ type well 2 is formed, and a field insulating film 4 for element isolation made of a silicon oxide film is formed on the main surface of the inactive region of the p ⁻ type well 2. A p-type channel stopper region 5 for preventing inversion is formed under the field insulating film 4.

Driving MIS that constitutes the memory cell MC _1.
FETs Qd ₁ and Qd ₂ , transfer MISFETs Qt ₁ and Qt ₂
Of the load MISFETs Qp ₁ and Qp ₂ and the drive MISFETs Qd ₁ and Qd ₂ and the transfer MISFET Q.
Each of t ₁ and Qt ₂ is formed on the main surface of the active region of the p ⁻ type well 2 surrounded by the field insulating film 4.

Each of the driving MISFETs Qd ₁ and Qd ₂ is composed of a gate insulating film 6, a gate electrode 7, a source region and a drain region. Gate electrode 7
Are formed in the gate material forming step of the first layer, and are formed of, for example, a polycrystalline silicon film. An n-type impurity (for example, phosphorus (P)) is introduced into this polycrystalline silicon film in order to reduce its resistance value.

An insulating film 8 is formed on the gate electrodes 7 of the driving MISFETs Qd ₁ and Qd ₂ . The insulating film 8 is made of, for example, a silicon oxide film. Also,
Sidewall spacers 9 are formed on the side walls of the gate electrode 7 in the gate length direction. The sidewall spacer 9 is made of, for example, a silicon oxide film.

The source region and drain region of each of the driving MISFETs Qd ₁ and Qd ₂ are composed of a low impurity concentration n ⁻ type semiconductor region 10 and a high impurity concentration n ⁺ type semiconductor region 11 provided thereabove. It is configured.
That is, each of the driving MISFETs Qd ₁ and Qd ₂ has a so-called double diffused drain (source diffused drain) structure.

The field insulating film 4 and the driving MISFETs Qd ₁ and Qd ₂ formed on the main surface of the semiconductor substrate 1.
FIG. 12 shows the pattern layout of the gate electrode 7 of FIG.
In the figure, two L-shaped regions 3 surrounded by the field insulating film 4 are active regions for one memory cell MC ₁ .

As shown in FIG. 12, the drive MISF is used.
One end side of each of the gate electrodes 7 of ETQd ₁ and Qd ₂ projects above the field insulating film 4 by at least the amount corresponding to the mask alignment margin dimension in the manufacturing process. In addition, the gate electrode 7 of the driving MISFET Qd ₁
The other end of the (Qd ₁₎ is projected to the field insulating film 4 on the drain region of the driving MISFET Qd ₂ through the other end of the gate electrode 7 of the drive MISFETQd ₂ (Qd ₂₎ the field insulating film 4 For driving MISFET
It projects above the drain region 7 of Qd ₁ .

As shown in FIG. 11, each of the transfer MISFETs Qt ₁ and Qt ₂ of the memory cell MC ₁ is composed of a gate insulating film 12, a gate electrode 13A, a source region and a drain region.

The gate electrode 13A is formed in the gate material forming step of the second layer, and is composed of, for example, a laminated film (polycide film) of a polycrystalline silicon film and a refractory metal silicide film. An n-type impurity (for example, P) is introduced into the lower polycrystalline silicon film in order to reduce its resistance value. The upper refractory metal silicide film is, for example, WSi.
x, MoSix, TiSix, TaSix, etc.

[0080] On top of the gate electrode 13A of the transfer MISFETQt _1, Qt _2, the insulating film 15 is formed. The insulating film 15 is made of, for example, a silicon oxide film. A sidewall spacer 16 is formed on the sidewall of the gate electrode 13A. The sidewall spacer 16 is made of, for example, a silicon oxide film.

The source region and drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ are composed of a low impurity concentration n ⁻ type semiconductor region 17 and a high impurity concentration n ⁺ type semiconductor region 18. That is, the MI for transfer
The source region and the drain region of the SFETs Qt ₁ and Qt ₂ have an LDD (Lightly Doped Drain) structure.

FIG. 13 shows a pattern layout of the gate electrodes 13A of the transfer MISFETs Qt ₁ and Qt ₂ formed on the main surface of the semiconductor substrate 1. As shown in the figure, the gate electrodes 13A of the transfer MISFETs Qt ₁ and Qt ₂ are
The gate length (Lg) direction is the driving MISFET Qd ₁ ,
It is arranged so as to intersect the gate length (Lg) direction of the gate electrode 7 of Qd ₂ .

As shown in FIG. 13, transfer MISFET
_One of the source region and the drain region of Qt ₁ is formed integrally with the drain region of the driving MISFET Qd ₁ . Similarly, one of the source region and the drain region of the transfer MISFET Qt ₂ is connected to the drive MISFET Qd ₂
Is integrally formed with the drain region.

The word line WL is connected to the gate electrodes 13A of the transfer MISFETs Qt ₁ and Qt _{2 and} the transfer MIs are transferred.
The gate electrode 13A of SFETQt _1, Qt ₂ is constructed integrally with the word line WL.

A reference voltage line (V _SS ) 13B configured as a source line common to the _two driving MISFETs Qd ₁ and Qd ₂ is arranged in parallel with the word line WL.
The reference voltage line (V _SS ) 13B is a transfer MISFET Qt.
The gate electrode 13A of ₁ and Qt ₂ and the word line WL are formed in the same second gate material forming step, and extend on the field insulating film 4 in the same direction as the word line WL.

Further, the reference voltage line (V _SS ) 13B is connected to the driving MISFETs Qd ₁ and Qd ₂ through the contact hole 14 formed in the same insulating film as the gate insulating film 6 of the driving MISFETs Qd ₁ and Qd ₂ . Each source region (n ⁺ type semiconductor region 11) is connected.

Two load MISF of memory cell MC ₁
Of ETQp ₁ and Qp ₂ , load MISFET Qp
₁ is disposed on the region of the driving MISFET Qd ₂ ,
The load MISFET Qp ₂ is a drive MISFET Qd.
It is located on area ₁ . MISFET for load Qp
Each of ₁ and Qp ₂ is composed of a gate electrode 23A, a gate insulating film 24, a channel region 26N, a source region 26P and a drain region 26P.

The gate electrodes 23A of the load MISFETs Qp ₁ and Qp ₂ are formed in the third layer gate material forming step, and are formed of, for example, a polycrystalline silicon film. In order to reduce the resistance value of the polycrystalline silicon film,
A type impurity (for example, P) is introduced. MI for load
SFETQp _1, the pattern layout of the gate electrode 23A of Qp ₂ shown in FIG. 14.

As shown in FIGS. 11 and 14, the gate electrode 23A of the load MISFET Qp ₁ has a contact hole 22 formed in the insulating film 21 and the insulating film 8.
Through the gate electrode 7 of the driving MISFET Qd _{1 and one} of the source region and the drain region of the transfer MISFET Qt ₂ .

Similarly, the gate electrode 23A of the load MISFET Qp ₂ is driven by the driving MISFET through the contact hole 22 formed in the insulating film 21 and the insulating film 8.
Gate electrode 7 of Qd ₂ and transfer MISFET Qt ₁
Is connected to one of the source region and the drain region.

On top of the other of the source region and the drain region of the transfer MISFETs Qt ₁ and Qt ₂ is a load M.
The same third as the gate electrode 23A of the ISFETs Qp ₁ and Qp ₂
The pad layer 23B formed in the gate material forming step of the first layer is arranged. The pad layer 23B is transferred to the transfer MI through the contact hole 22 formed in the insulating film 21.
It is connected to the other of the source region and the drain region of the SFETs Qt ₁ and Qt ₂ .

As shown in FIG. 11, the load MISF is used.
The gate insulating film 24 of the load MISFETs Qp ₁ and Qp ₂ is formed on the gate electrodes 23A of the ETQp ₁ and Qp ₂ . The gate insulating film 24 is made of, for example, a silicon oxide film.

Above the gate insulating film 24 of the load MISFETs Qp ₁ and Qp ₂ , the load MISFETs Qp ₁ and Qp ₁ ,
A channel region 26N, a source region 26P and a drain region 26P of Qp ₂ are formed. Channel region 2
6N is formed in the fourth layer gate material forming step, and is made of, for example, a polycrystalline silicon film.

A load MIS is formed on the polycrystalline silicon film.
An n-type impurity (for example, P) is introduced to make the threshold voltages of the FETs Qp ₁ and Qp ₂ enhancement type. Channel regions 26N, source regions 26P and drain regions 26P of the load MISFETs Qp ₁ and Qp ₂
FIG. 14 shows the pattern layout of the above.

As shown in FIG. 15, the load MISF is used.
A drain region 26P is formed on one end side of the channel regions 26N of ETQp ₁ and Qp ₂ , and a source region 2 is formed on the other end side.
6P is formed. The drain region 26P and the source region 26P are formed in the same fourth layer gate material (polycrystalline silicon) forming step as the channel region 26N, and are integrally formed with the channel region 26N. A p-type impurity (for example, BF ₂ ) is introduced into the polycrystalline silicon film forming the drain region 26P and the source region 26P.

As described above, the load MISFETs Qp ₁ and Qp ₂ of the memory cell MC of the present embodiment have the fourth structure above the gate electrode 23A formed in the third-layer gate material forming step.
Channel region 26 formed in the gate material forming step of the second layer
It has a so-called bottom gate structure in which N, a source region 26P and a drain region 26P are arranged.

As shown in FIG. 15, the load MISF is used.
The drain region 26P of ETQp ₁ is the gate insulating film 24.
It is connected to the gate electrode 23A of the load MISFET Qp ₂ through a contact hole 25 formed in the insulating film of the same layer. Similarly, the drain region 26P of the load MISFET Qp ₂ is connected to the gate electrode 23A of the load MISFET Qp ₁ through the contact hole 25 formed in the insulating film in the same layer as the gate insulating film 24.

A power supply voltage line (V _L ) 26P is connected to the source regions 26P of the load MISFETs Qp ₁ and Qp ₂ . The power supply voltage line ( _VL ) 26P includes a channel region 26N, a drain region 26P and a source region 26P.
It is formed in the same fourth layer gate material (polycrystalline silicon) forming step as above, and is integrated with these.

As shown in FIG. 11, the above MISF for load is used.
Above the ETQp ₁ and Qp ₂ , the first interlayer insulating film 2 is formed.
7 are formed. The interlayer insulating film 27 is made of, for example, a silicon oxide film and a BPSG film.

First layer wirings 29A and 29B are formed on the interlayer insulating film 27. The first-layer wiring 29A is connected to the drain regions 26P of the load MISFETs Qp ₁ and Qp ₂ through the contact holes 28A formed in the interlayer insulating film 27.

The wiring 29B of the first layer is transferred through the contact holes 28B formed in the gate insulating film 24 and the interlayer insulating film 27, and the transfer MISFETs Qt ₁ and Qt _{2 are formed.}
Of the source region to the drain region of the pad layer 23B. Wiring 29 of the first layer
A and 29B are formed in the first layer wiring material forming step,
For example, it is made of a refractory metal film such as tungsten (W).

FIG. 16 shows a pattern layout of the first-layer wiring 29A. In the figure, in order to make the drawing easier to see, among the conductive layers below the first-layer wirings 29A and 29B, the fourth-layer gate material (load MISFET Qp ₁ ,
Qp ₂ channel region 26N, the source region 26P, drain region 26P and the power source voltage line and (V _L) 26P),
Third layer gate material (load MISFETs Qp ₁ , Qp ₂
Gate electrode 23A and pad layer 23B) of FIG.

As shown in FIG. 11, a ferroelectric film 31 is formed on the upper layer of the first-layer wiring 29A via a first barrier layer 30. The first barrier layer 30 is, for example, an iridium oxide (IrO ₂ ) film, and the ferroelectric film 3
Reference numeral 1 is, for example, a PZT (PbZrTiO ₃ ) film.

Further, in the upper layer of the ferroelectric film 31,
The plate electrode 33 is formed via the second barrier layer 32. The second barrier layer 32 is, for example, an IrO ₂ film, and the plate electrode 33 is, for example, a refractory metal film of W or the like. The first barrier layer 30 and the second barrier layer 32 are composed of the ferroelectric film 31 and the first-layer wiring 29A located thereunder, and the ferroelectric film 31 and the plate electrode 33 located above it. Is provided to prevent it from reacting.

A second-layer wiring (data line DL) 36 is arranged above the plate electrode 33 and the first-layer electrode 29B via a second-layer interlayer insulating film 34. The data line DL is connected to the first-layer wiring 29B through the contact hole 35 formed in the interlayer insulating film 34, and the first-layer wiring 29B and the pad layer 23 are connected.
It is connected via B to _one of the source region and the drain region of the transfer MISFETs Qt ₁ and Qt ₂ .

The second-layer wiring 36 is composed of, for example, a three-layer metal film in which a barrier metal film, an aluminum alloy film, and a barrier metal film are sequentially laminated. The barrier metal is made of, for example, TiW, and the aluminum alloy is made of, for example, aluminum to which Cu and Si are added. The interlayer insulating film 34 is formed of, for example, a three-layer insulating film in which a silicon oxide film, a spin-on-glass (SOG) film, and a silicon oxide film are sequentially stacked.

A final passivation film 37 is formed on the second wiring 36. The final passivation film 37 is made of, for example, a laminated film of a silicon oxide film and a silicon nitride film.

Next, a method of manufacturing the memory cell MC ₁ of the present embodiment configured as described above will be described with reference to FIGS. 11, 17 and 18.

First, as shown in FIG. 17, a p ^-- type well 2 is formed in a part of the formation region of the memory cell array and the peripheral circuit (not shown) of the semiconductor substrate 1 made of n ^-- type silicon single crystal by a known method. To form. Next, a field insulating film 4 for element isolation is formed on the main surface of the inactive region of the p ⁻ type well 2. At this time, the p-type channel stopper region 5 for preventing inversion is formed under the field insulating film 4.

Next, after BF ₂ is ion-implanted into the main surface of the active region of the p ⁻ type well 2 to adjust the threshold voltage of the driving MISFETs Qd ₁ and Qd ₂ , the driving MISF is performed.
The gate insulating film 6 of ETQd ₁ and Qd ₂ is formed. This gate insulating film 6 is formed by a thermal oxidation method.

Next, a polycrystalline silicon film (not shown) in which P is introduced is deposited on the entire surface of the semiconductor substrate 1 by the CVD method. This polycrystalline silicon film is the gate material of the first layer. Next, the insulating film 8 made of a silicon oxide film is deposited on the polycrystalline silicon film by the CVD method. The insulating film 8 is formed to electrically separate the gate electrodes 7 of the driving MISFETs Qd ₁ and Qd ₂ from the conductive layer formed thereabove.

Next, by using the photoresist film as a mask, the insulating film 8 and the polycrystalline silicon film thereunder are sequentially etched to drive the MISFETs Qd ₁ and Qd _2.
Is formed. Next, the silicon oxide film (not shown) deposited on the entire surface of the semiconductor substrate 1 is removed by RIE (Re
The sidewall spacers 9 are formed on the sidewalls of the gate electrodes 7 of the driving MISFETs Qd ₁ and Qd ₂ by performing anisotropic etching such as active ion etching.

Next, after forming a photoresist film on the main surface of the semiconductor substrate 1, this is used as a mask for the above-mentioned drive MI.
P and arsenic (As) are ion-implanted into the main surface of the p ⁻ type well _{2 in} the formation region of the SFETs Qd ₁ and Qd ₂ , and the P and As are expanded and diffused to drive MISF.
An n ⁻ type semiconductor region 10 and an n ⁺ type semiconductor region 11 of ETQd ₁ and Qd ₂ are formed. As a result, the driving MISFETs Qd ₁ and Qd ₂ having the source region and the drain region of the double diffused drain structure are completed.

Next, the main surface of the active region is cleaned by etching with a dilute hydrofluoric acid solution to transfer MISFETs Qt ₁ and Qt.
The gate insulating film 12 of t ₂ is formed. Next, a photoresist film is formed on the main surface of the semiconductor substrate 1, and using this as a mask, an insulating film (insulating the same layer as the gate insulating film 12 on the n ⁺ type semiconductor region 11 of the driving MISFETs Qd ₁ and Qd ₂ is formed). Contact hole 1 by etching the film)
4 is formed.

Next, a second-layer gate material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This gate material is composed of a laminated film (polycide film) of a polycrystalline silicon film into which P is introduced and a tungsten silicide film.

Next, an insulating film 15 made of a silicon oxide film is deposited on the tungsten silicide film. The insulating film 15 is formed to electrically separate the gate insulating film 12 of the transfer MISFETs Qt ₁ and Qt ₂ from the conductive layer formed thereabove.

Next, a photoresist film is formed on the insulating film 15, and the insulating film 15 and the second-layer gate material (polycide film) underlying the insulating film 15 are sequentially etched and transferred using the photoresist film as a mask. The gate electrodes 13A, the word lines WL, and the reference voltage line (V _SS ) 13B of the MISFETs Qt ₁ and Qt ₂ are formed.

Next, after forming a photoresist film on the main surface of the semiconductor substrate 1, this is used as a mask to transfer MISF.
P is ion-implanted into the main surface of the p ⁻ type well _{2 in} the formation region of ETQt ₁ and Qt ₂ , and the P is expanded and diffused to transfer MI.
The n ⁻ type semiconductor region 17 of the SFETs Qt ₁ and Qt ₂ is formed.

Next, the silicon oxide film (not shown) deposited on the entire surface of the semiconductor substrate 1 by the CVD method is etched by anisotropic etching such as RIE to transfer MISFET.
Sidewall spacers 16 are formed on the respective side walls of the gate electrodes 13A of Qt ₁ and Qt ₂ , the word line WL, and the reference voltage line (V _SS ) 13B.

Next, using the photoresist film formed on the main surface of the semiconductor substrate 1 as a mask, the transfer MISFET Qt ₁ ,
Arsenic (A) is formed on the main surface of the p ⁻ type well 2 in the Qt ₂ formation region.
s) is ion-implanted to transfer MISFETs Qt ₁ , Qt ₂
Then, the n ⁺ type semiconductor region 18 is formed.

Since the n ⁻ type semiconductor region 17 is formed in advance on the main surface of the p ⁻ type well _{2 in} the formation region of the transfer MISFETs Qt ₁ and Qt ₂ , the n ⁺ type semiconductor region 1 is formed.
By forming 8, the transfer MISFETs Qt ₁ and Qt ₂ having the source region and the drain region of the LDD structure are completed.

Next, as shown in FIG. 18, the semiconductor substrate 1
An insulating film 21 made of a silicon oxide film is deposited on the entire surface of the substrate by the CVD method. Next, a photoresist film is formed on the insulating film 21, and the insulating film 21 and the insulating film 8 are etched using the photoresist film as a mask to thereby form the driving MISFET Q.
The gate electrode 7 (Qd ₁ ) of d ₁ and the transfer MISFET Qt
_A contact hole 22 is formed on _one of the source region and the drain region of _{No. 2 and on} the gate electrode 7 (Qd ₂ ) of the driving MISFET Qd ₂ and _one of the source region and the drain region of the transfer MISFET Qt ₁ .

At the same time, the insulating film 21 is etched by using the photoresist film as a mask to form the contact hole 22 on the other upper part of the source region and the drain region of the transfer MISFETs Qt ₁ and Qt ₂ .

Next, a polycrystalline silicon film (not shown) in which P is introduced is deposited on the entire surface of the semiconductor substrate 1 by the CVD method.
This polycrystalline silicon film is the gate material of the third layer. Next, by etching the polycrystalline silicon film by using a photoresist film formed on the polycrystalline silicon film as a mask to form load MISFET Qp _1, Qp ₂ of the gate electrode 23A and the pad layer 23B, respectively.

Next, the load MIS is formed on the entire surface of the semiconductor substrate 1.
After depositing the gate insulating film 24 of the FETs Qp ₁ and Qp ₂ by the CVD method, a photoresist film is formed on the gate insulating film 24, and the gate insulating film 24 is used as a mask to etch the gate insulating film 24. MISFET Qp ₁ , Q
A contact hole 25 is formed on the p ₂ gate electrode 23A.
To form

Next, a polycrystalline silicon film (not shown) which is the fourth layer gate material is deposited on the entire surface of the semiconductor substrate 1 by the CVD method. Then, using the photoresist film formed on the polycrystalline silicon film as a mask, the load MISFET is formed.
Qp _1, ion implantation of P into the polycrystalline silicon film in the region for forming a channel region 26N of qp _2.

Next, using the photoresist film newly formed on the polycrystalline silicon film as a mask, the load MISFE is used.
TQp _1, Qp ₂ source region 26P, the drain region 26
BF ₂ is ion-implanted into the polycrystalline silicon film in the region where P and the power supply voltage line (V _CC ) 26P are formed.

Next, the polycrystalline silicon film is etched using the photoresist film newly formed on the polycrystalline silicon film as a mask to etch the channel regions 26N, source regions 26P and drain regions of the load MISFETs Qp ₁ and Qp _2. Two
By forming 6P and the power supply voltage line (V _CC ) 26P, the load MISFETs Qp ₁ and Qp ₂ are completed.

Next, as shown in FIG. 11, the semiconductor substrate 1
An interlayer insulating film 27 made of a silicon oxide film and BPSG is sequentially deposited on the entire surface of the substrate by the CVD method. Next, using the photoresist film formed on the interlayer insulating film 27 as a mask, the interlayer insulating film 27 is etched, and the load MISFE is used.
TQP _1, to form a contact hole 28A in the upper part of the drain region 26P of Qp _2.

At the same time, the interlayer insulating film 27 and the insulating film (the gate insulating film 24 of the load MISFETs Qp ₁ and Qp ₂ ) are sequentially etched and arranged on one of the source and drain regions of the transfer MISFETs Qt ₁ and Qt _2. A contact hole 28B is formed on the formed pad layer 23B.

Next, a first-layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. The wiring material of the first layer is, for example, a tungsten film. Next, the tungsten film is etched by using the photoresist film formed on the tungsten film as a mask, and the first-layer wiring 29A,
29B is formed.

The first-layer wiring 29A is a load MIS.
The drain regions of the FETs Qp ₁ and Qp ₂ are connected through the contact holes 28A, and the wiring 29B of the first layer is connected to the pad layer 23B located above the transfer MISFETs Qt ₁ and Qt ₂ through the contact holes 28B. Has been done.

Next, as shown in FIG. 11, after depositing the first barrier layer 30 on the entire surface of the semiconductor substrate 1, a ferroelectric film serving as a ferroelectric material of the ferroelectric capacitors Cf ₁ and Cf ₂ is formed. 31 is deposited. The first barrier layer 30 is, for example, IrO.
_The ferroelectric film 31 is, for example, a PZT film. The PZT film is formed by, for example, a sputtering method or a spin-on coating method, and its film thickness is about 300 nm.

Then, a second barrier layer 32 and a conductive film (not shown) are deposited. This conductive film is, for example, W and becomes the plate electrode 33 that constitutes the other electrode plate of the ferroelectric capacitors Cf ₁ and Cf ₂ . The second barrier layer 3
2 is, for example, an IrO ₂ film.

Next, the plate electrode 33 is formed by etching the conductive film using the photoresist film formed on the conductive film as a mask. Then, using the same photoresist film as a mask, the second barrier layer 32, the ferroelectric film 31, and the first barrier layer 30 are sequentially etched.

As a result, the load MISFETs Qp ₁ , Q
First-layer wiring 29A connected to the drain region of p ₂
As the one electrode plate, the plate electrode 33 as the other electrode plate, and the ferroelectric capacitor Cf having the ferroelectric film 31 located between the first-layer wiring 29A and the plate electrode 33 as the dielectric material. ₁ and Cf ₂ are completed.

Next, as shown in FIG. 11, the semiconductor substrate 1
Interlayer insulating film 34 consisting of a three-layer film in which a silicon oxide film, a spin-on-glass film, and a silicon oxide film are sequentially laminated on the entire surface of the
Is deposited.

Next, the interlayer insulating film 34 is etched by using the photoresist film formed on the interlayer insulating film 34 as a mask, and the plate electrode 33 and the plate electrode 33, which is one of the plates of the ferroelectric capacitors Cf ₁ and Cf _2. Transfer MISFET Qt
After forming the contact hole 35 in the upper portion of the wiring 29B of the first layer arranged in the upper layer of one of the source region and the drain region of ₁ , Qt ₂ , the wiring material of the second layer ( (Not shown) is deposited.

This wiring material is composed of a three-layer film in which a TiW film, an aluminum alloy film, and a TiW film are sequentially laminated. next,
By sequentially etching the TiW film, the aluminum alloy film, and the TiW film using the photoresist film formed on the TiW film as a mask, the wiring 36 of the second layer (data line D
L) is formed.

Finally, as shown in FIG. 11, the final passivation film 37 is deposited on the semiconductor substrate ₁ to complete the memory cell MC ₁ of this embodiment.

According to this embodiment, the transfer MISFETs Qt ₁ and Qt ₂ and the driving MISFET are formed on the semiconductor substrate 1.
After forming Qd ₁ and Qd ₂ , the transfer MISFET Qt ₁ ,
The load MISFETs Qp ₁ and Qp ₂ are formed on the upper layer of Qt ₂ and the driving MISFETs Qd ₁ and Qd ₂ , and further, _{one of} the ferroelectric capacitors Cf ₁ and Cf ₂ is formed in the drain region 26P of the load MISFETs Qp ₁ and Qp ₂ . Electrode (29
A) is connected to transfer MISFETs Qt ₁ , Qt ₂ ,
Driving MISFETs Qd ₁ , Qd ₂ and load MISF
Ferroelectric capacitors Cf ₁ and C are provided on the upper layers of ETQp ₁ and Qp _2.
Since f ₂ can be formed, a memory cell having a nonvolatile memory function can be obtained without increasing the area of the memory cell of the TFT type SRAM.

(Embodiment 2) Next, a concrete second configuration (memory cell MC ₂ ) of the memory cell MC shown in FIG. 1 is shown in FIG.
This will be described with reference to FIGS.

19 to 21 show ferroelectric capacitors Cf ₁ ,
A plan view of a memory cell MC ₂ provided with Cf ₂ (a plan view of a semiconductor substrate showing approximately one memory cell MC ₂ ) is shown.
22 is a sectional view of the semiconductor substrate taken along the line (b)-(b) 'of FIG. The configuration of the flip-flop circuit of the memory cell MC _{2 is the same as that} of the flip-flop circuit used for the memory cell of the complete CMOS type SRAM.

Six MISFETs constituting a memory cell
Is the field insulating film 10 of the p ⁻ type semiconductor substrate 101.
It is formed in the active region surrounded by 2. Each of the n-channel type driving MISFETs Qd ₁ and Qd ₂ and the transfer MISFETs Qt ₁ and Qt ₂ is formed in the active region of the p-type well 103, and the p-channel type loading MISFETs Qp ₁ and Qp _{2 are formed.} Are formed in the active region of the n-type well 104. p-type well 10
3, the n-type well 104 is the semiconductor substrate 101.
It is formed on the main surface of the p-type epitaxial silicon layer 105 formed above.

As shown in FIG. 19, transfer MISFET
Qt ₁ and Qt ₂ have a gate electrode 106 integrally formed with the word line WL. The gate electrode 106 (word line WL) is formed of a polycrystalline silicon film (or a polycide film in which a polycrystalline silicon film and a refractory metal silicide film are stacked), and is a gate insulating film 107 formed of a silicon oxide film. Formed on.

Although not shown, the source region and drain region of each of the transfer MISFETs Qt ₁ and Qt ₂ are formed in the active region of the p-type well 103 and have a low impurity concentration n ⁻ type semiconductor region and a high impurity concentration. Of n ⁺ type semiconductor regions. That is, the transfer MISF
Each of the source region and the drain region of ETQt ₁ and Qt ₂ has an LDD structure.

The drive MISFET Qd ₁ and the load MISFET Qp ₁ which form one CMOS inverter of the flip-flop circuit have a common gate electrode 110A.
And a drive MISFET Qd ₂ and a load MISFET Qp which form the other CMOS inverter.
₂ has a common gate electrode 110B.

These gate electrodes 110A and 110B
Is made of the same polycrystalline silicon film as the gate electrodes 106 (word lines WL) of the transfer MISFETs Qt ₁ and Qt ₂ and is formed on the gate insulating film 107. Gate electrode 106 (word line WL) and gate electrode 110
An n-type impurity (for example, P) is introduced into the polycrystalline silicon film forming A and 110B.

The source region and drain region of each of the driving MISFETs Qd ₁ and Qd ₂ are a low impurity concentration n ⁻ type semiconductor region 108 and a high impurity concentration n ⁺ type semiconductor formed in the active region of the p type well 103. It is composed of a region 109. That is, the driving MISFET Qd ₁ ,
The source and drain regions of Qd ₂ are LD
It has a D structure.

Although not shown, the source region and the drain region of each of the load MISFETs Qp ₁ and Qp ₂ are formed in the active region of the n-type well 104 and have a low impurity concentration p ⁻ type semiconductor region and a high impurity concentration. It is composed of a heavily doped p ⁺ type semiconductor region. That is, the load MISF
Each of the source region and the drain region of ETQp ₁ and Qp ₂ has an LDD structure.

The insulating film 11 is formed on the gate electrode (word line) 106 and the gate electrodes 110A and 110B.
1 is formed. The insulating film 111 is made of, for example, a silicon oxide film. As shown in FIGS. 20 and 22, a driving MIS located on the field insulating film 102.
The ferroelectric capacitor C is provided above the common gate electrode 110A of the FET Qd ₁ and the load MISFET Qp _1.
A conductive film 114A that serves as one electrode plate of f ₁ is formed.

Similarly, the drive MISFET Qd ₂ and the load MISFE located on the field insulating film 102.
At the top of the common gate electrode 110B of TQP _2, strong conductive film 114 serves as one plate of the dielectric capacitor Cf ₂
B is formed. The conductive films 114A and 114B are composed of, for example, a laminated film in which a polycrystalline silicon film into which an n-type impurity is introduced and a refractory metal film such as tungsten (W) are sequentially deposited.

The conductive layer 114A, which is one of the plates of the ferroelectric capacitor Cf ₁ , has a driving MISFET through a contact hole 113A formed in the insulating film 111.
It is connected to the common gate electrode 110A of Qd ₁ and the load MISFET Qp ₁ . Similarly, the conductive layer 114B is one plate of the ferroelectric capacitor Cf ₂
Is a contact hole 113 formed in the insulating film 111.
Drive B through MISFET Qd ₂ and load MI
It is connected to the common gate electrode 110B of the SFET Qp ₂ .

[0154] As shown in FIG. 22, the conductive film 1 is a top and strong one plate of dielectric capacitor Cf ₂ of the conductive film 114A which is one plate of the ferroelectric capacitor Cf ₁
A ferroelectric film 116 is formed on the upper layer of 14B via a first barrier layer 115. First barrier layer 115
Is, for example, an IrO ₂ film, and the ferroelectric film 116 is, for example, a PZT film.

Further, a plate electrode 118, which is the other electrode plate of the ferroelectric capacitors Cf ₁ and Cf ₂ , is formed on the upper layer of the ferroelectric film 116 via the second barrier layer 117. The second barrier layer 117 is made of, for example, Ir.
The plate electrode 118 is an O ₂ film and is made of a high melting point metal film such as W.

The first barrier layer 115 and the second barrier layer 117 are composed of the ferroelectric film 116 and the conductive films 114A and 114B located therebelow, and the ferroelectric film 116 and the plate electrode 118 located above it. Is provided to prevent it from reacting.

As shown in FIGS. 21 and 22, the first layer interlayer insulating film 119 is formed on the plate electrode 118.
The wirings 121A and 121B of the first layer are arranged via the. The interlayer insulating film 119 is formed of, for example, a laminated film of a silicon oxide film and a BPSG film, and the first-layer wiring 12
1A and 121B are composed of, for example, a W film.

The contact hole 120A is formed in the interlayer insulating film 119 on the drain region of the driving MISFET Qd _1.
There are apertures, also in the interlayer insulating film 119 on the common gate electrode 110B of the drain region and the driving MISFET Qd ₂ and load MISFET Qp ₂ for load MISFET Qp _1, a contact hole 120B are apertures .

Similarly, the drain region of the drive MISFET Qd ₂ and the drive MISFET Qd ₁ and the load MI.
A contact hole 120C is opened in the interlayer insulating film 119 on the common gate electrode 110A of the SFET Qp ₁ , and the contact hole 120 is formed in the interlayer insulating film 119 on the drain region of the load MISFET Qp _2.
D is perforated.

Therefore, the drive MIS is formed by the first-layer wiring 121A formed on the interlayer insulating film 119.
Drain region of FET Qd ₁ , load MISFET Qp
_1, the drain region ₁ , the common gate electrode 110B of the driving MISFET Qd ₂ and the load MISFET Qp ₂ and _one of the source region and the drain region of the transfer MISFET Qt ₁ are electrically connected.

Similarly, the drain region of the drive MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ , and the drive MISFE are formed by the wiring 121B of the first layer.
The common gate electrode 110A of the TQd ₁ and the load MISFET Qp ₁ and _one of the source region and the drain region of the transfer MISFET Qt ₂ are electrically connected.

Although not shown, a second-layer wiring is formed on the upper layers of the first-layer wirings 121A and 121B via a second-layer interlayer insulating film. The wiring of the second layer constitutes the data lines DL ₁ and DL ₂ , and the data lines DL ₁ and DL ₂ are used for transfer through the contact holes 122A formed in the interlayer insulating film of the second layer. MISFET
It is connected to the source region and the drain region of Qt ₁ and Qt ₂ .

The wiring of the second layer is the reference voltage line (V
_SS ), and the driving MISFE is formed through the contact hole 122B formed in the second interlayer insulating film.
It is connected to the source regions of TQd ₁ and Qd ₂ . Further, the wiring of the second layer constitutes the power supply voltage ( _VL ) and is connected to the source region of the load MISFETs Qp ₁ and Qp ₂ through the contact hole 122C opened in the interlayer insulating film of the second layer. It is connected.

Next, a method of manufacturing the memory cell MC ₂ of this embodiment having the above structure will be described. Note that the cross-sectional view of FIG. 22 showing the manufacturing method of this memory cell is the same as that of FIG.
It corresponds to the (b)-(b) 'line of 1.

First, the p type epitaxial silicon layer 1 is formed on the semiconductor substrate 101 made of p ⁻ type single crystal silicon.
After growing 05, the field insulating film 102 is formed on the main surface of the semiconductor substrate 101. Then, the p-type well 103 and the n-type well 1044 are formed in the semiconductor substrate 101 by a known method. Next, the field insulating film 10
P-type well 103 and n-type well 104 surrounded by 2
A gate insulating film 107 made of a thin silicon oxide film is formed on each of the main surfaces.

Next, the gate electrodes 106 (word lines WL) of the transfer MISFETs Qt ₁ and Qt ₂ and the drive MI.
SFETs Qd ₁ and Qd ₂ and load MISFETs Qp ₁ and Qp
_{The second} gate electrodes 110A and 110B are formed.

The gate electrode 106 (word line WL) and the gate electrodes 110A and 110B are formed by depositing a polycrystalline silicon film in which P is introduced by the CVD method on the entire surface of the semiconductor substrate 1 and then forming a silicon oxide film by the CVD method thereon. Insulating film 111
Is deposited, and the insulating film 111 and the polycrystalline silicon film are patterned by dry etching using the photoresist film as a mask.

Next, an n-type impurity (P, A) is introduced into the p-type well 103 by ion implantation using the photoresist film as a mask.
s), and p-type impurities (BF ₂ ) are introduced into the n-type well 104. Next, after removing the photoresist film, the silicon oxide film deposited by the CVD method on the entire surface of the semiconductor substrate 101 is patterned by RIE to form the gate electrode 106 (word line WL) and the gate electrodes 110A and 110B, respectively. Sidewall spacers 112 are formed on the side walls.

Next, by ion implantation using the photoresist film as a mask, n-type impurities (P, A
s), and p-type impurities (BF ₂ ) are introduced into the n-type well 104.

Next, after removing the photoresist film, the n-type impurities and the p-type impurities are thermally diffused to form p-type impurities.
Transfer MISFETs Qt ₁ and Qt are formed on the main surface of the well 103.
₂ , the source region and the drain region of each of the driving MISFETs Qd ₁ and Qd ₂ (n ⁻ type semiconductor region 108, n ⁺
Type semiconductor region 109), the load MISFETs Qp ₁ and Qp ₂ are formed on the main surface of the n-type well 104 (not shown).
Source region, drain region (p ⁻ type semiconductor region, p ⁺
Type semiconductor region).

Next, the drive MISFET Qd ₁ and the load MISFET located above the field insulating film 102.
Qp ₁ common gate electrode 110A and driving MIS
Contact holes 113A and 113B are formed in the insulating film 111 covering the common gate electrode 110B of the FET Qd ₂ and the load MISFET Qp ₂ by dry etching to expose a part of each of the gate electrodes 110A and 110B.

Next, as shown in FIG. 22, the semiconductor substrate 1
On the entire surface of 01, a W film that constitutes one of the plates of the ferroelectric capacitors Cf ₁ and Cf ₂ is deposited. Next, the W film is etched using the photoresist film formed on the W film as a mask to form conductive films 114A and 114B, respectively.

The conductive film 114A is a driving MISFE.
The common gate electrode 110A of TQd ₁ and load MISFET Qp ₁ is connected through a contact hole 113A. In addition, the conductive film 114B is a driving MIS.
The FET Qd ₂ and the load MISFET Qp ₂ are connected to a common gate electrode 110B through a contact hole 113B.

Next, after depositing the first barrier layer 115 on the entire surface of the semiconductor substrate 101, the ferroelectric capacitors Cf ₁ ,
A ferroelectric film 116, which is a ferroelectric material of Cf ₂ , is deposited on the entire surface of the semiconductor substrate 101. First barrier layer 115
Is, for example, an IrO ₂ film, and the ferroelectric film is, for example, P
It is a ZT film.

The PZT film is formed by, for example, a sputtering method or a spin-on coating method, and its film thickness is 30.
It is about 0 nm. The first barrier layer 115 is provided to prevent reaction between the ferroelectric film 116 and the conductive films 114A and 114B.

Then, a second barrier layer 117 and a conductive film (not shown) are deposited. This conductive film serves as a plate electrode 118 that constitutes the other electrode plate of the ferroelectric capacitors Cf ₁ and Cf ₂ . The second barrier layer 117 is, for example, an IrO ₂ film, and the conductive film is made of W.
The second barrier layer 117, like the first barrier layer 115, is provided to prevent the reaction between the ferroelectric film 116 and the plate electrode 118.

Next, the plate electrode 118 is completed by etching the conductive film using the photoresist film formed on the conductive film as a mask.

Then, using the same photoresist film as a mask, the second barrier layer 117, the ferroelectric film 116 and the first barrier film 115 are sequentially etched. As a result, the driving MISFET Qd ₁ and the load MISFET
The conductive film 114A connected to the common gate electrode 110A of Qp ₁ serves as one electrode plate and the plate electrode 118 serves as the other electrode plate, and the ferroelectric film 116 located between the conductive film 114A and the plate electrode 118. A ferroelectric capacitor Cf ₂ using as a ferroelectric material is completed.

Similarly, the conductive film 114B connected to the common gate electrode 110B of the driving MISFET Qd ₂ and the load MISFET Qp ₂ is used as one electrode plate, the plate electrode 118 is used as the other electrode plate, and the conductive film 114B and the plate are connected. A ferroelectric capacitor Cf ₁ using the ferroelectric film 116 located between the electrodes 118 as a ferroelectric material is completed.

Next, an interlayer insulating film 119 in which a silicon oxide film and a BPSG film are sequentially deposited is formed on the entire surface of the semiconductor substrate 101. Next, the interlayer insulating film 119 is etched using the photoresist film formed on the interlayer insulating film 119 as a mask. By this, the load MISFET Q
A common contact hole 120B is formed on the drain region of p ₁ and on the common gate electrode 110B of the driving MISFET Qd ₂ and the load MISFET Qp ₂ .

Similarly, on the drain region of the driving MISFET Qd ₂ , the driving MISFET Qd ₁ and the load MIS are formed.
A common contact hole 120C is formed on the common gate electrode 110A of the FET Qp ₁ . Also, the drive MI
_On the drain region of SFET Qd ₁ and for load MISF
A contact hole 12 is also formed on the drain region of ETQp _2.
0A and 120D are formed, respectively.

Next, a conductive film (not shown) is deposited on the entire surface of the semiconductor substrate 101. This conductive film is, for example, a W film. The conductive film is etched using the photoresist film formed on this conductive film as a mask. by this,
Drain region of drive MISFET Qd ₁ , load MI
Drain region of SFETQp ₁ , driving MISFETQ
Common gate electrode 1 of d ₂ and load MISFET Qp ₂
First-layer wiring 121A connecting 10B is formed.

Similarly, the drain region of the driving MISFET Qd ₂ , the drain region of the load MISFET Qp ₂ ,
Drive MISFET Qd ₁ and load MISFET Qp ₁
Wiring 121B of the first layer for connecting the common gate electrode 110A is formed.

Next, a second interlayer insulating film (not shown) consisting of a three-layer film in which a silicon oxide film, an SOG film, and a silicon oxide film are sequentially deposited is deposited on the entire surface of the semiconductor substrate 1.

After that, contact holes 122A, 122B and 122C are formed in the second interlayer insulating film by dry etching using the photoresist film as a mask. The contact hole 122A has a transfer MISFET Qt.
₁ and Qt ₂ are formed on one of the source region and the drain region, and the contact hole 122B is for driving M.
ISFETQd _1, the upper portion of the source region of Qd _2, contact holes 122C are formed on the source region of the load MISFETQp _1, Qp _2.

Next, a second layer wiring material (not shown) is deposited on the entire surface of the semiconductor substrate 1. This wiring material is, for example, an aluminum alloy film. Next, the aluminum alloy film is patterned by dry etching using the photoresist film as a mask to form the data lines DL ₁ and DL ₂ .
Further, a power supply voltage ( _VL ) and a reference voltage line ( _VSS ) are formed.

Finally, a final passivation film is deposited on the second-layer wiring to complete the memory cell MC ₂ of this embodiment.

According to this embodiment, the driving MISFET Q is
d ₁ and the common gate electrode 1 of the load MISFET Qp ₁
The conductive film 114A, which is one of the plates of the ferroelectric capacitor Cf ₁ , is connected to 10A to drive the MISFETQ.
d ₁ and the common gate electrode 1 of the load MISFET Qp ₁
A ferroelectric capacitor Cf ₁ can be formed on the upper layer of 10A,
Similarly, the drive MISFET Qd ₂ and the load MI
The common gate electrode 110B of the SFET Qp ₂ is provided with the conductive film 114B which is one of the plates of the ferroelectric capacitor Cf _2.
To connect the drive MISFET Qd ₂ and the load MI.
Since the ferroelectric capacitor Cf ₂ can be formed in the upper layer of the common gate electrode 110B of the SFET Qp ₂ , a memory cell having a non-volatile memory function can be obtained without increasing the area of the SRAM memory cell.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, although the PZT film is used as the ferroelectric material of the ferroelectric capacitor in the above embodiment, a material that spontaneously generates polarization without applying an electric field, such as PLZ.
A T (PbLaZrTiO ₃ ) film or a BaTiO ₃ film can be used as a ferroelectric material.

Further, in the above-mentioned embodiment, the IrO ₂ film is used as the barrier layer for preventing the reaction between the ferroelectric material of the ferroelectric capacitor and the electrode, but the present invention is not limited to this, and platinum (Pt) is used. A film or a laminated film of a Pt film and a TiN film may be used.

[0192]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

According to the present invention, a ferroelectric capacitor capable of retaining information in the storage node of the flip-flop circuit can be connected to the flip-flop circuit without increasing the area of the memory cell, so that high integration having a nonvolatile memory function is achieved. RAM can be realized.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 4 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 6 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 7 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 8 is an equivalent circuit diagram of a memory cell showing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 9 is a timing diagram of switching of a power supply voltage and a plate voltage of a flip-flop circuit.

FIG. 10 is a diagram showing a change in voltage at a storage node of a flip-flop circuit.

FIG. 11 is a cross-sectional view of a main part of a semiconductor substrate showing a memory cell of a semiconductor integrated circuit device according to an embodiment of the present invention (a cross-section of the main part of the semiconductor substrate taken along line (a)-(a) ′ of FIG. 16). Figure).

FIG. 12 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is an embodiment of the present invention;

FIG. 13 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is an embodiment of the present invention;

FIG. 14 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is an embodiment of the present invention;

FIG. 15 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is an embodiment of the present invention;

FIG. 16 is a main-portion plan view showing the pattern layout of the memory cells of the semiconductor integrated circuit device which is an embodiment of the present invention;

FIG. 17 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention (of the semiconductor substrate taken along the line (a)-(a) ′ in FIG. 16). (Partial cross-sectional view).

FIG. 18 is a cross-sectional view of essential parts of a semiconductor substrate showing a method for manufacturing a memory cell of a semiconductor integrated circuit device which is an embodiment of the present invention (of the semiconductor substrate taken along the line (a)-(a) ′ in FIG. 16). (Partial cross-sectional view).

FIG. 19 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 20 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is another embodiment of the present invention;

FIG. 21 is a main-portion plan view showing a pattern layout of memory cells in a semiconductor integrated circuit device which is another embodiment of the present invention;

22 is a cross-sectional view of a main portion of a semiconductor substrate showing a memory cell of a semiconductor integrated circuit device according to another embodiment of the present invention (the main portion of the semiconductor substrate taken along the line (b)-(b) ′ in FIG. 21). Sectional view).

FIG. 23 is a diagram showing a hysteresis loop of a ferroelectric film of a semiconductor integrated circuit device which is another embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate (semiconductor chip) 2 p ⁻ type well 3 region 4 field insulating film 5 p type channel stopper region 6 gate insulating film 7 gate electrode 8 insulating film 9 sidewall spacer 10 n ⁻ type semiconductor region 11 n ⁺ type semiconductor region 12 Gate Insulating Film 13A Gate Electrode 13B Reference Voltage Line (V _SS ) 14 Contact Hole 15 Insulating Film 16 Sidewall Spacer 17 n ⁻ Type Semiconductor Region 18 n ⁺ Type Semiconductor Region 21 Insulating Film 22 Contact Hole 23A Gate Electrode 23B Pad Layer 24 Gate insulating film 25 Contact hole 26N Channel region 26P Source region 26P Drain region 26P Power supply voltage line ( _VL ) 27 Interlayer insulating film 28A Contact hole 28B Contact hole 29A First layer wiring 29B First layer wiring 30 First Bali A layer 31 ferroelectric film 32 second barrier layer 33 plate electrode 34 interlayer insulating film 35 contact hole 36 second layer wiring 37 final passivation film 101 semiconductor substrate 102 field insulating film 103 p-type well 104 n-type well 105 p-type epitaxial silicon layer 106 gate electrode 107 gate insulating film 108 n ⁻ type semiconductor region 109 n ⁺ type semiconductor region 110A gate electrode 110B gate electrode 111 insulating film 112 sidewall spacer 113A contact hole 113B contact hole 114A conductive film 114B conductive film 115 First barrier layer 116 Ferroelectric film 117 Second barrier layer 118 Plate electrode 119 Interlayer insulating film 120A Contact hole 120B Contact hole 120C Contact Hall 120D contact hole 121A of the first layer wiring 121B first wiring layer 122A contact hole 122B contact hole 122C contact hole Cf ₁ ferroelectric capacitor Cf ₂ ferroelectric capacitors DL data lines DL ₁ first data line DL ₂ Second data line MC memory cell MC ₁ memory cell MC ₂ memory cell Qd ₁ driving MISFET Qd ₂ driving MISFET Qp ₁ load MISFET Qp ₂ load MISFET Qt ₁ transfer MISFET Qt ₂ transfer MISFET WL word line N ₁ Storage node N ₂ Storage node N ₃ node _VL Power supply voltage _VP Plate voltage

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 21/8242 H01L 29/78 371 29/78 21/8247 29/788 29/792 (72) Invention Hisao Asakura 2326 Imai, Ome-shi, Tokyo Inside Hitachi, Ltd. Device Development Center

Claims (13)

[Claims] 1. A semiconductor integrated circuit device having a nonvolatile memory function, comprising a flip-flop circuit and two ferroelectric capacitors respectively connected to two storage nodes of the flip-flop circuit. A semiconductor integrated circuit device, comprising: 2. A semiconductor integrated circuit device having a non-volatile memory function, wherein the transfer MIS is controlled by a word line.
A semiconductor having an SRAM memory cell composed of an FET and a flip-flop circuit and a memory cell composed of two ferroelectric capacitors connected to each of the two storage nodes of the flip-flop circuit. Integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the flip-flop circuit is a load M.
It is composed of a pair of cross-coupled CMOS transistors composed of an ISFET and a driving MISFET, and further has a first node coupled to a first operating voltage source, a second node coupled to a reference voltage source, and the two nodes. Of the two ferroelectric capacitors, one plate of each of the two ferroelectric capacitors is connected to the storage node of the flip-flop circuit, and the other of the two ferroelectric capacitors is Is connected to a third node coupled to the second operating voltage source, the semiconductor integrated circuit device. 4. The semiconductor integrated circuit device according to claim 1, wherein the ferroelectric capacitor is formed above the load MISFET and the drive MISFET forming the flip-flop circuit. Semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 2, wherein the ferroelectric capacitor is formed above the load MISFET and the drive MISFET forming the transfer MISFET and the flip-flop circuit. And a semiconductor integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the transfer MI is provided on a main surface of a semiconductor substrate.
After forming the SFET and the driving MISFET,
Forming the load MISFET having a bottom gate structure above the drive MISFET;
Forming a contact hole reaching the silicon film in an insulating film deposited on the silicon film forming the drain region of the SFET; depositing a first conductive film on the semiconductor substrate; Processing the conductive film to form one plate of the ferroelectric capacitor connected to the silicon film, after sequentially depositing the ferroelectric film and the second conductive film on the semiconductor substrate, A method of manufacturing a semiconductor integrated circuit device, comprising the step of processing the second conductive film to form the other electrode plate of the ferroelectric capacitor, and then processing the ferroelectric film. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the transfer MI is provided on a main surface of a semiconductor substrate.
The driving M having an SFET and a common gate electrode
Forming an ISFET and the load MISFET,
A step of forming a contact hole reaching the silicon film in an insulating film deposited on a silicon film forming a common gate electrode of the driving MISFET and the load MISFET; and a first conductive film on the semiconductor substrate. And then processing the first conductive film to form one plate of the ferroelectric capacitor connected to the silicon film, the ferroelectric film and the second film on the semiconductor substrate. After sequentially depositing conductive films, the second conductive film is processed to form the other plate of the ferroelectric capacitor, and then,
A method of manufacturing a semiconductor integrated circuit device, comprising the step of processing the ferroelectric film. 8. The semiconductor integrated circuit device according to claim 1, 2 or 3, wherein the flip-flop circuit comprises the flip-flop circuit.
The information stored in each of the storage nodes is read out and stored in each of the ferroelectric capacitors connected to the storage node when the power of the memory cell is turned off. Information stored in each of the dielectric capacitors is written to each of the storage nodes of the flip-flop circuits to which the ferroelectric capacitors are connected when the power of the memory cell is turned on. apparatus. 9. The semiconductor integrated circuit device according to claim 8, wherein the flip-flop circuit has a first voltage at which a ferroelectric film forming the ferroelectric capacitor does not cause polarization inversion. Said first node connected
Is set to the operating voltage source, the flip-flop circuit is operated, and either the second voltage or the reference voltage at which the ferroelectric film forming the ferroelectric capacitor causes polarization inversion is applied. The third operating node is connected to the first operating voltage source to which the first node of the flip-flop circuit is connected or to the other plate of the ferroelectric capacitor. By setting the operating voltage source of No. 2 to control the polarization state of the ferroelectric film, information reading and writing operations between the flip-flop circuit and the ferroelectric capacitor are performed. Integrated circuit device. 10. The semiconductor integrated circuit device according to claim 8, wherein the information stored in the ferroelectric capacitors respectively connected to the two storage nodes of the flip-flop circuit is the ferroelectric substance. A semiconductor integrated circuit device, which is set according to a polarization direction of a ferroelectric film forming a capacitor. 11. The semiconductor integrated circuit device according to claim 8, wherein the information stored in the ferroelectric capacitors respectively connected to the two storage nodes of the flip-flop circuit is one of the ferroelectric capacitors. By amplifying the potential difference between the two storage nodes of the flip-flop circuit caused by the inversion of the dielectric capacitor, the storage node of the flip-flop circuit connected to each of the ferroelectric capacitors is amplified. A semiconductor integrated circuit device characterized by being respectively written. 12. The semiconductor integrated circuit device according to claim 9, wherein the second voltage is higher than the first voltage. 13. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the ferroelectric film is PbZ.
rTiO ₃ film, PbLaZrTiO ₃ film or BaTi
A method for manufacturing a semiconductor integrated circuit device, which is an O ₃ film.